1 //===-- X86CallingConv.td - Calling Conventions X86 32/64 --*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for the X86-32 and X86-64
12 //===----------------------------------------------------------------------===//
14 /// CCIfSubtarget - Match if the current subtarget has a feature F.
15 class CCIfSubtarget<string F, CCAction A>
16 : CCIf<!strconcat("static_cast<const X86Subtarget&>"
17 "(State.getMachineFunction().getSubtarget()).", F),
20 /// CCIfNotSubtarget - Match if the current subtarget doesn't has a feature F.
21 class CCIfNotSubtarget<string F, CCAction A>
22 : CCIf<!strconcat("!static_cast<const X86Subtarget&>"
23 "(State.getMachineFunction().getSubtarget()).", F),
26 // Register classes for RegCall
27 class RC_X86_RegCall {
28 list<Register> GPR_8 = [];
29 list<Register> GPR_16 = [];
30 list<Register> GPR_32 = [];
31 list<Register> GPR_64 = [];
32 list<Register> FP_CALL = [FP0];
33 list<Register> FP_RET = [FP0, FP1];
34 list<Register> XMM = [];
35 list<Register> YMM = [];
36 list<Register> ZMM = [];
39 // RegCall register classes for 32 bits
40 def RC_X86_32_RegCall : RC_X86_RegCall {
41 let GPR_8 = [AL, CL, DL, DIL, SIL];
42 let GPR_16 = [AX, CX, DX, DI, SI];
43 let GPR_32 = [EAX, ECX, EDX, EDI, ESI];
44 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
45 ///< \todo Fix AssignToReg to enable empty lists
46 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7];
47 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7];
48 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7];
51 class RC_X86_64_RegCall : RC_X86_RegCall {
52 let XMM = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
53 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15];
54 let YMM = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
55 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15];
56 let ZMM = [ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7,
57 ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15];
60 def RC_X86_64_RegCall_Win : RC_X86_64_RegCall {
61 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R10B, R11B, R12B, R14B, R15B];
62 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R10W, R11W, R12W, R14W, R15W];
63 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R10D, R11D, R12D, R14D, R15D];
64 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
67 def RC_X86_64_RegCall_SysV : RC_X86_64_RegCall {
68 let GPR_8 = [AL, CL, DL, DIL, SIL, R8B, R9B, R12B, R13B, R14B, R15B];
69 let GPR_16 = [AX, CX, DX, DI, SI, R8W, R9W, R12W, R13W, R14W, R15W];
70 let GPR_32 = [EAX, ECX, EDX, EDI, ESI, R8D, R9D, R12D, R13D, R14D, R15D];
71 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
74 // X86-64 Intel regcall calling convention.
75 multiclass X86_RegCall_base<RC_X86_RegCall RC> {
76 def CC_#NAME : CallingConv<[
77 // Handles byval parameters.
78 CCIfSubtarget<"is64Bit()", CCIfByVal<CCPassByVal<8, 8>>>,
79 CCIfByVal<CCPassByVal<4, 4>>,
81 // Promote i1/i8/i16/v1i1 arguments to i32.
82 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
84 // Promote v8i1/v16i1/v32i1 arguments to i32.
85 CCIfType<[v8i1, v16i1, v32i1], CCPromoteToType<i32>>,
87 // bool, char, int, enum, long, pointer --> GPR
88 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
90 // long long, __int64 --> GPR
91 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
93 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
94 CCIfType<[v64i1], CCPromoteToType<i64>>,
95 CCIfSubtarget<"is64Bit()", CCIfType<[i64],
96 CCAssignToReg<RC.GPR_64>>>,
97 CCIfSubtarget<"is32Bit()", CCIfType<[i64],
98 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>,
100 // float, double, float128 --> XMM
101 // In the case of SSE disabled --> save to stack
102 CCIfType<[f32, f64, f128],
103 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
105 // long double --> FP
106 CCIfType<[f80], CCAssignToReg<RC.FP_CALL>>,
108 // __m128, __m128i, __m128d --> XMM
109 // In the case of SSE disabled --> save to stack
110 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
111 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
113 // __m256, __m256i, __m256d --> YMM
114 // In the case of SSE disabled --> save to stack
115 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
116 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,
118 // __m512, __m512i, __m512d --> ZMM
119 // In the case of SSE disabled --> save to stack
120 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
121 CCIfSubtarget<"hasAVX512()",CCAssignToReg<RC.ZMM>>>,
123 // If no register was found -> assign to stack
125 // In 64 bit, assign 64/32 bit values to 8 byte stack
126 CCIfSubtarget<"is64Bit()", CCIfType<[i32, i64, f32, f64],
127 CCAssignToStack<8, 8>>>,
129 // In 32 bit, assign 64/32 bit values to 8/4 byte stack
130 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
131 CCIfType<[i64, f64], CCAssignToStack<8, 4>>,
133 // MMX type gets 8 byte slot in stack , while alignment depends on target
134 CCIfSubtarget<"is64Bit()", CCIfType<[x86mmx], CCAssignToStack<8, 8>>>,
135 CCIfType<[x86mmx], CCAssignToStack<8, 4>>,
137 // float 128 get stack slots whose size and alignment depends
139 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,
141 // Vectors get 16-byte stack slots that are 16-byte aligned.
142 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
143 CCAssignToStack<16, 16>>,
145 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
146 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
147 CCAssignToStack<32, 32>>,
149 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
150 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
151 CCAssignToStack<64, 64>>
154 def RetCC_#NAME : CallingConv<[
155 // Promote i1, v1i1, v8i1 arguments to i8.
156 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>,
158 // Promote v16i1 arguments to i16.
159 CCIfType<[v16i1], CCPromoteToType<i16>>,
161 // Promote v32i1 arguments to i32.
162 CCIfType<[v32i1], CCPromoteToType<i32>>,
164 // bool, char, int, enum, long, pointer --> GPR
165 CCIfType<[i8], CCAssignToReg<RC.GPR_8>>,
166 CCIfType<[i16], CCAssignToReg<RC.GPR_16>>,
167 CCIfType<[i32], CCAssignToReg<RC.GPR_32>>,
169 // long long, __int64 --> GPR
170 CCIfType<[i64], CCAssignToReg<RC.GPR_64>>,
172 // __mmask64 (v64i1) --> GPR64 (for x64) or 2 x GPR32 (for IA32)
173 CCIfType<[v64i1], CCPromoteToType<i64>>,
174 CCIfSubtarget<"is64Bit()", CCIfType<[i64],
175 CCAssignToReg<RC.GPR_64>>>,
176 CCIfSubtarget<"is32Bit()", CCIfType<[i64],
177 CCCustom<"CC_X86_32_RegCall_Assign2Regs">>>,
179 // long double --> FP
180 CCIfType<[f80], CCAssignToReg<RC.FP_RET>>,
182 // float, double, float128 --> XMM
183 CCIfType<[f32, f64, f128],
184 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
186 // __m128, __m128i, __m128d --> XMM
187 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
188 CCIfSubtarget<"hasSSE1()", CCAssignToReg<RC.XMM>>>,
190 // __m256, __m256i, __m256d --> YMM
191 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
192 CCIfSubtarget<"hasAVX()", CCAssignToReg<RC.YMM>>>,
194 // __m512, __m512i, __m512d --> ZMM
195 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
196 CCIfSubtarget<"hasAVX512()", CCAssignToReg<RC.ZMM>>>
200 //===----------------------------------------------------------------------===//
201 // Return Value Calling Conventions
202 //===----------------------------------------------------------------------===//
204 // Return-value conventions common to all X86 CC's.
205 def RetCC_X86Common : CallingConv<[
206 // Scalar values are returned in AX first, then DX. For i8, the ABI
207 // requires the values to be in AL and AH, however this code uses AL and DL
208 // instead. This is because using AH for the second register conflicts with
209 // the way LLVM does multiple return values -- a return of {i16,i8} would end
210 // up in AX and AH, which overlap. Front-ends wishing to conform to the ABI
211 // for functions that return two i8 values are currently expected to pack the
212 // values into an i16 (which uses AX, and thus AL:AH).
214 // For code that doesn't care about the ABI, we allow returning more than two
215 // integer values in registers.
216 CCIfType<[v1i1], CCPromoteToType<i8>>,
217 CCIfType<[i1], CCPromoteToType<i8>>,
218 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL]>>,
219 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
220 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
221 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
223 // Boolean vectors of AVX-512 are returned in SIMD registers.
224 // The call from AVX to AVX-512 function should work,
225 // since the boolean types in AVX/AVX2 are promoted by default.
226 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
227 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
228 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
229 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
230 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
231 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
233 // Vector types are returned in XMM0 and XMM1, when they fit. XMM2 and XMM3
234 // can only be used by ABI non-compliant code. If the target doesn't have XMM
235 // registers, it won't have vector types.
236 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
237 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
239 // 256-bit vectors are returned in YMM0 and XMM1, when they fit. YMM2 and YMM3
240 // can only be used by ABI non-compliant code. This vector type is only
241 // supported while using the AVX target feature.
242 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
243 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
245 // 512-bit vectors are returned in ZMM0 and ZMM1, when they fit. ZMM2 and ZMM3
246 // can only be used by ABI non-compliant code. This vector type is only
247 // supported while using the AVX-512 target feature.
248 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
249 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
251 // MMX vector types are always returned in MM0. If the target doesn't have
252 // MM0, it doesn't support these vector types.
253 CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
255 // Long double types are always returned in FP0 (even with SSE),
257 CCIfNotSubtarget<"isTargetWin64()", CCIfType<[f80], CCAssignToReg<[FP0, FP1]>>>
260 // X86-32 C return-value convention.
261 def RetCC_X86_32_C : CallingConv<[
262 // The X86-32 calling convention returns FP values in FP0, unless marked
263 // with "inreg" (used here to distinguish one kind of reg from another,
264 // weirdly; this is really the sse-regparm calling convention) in which
265 // case they use XMM0, otherwise it is the same as the common X86 calling
267 CCIfInReg<CCIfSubtarget<"hasSSE2()",
268 CCIfType<[f32, f64], CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
269 CCIfType<[f32,f64], CCAssignToReg<[FP0, FP1]>>,
270 CCDelegateTo<RetCC_X86Common>
273 // X86-32 FastCC return-value convention.
274 def RetCC_X86_32_Fast : CallingConv<[
275 // The X86-32 fastcc returns 1, 2, or 3 FP values in XMM0-2 if the target has
277 // This can happen when a float, 2 x float, or 3 x float vector is split by
278 // target lowering, and is returned in 1-3 sse regs.
279 CCIfType<[f32], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
280 CCIfType<[f64], CCIfSubtarget<"hasSSE2()", CCAssignToReg<[XMM0,XMM1,XMM2]>>>,
282 // For integers, ECX can be used as an extra return register
283 CCIfType<[i8], CCAssignToReg<[AL, DL, CL]>>,
284 CCIfType<[i16], CCAssignToReg<[AX, DX, CX]>>,
285 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>,
287 // Otherwise, it is the same as the common X86 calling convention.
288 CCDelegateTo<RetCC_X86Common>
291 // Intel_OCL_BI return-value convention.
292 def RetCC_Intel_OCL_BI : CallingConv<[
293 // Vector types are returned in XMM0,XMM1,XMMM2 and XMM3.
294 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
295 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
297 // 256-bit FP vectors
298 // No more than 4 registers
299 CCIfType<[v8f32, v4f64, v8i32, v4i64],
300 CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
302 // 512-bit FP vectors
303 CCIfType<[v16f32, v8f64, v16i32, v8i64],
304 CCAssignToReg<[ZMM0,ZMM1,ZMM2,ZMM3]>>,
306 // i32, i64 in the standard way
307 CCDelegateTo<RetCC_X86Common>
310 // X86-32 HiPE return-value convention.
311 def RetCC_X86_32_HiPE : CallingConv<[
312 // Promote all types to i32
313 CCIfType<[i8, i16], CCPromoteToType<i32>>,
315 // Return: HP, P, VAL1, VAL2
316 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX]>>
319 // X86-32 Vectorcall return-value convention.
320 def RetCC_X86_32_VectorCall : CallingConv<[
321 // Floating Point types are returned in XMM0,XMM1,XMMM2 and XMM3.
322 CCIfType<[f32, f64, f128],
323 CCAssignToReg<[XMM0,XMM1,XMM2,XMM3]>>,
325 // Return integers in the standard way.
326 CCDelegateTo<RetCC_X86Common>
329 // X86-64 C return-value convention.
330 def RetCC_X86_64_C : CallingConv<[
331 // The X86-64 calling convention always returns FP values in XMM0.
332 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
333 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
334 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1]>>,
336 // MMX vector types are always returned in XMM0.
337 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
339 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
341 CCDelegateTo<RetCC_X86Common>
344 // X86-Win64 C return-value convention.
345 def RetCC_X86_Win64_C : CallingConv<[
346 // The X86-Win64 calling convention always returns __m64 values in RAX.
347 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
349 // Otherwise, everything is the same as 'normal' X86-64 C CC.
350 CCDelegateTo<RetCC_X86_64_C>
353 // X86-64 vectorcall return-value convention.
354 def RetCC_X86_64_Vectorcall : CallingConv<[
355 // Vectorcall calling convention always returns FP values in XMMs.
356 CCIfType<[f32, f64, f128],
357 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
359 // Otherwise, everything is the same as Windows X86-64 C CC.
360 CCDelegateTo<RetCC_X86_Win64_C>
363 // X86-64 HiPE return-value convention.
364 def RetCC_X86_64_HiPE : CallingConv<[
365 // Promote all types to i64
366 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
368 // Return: HP, P, VAL1, VAL2
369 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
372 // X86-64 WebKit_JS return-value convention.
373 def RetCC_X86_64_WebKit_JS : CallingConv<[
374 // Promote all types to i64
375 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
378 CCIfType<[i64], CCAssignToReg<[RAX]>>
381 def RetCC_X86_64_Swift : CallingConv<[
383 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
385 // For integers, ECX, R8D can be used as extra return registers.
386 CCIfType<[v1i1], CCPromoteToType<i8>>,
387 CCIfType<[i1], CCPromoteToType<i8>>,
388 CCIfType<[i8] , CCAssignToReg<[AL, DL, CL, R8B]>>,
389 CCIfType<[i16], CCAssignToReg<[AX, DX, CX, R8W]>>,
390 CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX, R8D]>>,
391 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
393 // XMM0, XMM1, XMM2 and XMM3 can be used to return FP values.
394 CCIfType<[f32], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
395 CCIfType<[f64], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
396 CCIfType<[f128], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
398 // MMX vector types are returned in XMM0, XMM1, XMM2 and XMM3.
399 CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
400 CCDelegateTo<RetCC_X86Common>
403 // X86-64 AnyReg return-value convention. No explicit register is specified for
404 // the return-value. The register allocator is allowed and expected to choose
405 // any free register.
407 // This calling convention is currently only supported by the stackmap and
408 // patchpoint intrinsics. All other uses will result in an assert on Debug
409 // builds. On Release builds we fallback to the X86 C calling convention.
410 def RetCC_X86_64_AnyReg : CallingConv<[
411 CCCustom<"CC_X86_AnyReg_Error">
414 // X86-64 HHVM return-value convention.
415 def RetCC_X86_64_HHVM: CallingConv<[
416 // Promote all types to i64
417 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
419 // Return: could return in any GP register save RSP and R12.
420 CCIfType<[i64], CCAssignToReg<[RBX, RBP, RDI, RSI, RDX, RCX, R8, R9,
421 RAX, R10, R11, R13, R14, R15]>>
425 defm X86_32_RegCall :
426 X86_RegCall_base<RC_X86_32_RegCall>;
427 defm X86_Win64_RegCall :
428 X86_RegCall_base<RC_X86_64_RegCall_Win>;
429 defm X86_SysV64_RegCall :
430 X86_RegCall_base<RC_X86_64_RegCall_SysV>;
432 // This is the root return-value convention for the X86-32 backend.
433 def RetCC_X86_32 : CallingConv<[
434 // If FastCC, use RetCC_X86_32_Fast.
435 CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_X86_32_Fast>>,
436 // If HiPE, use RetCC_X86_32_HiPE.
437 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_32_HiPE>>,
438 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_32_VectorCall>>,
439 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_32_RegCall>>,
441 // Otherwise, use RetCC_X86_32_C.
442 CCDelegateTo<RetCC_X86_32_C>
445 // This is the root return-value convention for the X86-64 backend.
446 def RetCC_X86_64 : CallingConv<[
447 // HiPE uses RetCC_X86_64_HiPE
448 CCIfCC<"CallingConv::HiPE", CCDelegateTo<RetCC_X86_64_HiPE>>,
450 // Handle JavaScript calls.
451 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<RetCC_X86_64_WebKit_JS>>,
452 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_X86_64_AnyReg>>,
454 // Handle Swift calls.
455 CCIfCC<"CallingConv::Swift", CCDelegateTo<RetCC_X86_64_Swift>>,
457 // Handle explicit CC selection
458 CCIfCC<"CallingConv::Win64", CCDelegateTo<RetCC_X86_Win64_C>>,
459 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<RetCC_X86_64_C>>,
461 // Handle Vectorcall CC
462 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<RetCC_X86_64_Vectorcall>>,
464 // Handle HHVM calls.
465 CCIfCC<"CallingConv::HHVM", CCDelegateTo<RetCC_X86_64_HHVM>>,
467 CCIfCC<"CallingConv::X86_RegCall",
468 CCIfSubtarget<"isTargetWin64()",
469 CCDelegateTo<RetCC_X86_Win64_RegCall>>>,
470 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<RetCC_X86_SysV64_RegCall>>,
472 // Mingw64 and native Win64 use Win64 CC
473 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<RetCC_X86_Win64_C>>,
475 // Otherwise, drop to normal X86-64 CC
476 CCDelegateTo<RetCC_X86_64_C>
479 // This is the return-value convention used for the entire X86 backend.
481 def RetCC_X86 : CallingConv<[
483 // Check if this is the Intel OpenCL built-ins calling convention
484 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<RetCC_Intel_OCL_BI>>,
486 CCIfSubtarget<"is64Bit()", CCDelegateTo<RetCC_X86_64>>,
487 CCDelegateTo<RetCC_X86_32>
490 //===----------------------------------------------------------------------===//
491 // X86-64 Argument Calling Conventions
492 //===----------------------------------------------------------------------===//
494 def CC_X86_64_C : CallingConv<[
495 // Handles byval parameters.
496 CCIfByVal<CCPassByVal<8, 8>>,
498 // Promote i1/i8/i16/v1i1 arguments to i32.
499 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
501 // The 'nest' parameter, if any, is passed in R10.
502 CCIfNest<CCIfSubtarget<"isTarget64BitILP32()", CCAssignToReg<[R10D]>>>,
503 CCIfNest<CCAssignToReg<[R10]>>,
505 // Pass SwiftSelf in a callee saved register.
506 CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R13]>>>,
508 // A SwiftError is passed in R12.
509 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
511 // For Swift Calling Convention, pass sret in %rax.
512 CCIfCC<"CallingConv::Swift",
513 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>,
515 // The first 6 integer arguments are passed in integer registers.
516 CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
517 CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
519 // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
521 CCIfSubtarget<"isTargetDarwin()",
522 CCIfSubtarget<"hasSSE2()",
523 CCPromoteToType<v2i64>>>>,
525 // Boolean vectors of AVX-512 are passed in SIMD registers.
526 // The call from AVX to AVX-512 function should work,
527 // since the boolean types in AVX/AVX2 are promoted by default.
528 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
529 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
530 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
531 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
532 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
533 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
535 // The first 8 FP/Vector arguments are passed in XMM registers.
536 CCIfType<[f32, f64, f128, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
537 CCIfSubtarget<"hasSSE1()",
538 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>>>,
540 // The first 8 256-bit vector arguments are passed in YMM registers, unless
541 // this is a vararg function.
542 // FIXME: This isn't precisely correct; the x86-64 ABI document says that
543 // fixed arguments to vararg functions are supposed to be passed in
544 // registers. Actually modeling that would be a lot of work, though.
545 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
546 CCIfSubtarget<"hasAVX()",
547 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
548 YMM4, YMM5, YMM6, YMM7]>>>>,
550 // The first 8 512-bit vector arguments are passed in ZMM registers.
551 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
552 CCIfSubtarget<"hasAVX512()",
553 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7]>>>>,
555 // Integer/FP values get stored in stack slots that are 8 bytes in size and
556 // 8-byte aligned if there are no more registers to hold them.
557 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
559 // Long doubles get stack slots whose size and alignment depends on the
561 CCIfType<[f80, f128], CCAssignToStack<0, 0>>,
563 // Vectors get 16-byte stack slots that are 16-byte aligned.
564 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
566 // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
567 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
568 CCAssignToStack<32, 32>>,
570 // 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
571 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
572 CCAssignToStack<64, 64>>
575 // Calling convention for X86-64 HHVM.
576 def CC_X86_64_HHVM : CallingConv<[
577 // Use all/any GP registers for args, except RSP.
578 CCIfType<[i64], CCAssignToReg<[RBX, R12, RBP, R15,
579 RDI, RSI, RDX, RCX, R8, R9,
580 RAX, R10, R11, R13, R14]>>
583 // Calling convention for helper functions in HHVM.
584 def CC_X86_64_HHVM_C : CallingConv<[
585 // Pass the first argument in RBP.
586 CCIfType<[i64], CCAssignToReg<[RBP]>>,
588 // Otherwise it's the same as the regular C calling convention.
589 CCDelegateTo<CC_X86_64_C>
592 // Calling convention used on Win64
593 def CC_X86_Win64_C : CallingConv<[
594 // FIXME: Handle varargs.
596 // Byval aggregates are passed by pointer
597 CCIfByVal<CCPassIndirect<i64>>,
599 // Promote i1/v1i1 arguments to i8.
600 CCIfType<[i1, v1i1], CCPromoteToType<i8>>,
602 // The 'nest' parameter, if any, is passed in R10.
603 CCIfNest<CCAssignToReg<[R10]>>,
605 // A SwiftError is passed in R12.
606 CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R12]>>>,
608 // 128 bit vectors are passed by pointer
609 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect<i64>>,
612 // 256 bit vectors are passed by pointer
613 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], CCPassIndirect<i64>>,
615 // 512 bit vectors are passed by pointer
616 CCIfType<[v64i8, v32i16, v16i32, v16f32, v8f64, v8i64], CCPassIndirect<i64>>,
618 // Long doubles are passed by pointer
619 CCIfType<[f80], CCPassIndirect<i64>>,
621 // The first 4 MMX vector arguments are passed in GPRs.
622 CCIfType<[x86mmx], CCBitConvertToType<i64>>,
624 // The first 4 integer arguments are passed in integer registers.
625 CCIfType<[i8 ], CCAssignToRegWithShadow<[CL , DL , R8B , R9B ],
626 [XMM0, XMM1, XMM2, XMM3]>>,
627 CCIfType<[i16], CCAssignToRegWithShadow<[CX , DX , R8W , R9W ],
628 [XMM0, XMM1, XMM2, XMM3]>>,
629 CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
630 [XMM0, XMM1, XMM2, XMM3]>>,
632 // Do not pass the sret argument in RCX, the Win64 thiscall calling
633 // convention requires "this" to be passed in RCX.
634 CCIfCC<"CallingConv::X86_ThisCall",
635 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[RDX , R8 , R9 ],
636 [XMM1, XMM2, XMM3]>>>>,
638 CCIfType<[i64], CCAssignToRegWithShadow<[RCX , RDX , R8 , R9 ],
639 [XMM0, XMM1, XMM2, XMM3]>>,
641 // The first 4 FP/Vector arguments are passed in XMM registers.
642 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
643 CCAssignToRegWithShadow<[XMM0, XMM1, XMM2, XMM3],
644 [RCX , RDX , R8 , R9 ]>>,
646 // Integer/FP values get stored in stack slots that are 8 bytes in size and
647 // 8-byte aligned if there are no more registers to hold them.
648 CCIfType<[i8, i16, i32, i64, f32, f64], CCAssignToStack<8, 8>>
651 def CC_X86_Win64_VectorCall : CallingConv<[
652 CCCustom<"CC_X86_64_VectorCall">,
654 // Delegate to fastcall to handle integer types.
655 CCDelegateTo<CC_X86_Win64_C>
659 def CC_X86_64_GHC : CallingConv<[
660 // Promote i8/i16/i32 arguments to i64.
661 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
663 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
665 CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9, R15]>>,
667 // Pass in STG registers: F1, F2, F3, F4, D1, D2
668 CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
669 CCIfSubtarget<"hasSSE1()",
670 CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>,
672 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
673 CCIfSubtarget<"hasAVX()",
674 CCAssignToReg<[YMM1, YMM2, YMM3, YMM4, YMM5, YMM6]>>>,
676 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
677 CCIfSubtarget<"hasAVX512()",
678 CCAssignToReg<[ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6]>>>
681 def CC_X86_64_HiPE : CallingConv<[
682 // Promote i8/i16/i32 arguments to i64.
683 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
685 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2, ARG3
686 CCIfType<[i64], CCAssignToReg<[R15, RBP, RSI, RDX, RCX, R8]>>,
688 // Integer/FP values get stored in stack slots that are 8 bytes in size and
689 // 8-byte aligned if there are no more registers to hold them.
690 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
693 def CC_X86_64_WebKit_JS : CallingConv<[
694 // Promote i8/i16 arguments to i32.
695 CCIfType<[i8, i16], CCPromoteToType<i32>>,
697 // Only the first integer argument is passed in register.
698 CCIfType<[i32], CCAssignToReg<[EAX]>>,
699 CCIfType<[i64], CCAssignToReg<[RAX]>>,
701 // The remaining integer arguments are passed on the stack. 32bit integer and
702 // floating-point arguments are aligned to 4 byte and stored in 4 byte slots.
703 // 64bit integer and floating-point arguments are aligned to 8 byte and stored
704 // in 8 byte stack slots.
705 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
706 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
709 // No explicit register is specified for the AnyReg calling convention. The
710 // register allocator may assign the arguments to any free register.
712 // This calling convention is currently only supported by the stackmap and
713 // patchpoint intrinsics. All other uses will result in an assert on Debug
714 // builds. On Release builds we fallback to the X86 C calling convention.
715 def CC_X86_64_AnyReg : CallingConv<[
716 CCCustom<"CC_X86_AnyReg_Error">
719 //===----------------------------------------------------------------------===//
720 // X86 C Calling Convention
721 //===----------------------------------------------------------------------===//
723 /// CC_X86_32_Vector_Common - In all X86-32 calling conventions, extra vector
724 /// values are spilled on the stack.
725 def CC_X86_32_Vector_Common : CallingConv<[
726 // Other SSE vectors get 16-byte stack slots that are 16-byte aligned.
727 CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCAssignToStack<16, 16>>,
729 // 256-bit AVX vectors get 32-byte stack slots that are 32-byte aligned.
730 CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
731 CCAssignToStack<32, 32>>,
733 // 512-bit AVX 512-bit vectors get 64-byte stack slots that are 64-byte aligned.
734 CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
735 CCAssignToStack<64, 64>>
738 // CC_X86_32_Vector_Standard - The first 3 vector arguments are passed in
740 def CC_X86_32_Vector_Standard : CallingConv<[
741 // SSE vector arguments are passed in XMM registers.
742 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
743 CCAssignToReg<[XMM0, XMM1, XMM2]>>>,
745 // AVX 256-bit vector arguments are passed in YMM registers.
746 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
747 CCIfSubtarget<"hasAVX()",
748 CCAssignToReg<[YMM0, YMM1, YMM2]>>>>,
750 // AVX 512-bit vector arguments are passed in ZMM registers.
751 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
752 CCAssignToReg<[ZMM0, ZMM1, ZMM2]>>>,
754 CCDelegateTo<CC_X86_32_Vector_Common>
757 // CC_X86_32_Vector_Darwin - The first 4 vector arguments are passed in
759 def CC_X86_32_Vector_Darwin : CallingConv<[
760 // SSE vector arguments are passed in XMM registers.
761 CCIfNotVarArg<CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
762 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>>,
764 // AVX 256-bit vector arguments are passed in YMM registers.
765 CCIfNotVarArg<CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
766 CCIfSubtarget<"hasAVX()",
767 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>>>,
769 // AVX 512-bit vector arguments are passed in ZMM registers.
770 CCIfNotVarArg<CCIfType<[v64i8, v32i16, v16i32, v8i64, v16f32, v8f64],
771 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>>,
773 CCDelegateTo<CC_X86_32_Vector_Common>
776 /// CC_X86_32_Common - In all X86-32 calling conventions, extra integers and FP
777 /// values are spilled on the stack.
778 def CC_X86_32_Common : CallingConv<[
779 // Handles byval parameters.
780 CCIfByVal<CCPassByVal<4, 4>>,
782 // The first 3 float or double arguments, if marked 'inreg' and if the call
783 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
784 CCIfNotVarArg<CCIfInReg<CCIfType<[f32,f64],
785 CCIfSubtarget<"hasSSE2()",
786 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
788 // The first 3 __m64 vector arguments are passed in mmx registers if the
789 // call is not a vararg call.
790 CCIfNotVarArg<CCIfType<[x86mmx],
791 CCAssignToReg<[MM0, MM1, MM2]>>>,
793 // Integer/Float values get stored in stack slots that are 4 bytes in
794 // size and 4-byte aligned.
795 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
797 // Doubles get 8-byte slots that are 4-byte aligned.
798 CCIfType<[f64], CCAssignToStack<8, 4>>,
800 // Long doubles get slots whose size depends on the subtarget.
801 CCIfType<[f80], CCAssignToStack<0, 4>>,
803 // Boolean vectors of AVX-512 are passed in SIMD registers.
804 // The call from AVX to AVX-512 function should work,
805 // since the boolean types in AVX/AVX2 are promoted by default.
806 CCIfType<[v2i1], CCPromoteToType<v2i64>>,
807 CCIfType<[v4i1], CCPromoteToType<v4i32>>,
808 CCIfType<[v8i1], CCPromoteToType<v8i16>>,
809 CCIfType<[v16i1], CCPromoteToType<v16i8>>,
810 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
811 CCIfType<[v64i1], CCPromoteToType<v64i8>>,
813 // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
814 // passed in the parameter area.
815 CCIfType<[x86mmx], CCAssignToStack<8, 4>>,
817 // Darwin passes vectors in a form that differs from the i386 psABI
818 CCIfSubtarget<"isTargetDarwin()", CCDelegateTo<CC_X86_32_Vector_Darwin>>,
820 // Otherwise, drop to 'normal' X86-32 CC
821 CCDelegateTo<CC_X86_32_Vector_Standard>
824 def CC_X86_32_C : CallingConv<[
825 // Promote i1/i8/i16/v1i1 arguments to i32.
826 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
828 // The 'nest' parameter, if any, is passed in ECX.
829 CCIfNest<CCAssignToReg<[ECX]>>,
831 // The first 3 integer arguments, if marked 'inreg' and if the call is not
832 // a vararg call, are passed in integer registers.
833 CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[EAX, EDX, ECX]>>>>,
835 // Otherwise, same as everything else.
836 CCDelegateTo<CC_X86_32_Common>
839 def CC_X86_32_MCU : CallingConv<[
840 // Handles byval parameters. Note that, like FastCC, we can't rely on
841 // the delegation to CC_X86_32_Common because that happens after code that
842 // puts arguments in registers.
843 CCIfByVal<CCPassByVal<4, 4>>,
845 // Promote i1/i8/i16/v1i1 arguments to i32.
846 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
848 // If the call is not a vararg call, some arguments may be passed
849 // in integer registers.
850 CCIfNotVarArg<CCIfType<[i32], CCCustom<"CC_X86_32_MCUInReg">>>,
852 // Otherwise, same as everything else.
853 CCDelegateTo<CC_X86_32_Common>
856 def CC_X86_32_FastCall : CallingConv<[
858 CCIfType<[i1], CCPromoteToType<i8>>,
860 // The 'nest' parameter, if any, is passed in EAX.
861 CCIfNest<CCAssignToReg<[EAX]>>,
863 // The first 2 integer arguments are passed in ECX/EDX
864 CCIfInReg<CCIfType<[ i8], CCAssignToReg<[ CL, DL]>>>,
865 CCIfInReg<CCIfType<[i16], CCAssignToReg<[ CX, DX]>>>,
866 CCIfInReg<CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>>,
868 // Otherwise, same as everything else.
869 CCDelegateTo<CC_X86_32_Common>
872 def CC_X86_Win32_VectorCall : CallingConv<[
873 // Pass floating point in XMMs
874 CCCustom<"CC_X86_32_VectorCall">,
876 // Delegate to fastcall to handle integer types.
877 CCDelegateTo<CC_X86_32_FastCall>
880 def CC_X86_32_ThisCall_Common : CallingConv<[
881 // The first integer argument is passed in ECX
882 CCIfType<[i32], CCAssignToReg<[ECX]>>,
884 // Otherwise, same as everything else.
885 CCDelegateTo<CC_X86_32_Common>
888 def CC_X86_32_ThisCall_Mingw : CallingConv<[
889 // Promote i1/i8/i16/v1i1 arguments to i32.
890 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
892 CCDelegateTo<CC_X86_32_ThisCall_Common>
895 def CC_X86_32_ThisCall_Win : CallingConv<[
896 // Promote i1/i8/i16/v1i1 arguments to i32.
897 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
899 // Pass sret arguments indirectly through stack.
900 CCIfSRet<CCAssignToStack<4, 4>>,
902 CCDelegateTo<CC_X86_32_ThisCall_Common>
905 def CC_X86_32_ThisCall : CallingConv<[
906 CCIfSubtarget<"isTargetCygMing()", CCDelegateTo<CC_X86_32_ThisCall_Mingw>>,
907 CCDelegateTo<CC_X86_32_ThisCall_Win>
910 def CC_X86_32_FastCC : CallingConv<[
911 // Handles byval parameters. Note that we can't rely on the delegation
912 // to CC_X86_32_Common for this because that happens after code that
913 // puts arguments in registers.
914 CCIfByVal<CCPassByVal<4, 4>>,
916 // Promote i1/i8/i16/v1i1 arguments to i32.
917 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
919 // The 'nest' parameter, if any, is passed in EAX.
920 CCIfNest<CCAssignToReg<[EAX]>>,
922 // The first 2 integer arguments are passed in ECX/EDX
923 CCIfType<[i32], CCAssignToReg<[ECX, EDX]>>,
925 // The first 3 float or double arguments, if the call is not a vararg
926 // call and if SSE2 is available, are passed in SSE registers.
927 CCIfNotVarArg<CCIfType<[f32,f64],
928 CCIfSubtarget<"hasSSE2()",
929 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>,
931 // Doubles get 8-byte slots that are 8-byte aligned.
932 CCIfType<[f64], CCAssignToStack<8, 8>>,
934 // Otherwise, same as everything else.
935 CCDelegateTo<CC_X86_32_Common>
938 def CC_X86_32_GHC : CallingConv<[
939 // Promote i8/i16 arguments to i32.
940 CCIfType<[i8, i16], CCPromoteToType<i32>>,
942 // Pass in STG registers: Base, Sp, Hp, R1
943 CCIfType<[i32], CCAssignToReg<[EBX, EBP, EDI, ESI]>>
946 def CC_X86_32_HiPE : CallingConv<[
947 // Promote i8/i16 arguments to i32.
948 CCIfType<[i8, i16], CCPromoteToType<i32>>,
950 // Pass in VM's registers: HP, P, ARG0, ARG1, ARG2
951 CCIfType<[i32], CCAssignToReg<[ESI, EBP, EAX, EDX, ECX]>>,
953 // Integer/Float values get stored in stack slots that are 4 bytes in
954 // size and 4-byte aligned.
955 CCIfType<[i32, f32], CCAssignToStack<4, 4>>
958 // X86-64 Intel OpenCL built-ins calling convention.
959 def CC_Intel_OCL_BI : CallingConv<[
961 CCIfType<[i32], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[ECX, EDX, R8D, R9D]>>>,
962 CCIfType<[i64], CCIfSubtarget<"isTargetWin64()", CCAssignToReg<[RCX, RDX, R8, R9 ]>>>,
964 CCIfType<[i32], CCIfSubtarget<"is64Bit()", CCAssignToReg<[EDI, ESI, EDX, ECX]>>>,
965 CCIfType<[i64], CCIfSubtarget<"is64Bit()", CCAssignToReg<[RDI, RSI, RDX, RCX]>>>,
967 CCIfType<[i32], CCAssignToStack<4, 4>>,
969 // The SSE vector arguments are passed in XMM registers.
970 CCIfType<[f32, f64, v4i32, v2i64, v4f32, v2f64],
971 CCAssignToReg<[XMM0, XMM1, XMM2, XMM3]>>,
973 // The 256-bit vector arguments are passed in YMM registers.
974 CCIfType<[v8f32, v4f64, v8i32, v4i64],
975 CCAssignToReg<[YMM0, YMM1, YMM2, YMM3]>>,
977 // The 512-bit vector arguments are passed in ZMM registers.
978 CCIfType<[v16f32, v8f64, v16i32, v8i64],
979 CCAssignToReg<[ZMM0, ZMM1, ZMM2, ZMM3]>>,
981 // Pass masks in mask registers
982 CCIfType<[v16i1, v8i1], CCAssignToReg<[K1]>>,
984 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
985 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64_C>>,
986 CCDelegateTo<CC_X86_32_C>
989 //===----------------------------------------------------------------------===//
990 // X86 Root Argument Calling Conventions
991 //===----------------------------------------------------------------------===//
993 // This is the root argument convention for the X86-32 backend.
994 def CC_X86_32 : CallingConv<[
995 // X86_INTR calling convention is valid in MCU target and should override the
996 // MCU calling convention. Thus, this should be checked before isTargetMCU().
997 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>,
998 CCIfSubtarget<"isTargetMCU()", CCDelegateTo<CC_X86_32_MCU>>,
999 CCIfCC<"CallingConv::X86_FastCall", CCDelegateTo<CC_X86_32_FastCall>>,
1000 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win32_VectorCall>>,
1001 CCIfCC<"CallingConv::X86_ThisCall", CCDelegateTo<CC_X86_32_ThisCall>>,
1002 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_X86_32_FastCC>>,
1003 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_32_GHC>>,
1004 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_32_HiPE>>,
1005 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_32_RegCall>>,
1007 // Otherwise, drop to normal X86-32 CC
1008 CCDelegateTo<CC_X86_32_C>
1011 // This is the root argument convention for the X86-64 backend.
1012 def CC_X86_64 : CallingConv<[
1013 CCIfCC<"CallingConv::GHC", CCDelegateTo<CC_X86_64_GHC>>,
1014 CCIfCC<"CallingConv::HiPE", CCDelegateTo<CC_X86_64_HiPE>>,
1015 CCIfCC<"CallingConv::WebKit_JS", CCDelegateTo<CC_X86_64_WebKit_JS>>,
1016 CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_X86_64_AnyReg>>,
1017 CCIfCC<"CallingConv::Win64", CCDelegateTo<CC_X86_Win64_C>>,
1018 CCIfCC<"CallingConv::X86_64_SysV", CCDelegateTo<CC_X86_64_C>>,
1019 CCIfCC<"CallingConv::X86_VectorCall", CCDelegateTo<CC_X86_Win64_VectorCall>>,
1020 CCIfCC<"CallingConv::HHVM", CCDelegateTo<CC_X86_64_HHVM>>,
1021 CCIfCC<"CallingConv::HHVM_C", CCDelegateTo<CC_X86_64_HHVM_C>>,
1022 CCIfCC<"CallingConv::X86_RegCall",
1023 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_RegCall>>>,
1024 CCIfCC<"CallingConv::X86_RegCall", CCDelegateTo<CC_X86_SysV64_RegCall>>,
1025 CCIfCC<"CallingConv::X86_INTR", CCCustom<"CC_X86_Intr">>,
1027 // Mingw64 and native Win64 use Win64 CC
1028 CCIfSubtarget<"isTargetWin64()", CCDelegateTo<CC_X86_Win64_C>>,
1030 // Otherwise, drop to normal X86-64 CC
1031 CCDelegateTo<CC_X86_64_C>
1034 // This is the argument convention used for the entire X86 backend.
1036 def CC_X86 : CallingConv<[
1037 CCIfCC<"CallingConv::Intel_OCL_BI", CCDelegateTo<CC_Intel_OCL_BI>>,
1038 CCIfSubtarget<"is64Bit()", CCDelegateTo<CC_X86_64>>,
1039 CCDelegateTo<CC_X86_32>
1042 //===----------------------------------------------------------------------===//
1043 // Callee-saved Registers.
1044 //===----------------------------------------------------------------------===//
1046 def CSR_NoRegs : CalleeSavedRegs<(add)>;
1048 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
1049 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
1051 def CSR_64_SwiftError : CalleeSavedRegs<(sub CSR_64, R12)>;
1053 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
1054 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
1056 def CSR_Win64_NoSSE : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15)>;
1058 def CSR_Win64 : CalleeSavedRegs<(add CSR_Win64_NoSSE,
1059 (sequence "XMM%u", 6, 15))>;
1061 def CSR_Win64_SwiftError : CalleeSavedRegs<(sub CSR_Win64, R12)>;
1063 // The function used by Darwin to obtain the address of a thread-local variable
1064 // uses rdi to pass a single parameter and rax for the return value. All other
1065 // GPRs are preserved.
1066 def CSR_64_TLS_Darwin : CalleeSavedRegs<(add CSR_64, RCX, RDX, RSI,
1069 // CSRs that are handled by prologue, epilogue.
1070 def CSR_64_CXX_TLS_Darwin_PE : CalleeSavedRegs<(add RBP)>;
1072 // CSRs that are handled explicitly via copies.
1073 def CSR_64_CXX_TLS_Darwin_ViaCopy : CalleeSavedRegs<(sub CSR_64_TLS_Darwin, RBP)>;
1075 // All GPRs - except r11
1076 def CSR_64_RT_MostRegs : CalleeSavedRegs<(add CSR_64, RAX, RCX, RDX, RSI, RDI,
1079 // All registers - except r11
1080 def CSR_64_RT_AllRegs : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
1081 (sequence "XMM%u", 0, 15))>;
1082 def CSR_64_RT_AllRegs_AVX : CalleeSavedRegs<(add CSR_64_RT_MostRegs,
1083 (sequence "YMM%u", 0, 15))>;
1085 def CSR_64_MostRegs : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
1086 R11, R12, R13, R14, R15, RBP,
1087 (sequence "XMM%u", 0, 15))>;
1089 def CSR_32_AllRegs : CalleeSavedRegs<(add EAX, EBX, ECX, EDX, EBP, ESI,
1091 def CSR_32_AllRegs_SSE : CalleeSavedRegs<(add CSR_32_AllRegs,
1092 (sequence "XMM%u", 0, 7))>;
1093 def CSR_32_AllRegs_AVX : CalleeSavedRegs<(add CSR_32_AllRegs,
1094 (sequence "YMM%u", 0, 7))>;
1095 def CSR_32_AllRegs_AVX512 : CalleeSavedRegs<(add CSR_32_AllRegs,
1096 (sequence "ZMM%u", 0, 7),
1097 (sequence "K%u", 0, 7))>;
1099 def CSR_64_AllRegs : CalleeSavedRegs<(add CSR_64_MostRegs, RAX)>;
1100 def CSR_64_AllRegs_NoSSE : CalleeSavedRegs<(add RAX, RBX, RCX, RDX, RSI, RDI, R8, R9,
1101 R10, R11, R12, R13, R14, R15, RBP)>;
1102 def CSR_64_AllRegs_AVX : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX,
1103 (sequence "YMM%u", 0, 15)),
1104 (sequence "XMM%u", 0, 15))>;
1105 def CSR_64_AllRegs_AVX512 : CalleeSavedRegs<(sub (add CSR_64_MostRegs, RAX,
1106 (sequence "ZMM%u", 0, 31),
1107 (sequence "K%u", 0, 7)),
1108 (sequence "XMM%u", 0, 15))>;
1110 // Standard C + YMM6-15
1111 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
1113 (sequence "YMM%u", 6, 15))>;
1115 def CSR_Win64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI,
1117 (sequence "ZMM%u", 6, 21),
1119 //Standard C + XMM 8-15
1120 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
1121 (sequence "XMM%u", 8, 15))>;
1123 //Standard C + YMM 8-15
1124 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
1125 (sequence "YMM%u", 8, 15))>;
1127 def CSR_64_Intel_OCL_BI_AVX512 : CalleeSavedRegs<(add RBX, RDI, RSI, R14, R15,
1128 (sequence "ZMM%u", 16, 31),
1131 // Only R12 is preserved for PHP calls in HHVM.
1132 def CSR_64_HHVM : CalleeSavedRegs<(add R12)>;
1134 // Register calling convention preserves few GPR and XMM8-15
1135 def CSR_32_RegCall_NoSSE : CalleeSavedRegs<(add ESI, EDI, EBX, EBP, ESP)>;
1136 def CSR_32_RegCall : CalleeSavedRegs<(add CSR_32_RegCall_NoSSE,
1137 (sequence "XMM%u", 4, 7))>;
1138 def CSR_Win64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP,
1139 (sequence "R%u", 10, 15))>;
1140 def CSR_Win64_RegCall : CalleeSavedRegs<(add CSR_Win64_RegCall_NoSSE,
1141 (sequence "XMM%u", 8, 15))>;
1142 def CSR_SysV64_RegCall_NoSSE : CalleeSavedRegs<(add RBX, RBP, RSP,
1143 (sequence "R%u", 12, 15))>;
1144 def CSR_SysV64_RegCall : CalleeSavedRegs<(add CSR_SysV64_RegCall_NoSSE,
1145 (sequence "XMM%u", 8, 15))>;