1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file declares codegen opcodes and related utilities.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_CODEGEN_ISDOPCODES_H
14 #define LLVM_CODEGEN_ISDOPCODES_H
18 /// ISD namespace - This namespace contains an enum which represents all of the
19 /// SelectionDAG node types and value types.
23 //===--------------------------------------------------------------------===//
24 /// ISD::NodeType enum - This enum defines the target-independent operators
25 /// for a SelectionDAG.
27 /// Targets may also define target-dependent operator codes for SDNodes. For
28 /// example, on x86, these are the enum values in the X86ISD namespace.
29 /// Targets should aim to use target-independent operators to model their
30 /// instruction sets as much as possible, and only use target-dependent
31 /// operators when they have special requirements.
33 /// Finally, during and after selection proper, SNodes may use special
34 /// operator codes that correspond directly with MachineInstr opcodes. These
35 /// are used to represent selected instructions. See the isMachineOpcode()
36 /// and getMachineOpcode() member functions of SDNode.
39 /// DELETED_NODE - This is an illegal value that is used to catch
40 /// errors. This opcode is not a legal opcode for any node.
43 /// EntryToken - This is the marker used to indicate the start of a region.
46 /// TokenFactor - This node takes multiple tokens as input and produces a
47 /// single token result. This is used to represent the fact that the operand
48 /// operators are independent of each other.
51 /// AssertSext, AssertZext - These nodes record if a register contains a
52 /// value that has already been zero or sign extended from a narrower type.
53 /// These nodes take two operands. The first is the node that has already
54 /// been extended, and the second is a value type node indicating the width
56 AssertSext
, AssertZext
,
58 /// Various leaf nodes.
59 BasicBlock
, VALUETYPE
, CONDCODE
, Register
, RegisterMask
,
61 GlobalAddress
, GlobalTLSAddress
, FrameIndex
,
62 JumpTable
, ConstantPool
, ExternalSymbol
, BlockAddress
,
64 /// The address of the GOT
67 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
68 /// llvm.returnaddress on the DAG. These nodes take one operand, the index
69 /// of the frame or return address to return. An index of zero corresponds
70 /// to the current function's frame or return address, an index of one to
71 /// the parent's frame or return address, and so on.
72 FRAMEADDR
, RETURNADDR
, ADDROFRETURNADDR
, SPONENTRY
,
74 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
75 /// Materializes the offset from the local object pointer of another
76 /// function to a particular local object passed to llvm.localescape. The
77 /// operand is the MCSymbol label used to represent this offset, since
78 /// typically the offset is not known until after code generation of the
82 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
83 /// the DAG, which implements the named register global variables extension.
87 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
88 /// first (possible) on-stack argument. This is needed for correct stack
89 /// adjustment during unwind.
92 /// EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical
93 /// Frame Address (CFA), generally the value of the stack pointer at the
94 /// call site in the previous frame.
97 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
98 /// 'eh_return' gcc dwarf builtin, which is used to return from
99 /// exception. The general meaning is: adjust stack by OFFSET and pass
100 /// execution to HANDLER. Many platform-related details also :)
103 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
104 /// This corresponds to the eh.sjlj.setjmp intrinsic.
105 /// It takes an input chain and a pointer to the jump buffer as inputs
106 /// and returns an outchain.
109 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
110 /// This corresponds to the eh.sjlj.longjmp intrinsic.
111 /// It takes an input chain and a pointer to the jump buffer as inputs
112 /// and returns an outchain.
115 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
116 /// The target initializes the dispatch table here.
117 EH_SJLJ_SETUP_DISPATCH
,
119 /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
120 /// simplification, or lowering of the constant. They are used for constants
121 /// which are known to fit in the immediate fields of their users, or for
122 /// carrying magic numbers which are not values which need to be
123 /// materialized in registers.
127 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
128 /// anything else with this node, and this is valid in the target-specific
129 /// dag, turning into a GlobalAddress operand.
131 TargetGlobalTLSAddress
,
135 TargetExternalSymbol
,
140 /// TargetIndex - Like a constant pool entry, but with completely
141 /// target-dependent semantics. Holds target flags, a 32-bit index, and a
142 /// 64-bit index. Targets can use this however they like.
145 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
146 /// This node represents a target intrinsic function with no side effects.
147 /// The first operand is the ID number of the intrinsic from the
148 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
149 /// node returns the result of the intrinsic.
152 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
153 /// This node represents a target intrinsic function with side effects that
154 /// returns a result. The first operand is a chain pointer. The second is
155 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
156 /// operands to the intrinsic follow. The node has two results, the result
157 /// of the intrinsic and an output chain.
160 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
161 /// This node represents a target intrinsic function with side effects that
162 /// does not return a result. The first operand is a chain pointer. The
163 /// second is the ID number of the intrinsic from the llvm::Intrinsic
164 /// namespace. The operands to the intrinsic follow.
167 /// CopyToReg - This node has three operands: a chain, a register number to
168 /// set to this value, and a value.
171 /// CopyFromReg - This node indicates that the input value is a virtual or
172 /// physical register that is defined outside of the scope of this
173 /// SelectionDAG. The register is available from the RegisterSDNode object.
176 /// UNDEF - An undefined node.
179 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
180 /// a Constant, which is required to be operand #1) half of the integer or
181 /// float value specified as operand #0. This is only for use before
182 /// legalization, for values that will be broken into multiple registers.
185 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
186 /// Given two values of the same integer value type, this produces a value
187 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
188 /// legalization. The lower part of the composite value should be in
189 /// element 0 and the upper part should be in element 1.
192 /// MERGE_VALUES - This node takes multiple discrete operands and returns
193 /// them all as its individual results. This nodes has exactly the same
194 /// number of inputs and outputs. This node is useful for some pieces of the
195 /// code generator that want to think about a single node with multiple
196 /// results, not multiple nodes.
199 /// Simple integer binary arithmetic operators.
200 ADD
, SUB
, MUL
, SDIV
, UDIV
, SREM
, UREM
,
202 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
203 /// a signed/unsigned value of type i[2*N], and return the full value as
204 /// two results, each of type iN.
205 SMUL_LOHI
, UMUL_LOHI
,
207 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
208 /// remainder result.
211 /// CARRY_FALSE - This node is used when folding other nodes,
212 /// like ADDC/SUBC, which indicate the carry result is always false.
215 /// Carry-setting nodes for multiple precision addition and subtraction.
216 /// These nodes take two operands of the same value type, and produce two
217 /// results. The first result is the normal add or sub result, the second
218 /// result is the carry flag result.
219 /// FIXME: These nodes are deprecated in favor of ADDCARRY and SUBCARRY.
220 /// They are kept around for now to provide a smooth transition path
221 /// toward the use of ADDCARRY/SUBCARRY and will eventually be removed.
224 /// Carry-using nodes for multiple precision addition and subtraction. These
225 /// nodes take three operands: The first two are the normal lhs and rhs to
226 /// the add or sub, and the third is the input carry flag. These nodes
227 /// produce two results; the normal result of the add or sub, and the output
228 /// carry flag. These nodes both read and write a carry flag to allow them
229 /// to them to be chained together for add and sub of arbitrarily large
233 /// Carry-using nodes for multiple precision addition and subtraction.
234 /// These nodes take three operands: The first two are the normal lhs and
235 /// rhs to the add or sub, and the third is a boolean indicating if there
236 /// is an incoming carry. These nodes produce two results: the normal
237 /// result of the add or sub, and the output carry so they can be chained
238 /// together. The use of this opcode is preferable to adde/sube if the
239 /// target supports it, as the carry is a regular value rather than a
240 /// glue, which allows further optimisation.
243 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
244 /// These nodes take two operands: the normal LHS and RHS to the add. They
245 /// produce two results: the normal result of the add, and a boolean that
246 /// indicates if an overflow occurred (*not* a flag, because it may be store
247 /// to memory, etc.). If the type of the boolean is not i1 then the high
248 /// bits conform to getBooleanContents.
249 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
252 /// Same for subtraction.
255 /// Same for multiplication.
258 /// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2
259 /// integers with the same bit width (W). If the true value of LHS + RHS
260 /// exceeds the largest value that can be represented by W bits, the
261 /// resulting value is this maximum value. Otherwise, if this value is less
262 /// than the smallest value that can be represented by W bits, the
263 /// resulting value is this minimum value.
266 /// RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2
267 /// integers with the same bit width (W). If the true value of LHS - RHS
268 /// exceeds the largest value that can be represented by W bits, the
269 /// resulting value is this maximum value. Otherwise, if this value is less
270 /// than the smallest value that can be represented by W bits, the
271 /// resulting value is this minimum value.
274 /// RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on
275 /// 2 integers with the same width and scale. SCALE represents the scale of
276 /// both operands as fixed point numbers. This SCALE parameter must be a
277 /// constant integer. A scale of zero is effectively performing
278 /// multiplication on 2 integers.
281 /// Same as the corresponding unsaturated fixed point instructions, but the
282 /// result is clamped between the min and max values representable by the
283 /// bits of the first 2 operands.
284 SMULFIXSAT
, UMULFIXSAT
,
286 /// Simple binary floating point operators.
287 FADD
, FSUB
, FMUL
, FDIV
, FREM
,
289 /// Constrained versions of the binary floating point operators.
290 /// These will be lowered to the simple operators before final selection.
291 /// They are used to limit optimizations while the DAG is being
293 STRICT_FADD
, STRICT_FSUB
, STRICT_FMUL
, STRICT_FDIV
, STRICT_FREM
,
296 /// Constrained versions of libm-equivalent floating point intrinsics.
297 /// These will be lowered to the equivalent non-constrained pseudo-op
298 /// (or expanded to the equivalent library call) before final selection.
299 /// They are used to limit optimizations while the DAG is being optimized.
300 STRICT_FSQRT
, STRICT_FPOW
, STRICT_FPOWI
, STRICT_FSIN
, STRICT_FCOS
,
301 STRICT_FEXP
, STRICT_FEXP2
, STRICT_FLOG
, STRICT_FLOG10
, STRICT_FLOG2
,
302 STRICT_FRINT
, STRICT_FNEARBYINT
, STRICT_FMAXNUM
, STRICT_FMINNUM
,
303 STRICT_FCEIL
, STRICT_FFLOOR
, STRICT_FROUND
, STRICT_FTRUNC
,
305 /// STRICT_FP_TO_[US]INT - Convert a floating point value to a signed or
306 /// unsigned integer. These have the same semantics as fptosi and fptoui
308 /// They are used to limit optimizations while the DAG is being optimized.
312 /// X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating
313 /// point type down to the precision of the destination VT. TRUNC is a
314 /// flag, which is always an integer that is zero or one. If TRUNC is 0,
315 /// this is a normal rounding, if it is 1, this FP_ROUND is known to not
316 /// change the value of Y.
318 /// The TRUNC = 1 case is used in cases where we know that the value will
319 /// not be modified by the node, because Y is not using any of the extra
320 /// precision of source type. This allows certain transformations like
321 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,1)) -> X which are not safe for
322 /// STRICT_FP_EXTEND(STRICT_FP_ROUND(X,0)) because the extra bits aren't
324 /// It is used to limit optimizations while the DAG is being optimized.
327 /// X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP
329 /// It is used to limit optimizations while the DAG is being optimized.
332 /// FMA - Perform a * b + c with no intermediate rounding step.
335 /// FMAD - Perform a * b + c, while getting the same result as the
336 /// separately rounded operations.
339 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
340 /// DAG node does not require that X and Y have the same type, just that
341 /// they are both floating point. X and the result must have the same type.
342 /// FCOPYSIGN(f32, f64) is allowed.
345 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
346 /// value as an integer 0/1 value.
349 /// Returns platform specific canonical encoding of a floating point number.
352 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
353 /// specified, possibly variable, elements. The number of elements is
354 /// required to be a power of two. The types of the operands must all be
355 /// the same and must match the vector element type, except that integer
356 /// types are allowed to be larger than the element type, in which case
357 /// the operands are implicitly truncated.
360 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
361 /// at IDX replaced with VAL. If the type of VAL is larger than the vector
362 /// element type then VAL is truncated before replacement.
365 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
366 /// identified by the (potentially variable) element number IDX. If the
367 /// return type is an integer type larger than the element type of the
368 /// vector, the result is extended to the width of the return type. In
369 /// that case, the high bits are undefined.
372 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
373 /// vector type with the same length and element type, this produces a
374 /// concatenated vector result value, with length equal to the sum of the
375 /// lengths of the input vectors.
378 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
379 /// with VECTOR2 inserted into VECTOR1 at the (potentially
380 /// variable) element number IDX, which must be a multiple of the
381 /// VECTOR2 vector length. The elements of VECTOR1 starting at
382 /// IDX are overwritten with VECTOR2. Elements IDX through
383 /// vector_length(VECTOR2) must be valid VECTOR1 indices.
386 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
387 /// vector value) starting with the element number IDX, which must be a
388 /// constant multiple of the result vector length.
391 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
392 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
393 /// values that indicate which value (or undef) each result element will
394 /// get. These constant ints are accessible through the
395 /// ShuffleVectorSDNode class. This is quite similar to the Altivec
396 /// 'vperm' instruction, except that the indices must be constants and are
397 /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
400 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
401 /// scalar value into element 0 of the resultant vector type. The top
402 /// elements 1 to N-1 of the N-element vector are undefined. The type
403 /// of the operand must match the vector element type, except when they
404 /// are integer types. In this case the operand is allowed to be wider
405 /// than the vector element type, and is implicitly truncated to it.
408 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
409 /// producing an unsigned/signed value of type i[2*N], then return the top
413 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned
415 SMIN
, SMAX
, UMIN
, UMAX
,
417 /// Bitwise operators - logical and, logical or, logical xor.
420 /// ABS - Determine the unsigned absolute value of a signed integer value of
421 /// the same bitwidth.
422 /// Note: A value of INT_MIN will return INT_MIN, no saturation or overflow
426 /// Shift and rotation operations. After legalization, the type of the
427 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
428 /// the shift amount can be any type, but care must be taken to ensure it is
429 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
430 /// legalization, types like i1024 can occur and i8 doesn't have enough bits
431 /// to represent the shift amount.
432 /// When the 1st operand is a vector, the shift amount must be in the same
433 /// type. (TLI.getShiftAmountTy() will return the same type when the input
434 /// type is a vector.)
435 /// For rotates and funnel shifts, the shift amount is treated as an unsigned
436 /// amount modulo the element size of the first operand.
438 /// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount.
439 /// fshl(X,Y,Z): (X << (Z % BW)) | (Y >> (BW - (Z % BW)))
440 /// fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW))
441 SHL
, SRA
, SRL
, ROTL
, ROTR
, FSHL
, FSHR
,
443 /// Byte Swap and Counting operators.
444 BSWAP
, CTTZ
, CTLZ
, CTPOP
, BITREVERSE
,
446 /// Bit counting operators with an undefined result for zero inputs.
447 CTTZ_ZERO_UNDEF
, CTLZ_ZERO_UNDEF
,
449 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
450 /// i1 then the high bits must conform to getBooleanContents.
453 /// Select with a vector condition (op #0) and two vector operands (ops #1
454 /// and #2), returning a vector result. All vectors have the same length.
455 /// Much like the scalar select and setcc, each bit in the condition selects
456 /// whether the corresponding result element is taken from op #1 or op #2.
457 /// At first, the VSELECT condition is of vXi1 type. Later, targets may
458 /// change the condition type in order to match the VSELECT node using a
459 /// pattern. The condition follows the BooleanContent format of the target.
462 /// Select with condition operator - This selects between a true value and
463 /// a false value (ops #2 and #3) based on the boolean result of comparing
464 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
465 /// condition code in op #4, a CondCodeSDNode.
468 /// SetCC operator - This evaluates to a true value iff the condition is
469 /// true. If the result value type is not i1 then the high bits conform
470 /// to getBooleanContents. The operands to this are the left and right
471 /// operands to compare (ops #0, and #1) and the condition code to compare
472 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
473 /// then the result type must also be a vector type.
476 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
477 /// op #2 is a boolean indicating if there is an incoming carry. This
478 /// operator checks the result of "LHS - RHS - Carry", and can be used to
479 /// compare two wide integers:
480 /// (setcccarry lhshi rhshi (subcarry lhslo rhslo) cc).
481 /// Only valid for integers.
484 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
485 /// integer shift operations. The operation ordering is:
486 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
487 SHL_PARTS
, SRA_PARTS
, SRL_PARTS
,
489 /// Conversion operators. These are all single input single output
490 /// operations. For all of these, the result type must be strictly
491 /// wider or narrower (depending on the operation) than the source
494 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
498 /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
501 /// ANY_EXTEND - Used for integer types. The high bits are undefined.
504 /// TRUNCATE - Completely drop the high bits.
507 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
508 /// depends on the first letter) to floating point.
512 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
513 /// sign extend a small value in a large integer register (e.g. sign
514 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
515 /// with the 7th bit). The size of the smaller type is indicated by the 1th
516 /// operand, a ValueType node.
519 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
520 /// in-register any-extension of the low lanes of an integer vector. The
521 /// result type must have fewer elements than the operand type, and those
522 /// elements must be larger integer types such that the total size of the
523 /// operand type is less than or equal to the size of the result type. Each
524 /// of the low operand elements is any-extended into the corresponding,
525 /// wider result elements with the high bits becoming undef.
526 /// NOTE: The type legalizer prefers to make the operand and result size
527 /// the same to allow expansion to shuffle vector during op legalization.
528 ANY_EXTEND_VECTOR_INREG
,
530 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
531 /// in-register sign-extension of the low lanes of an integer vector. The
532 /// result type must have fewer elements than the operand type, and those
533 /// elements must be larger integer types such that the total size of the
534 /// operand type is less than or equal to the size of the result type. Each
535 /// of the low operand elements is sign-extended into the corresponding,
536 /// wider result elements.
537 /// NOTE: The type legalizer prefers to make the operand and result size
538 /// the same to allow expansion to shuffle vector during op legalization.
539 SIGN_EXTEND_VECTOR_INREG
,
541 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
542 /// in-register zero-extension of the low lanes of an integer vector. The
543 /// result type must have fewer elements than the operand type, and those
544 /// elements must be larger integer types such that the total size of the
545 /// operand type is less than or equal to the size of the result type. Each
546 /// of the low operand elements is zero-extended into the corresponding,
547 /// wider result elements.
548 /// NOTE: The type legalizer prefers to make the operand and result size
549 /// the same to allow expansion to shuffle vector during op legalization.
550 ZERO_EXTEND_VECTOR_INREG
,
552 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
553 /// integer. These have the same semantics as fptosi and fptoui in IR. If
554 /// the FP value cannot fit in the integer type, the results are undefined.
558 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
559 /// down to the precision of the destination VT. TRUNC is a flag, which is
560 /// always an integer that is zero or one. If TRUNC is 0, this is a
561 /// normal rounding, if it is 1, this FP_ROUND is known to not change the
564 /// The TRUNC = 1 case is used in cases where we know that the value will
565 /// not be modified by the node, because Y is not using any of the extra
566 /// precision of source type. This allows certain transformations like
567 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
568 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
571 /// FLT_ROUNDS_ - Returns current rounding mode:
574 /// 1 Round to nearest
579 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
582 /// BITCAST - This operator converts between integer, vector and FP
583 /// values, as if the value was stored to memory with one type and loaded
584 /// from the same address with the other type (or equivalently for vector
585 /// format conversions, etc). The source and result are required to have
586 /// the same bit size (e.g. f32 <-> i32). This can also be used for
587 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
590 /// This operator is subtly different from the bitcast instruction from
591 /// LLVM-IR since this node may change the bits in the register. For
592 /// example, this occurs on big-endian NEON and big-endian MSA where the
593 /// layout of the bits in the register depends on the vector type and this
594 /// operator acts as a shuffle operation for some vector type combinations.
597 /// ADDRSPACECAST - This operator converts between pointers of different
601 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
602 /// and truncation for half-precision (16 bit) floating numbers. These nodes
603 /// form a semi-softened interface for dealing with f16 (as an i16), which
604 /// is often a storage-only type but has native conversions.
605 FP16_TO_FP
, FP_TO_FP16
,
607 /// Perform various unary floating-point operations inspired by libm. For
608 /// FPOWI, the result is undefined if if the integer operand doesn't fit
610 FNEG
, FABS
, FSQRT
, FCBRT
, FSIN
, FCOS
, FPOWI
, FPOW
,
611 FLOG
, FLOG2
, FLOG10
, FEXP
, FEXP2
,
612 FCEIL
, FTRUNC
, FRINT
, FNEARBYINT
, FROUND
, FFLOOR
,
613 LROUND
, LLROUND
, LRINT
, LLRINT
,
615 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
618 /// In the case where a single input is a NaN (either signaling or quiet),
619 /// the non-NaN input is returned.
621 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
624 /// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
625 /// two values, following the IEEE-754 2008 definition. This differs from
626 /// FMINNUM/FMAXNUM in the handling of signaling NaNs. If one input is a
627 /// signaling NaN, returns a quiet NaN.
628 FMINNUM_IEEE
, FMAXNUM_IEEE
,
630 /// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
631 /// as less than 0.0. While FMINNUM_IEEE/FMAXNUM_IEEE follow IEEE 754-2008
632 /// semantics, FMINIMUM/FMAXIMUM follow IEEE 754-2018 draft semantics.
635 /// FSINCOS - Compute both fsin and fcos as a single operation.
638 /// LOAD and STORE have token chains as their first operand, then the same
639 /// operands as an LLVM load/store instruction, then an offset node that
640 /// is added / subtracted from the base pointer to form the address (for
641 /// indexed memory ops).
644 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
645 /// to a specified boundary. This node always has two return values: a new
646 /// stack pointer value and a chain. The first operand is the token chain,
647 /// the second is the number of bytes to allocate, and the third is the
648 /// alignment boundary. The size is guaranteed to be a multiple of the
649 /// stack alignment, and the alignment is guaranteed to be bigger than the
650 /// stack alignment (if required) or 0 to get standard stack alignment.
653 /// Control flow instructions. These all have token chains.
655 /// BR - Unconditional branch. The first operand is the chain
656 /// operand, the second is the MBB to branch to.
659 /// BRIND - Indirect branch. The first operand is the chain, the second
660 /// is the value to branch to, which must be of the same type as the
661 /// target's pointer type.
664 /// BR_JT - Jumptable branch. The first operand is the chain, the second
665 /// is the jumptable index, the last one is the jumptable entry index.
668 /// BRCOND - Conditional branch. The first operand is the chain, the
669 /// second is the condition, the third is the block to branch to if the
670 /// condition is true. If the type of the condition is not i1, then the
671 /// high bits must conform to getBooleanContents.
674 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
675 /// that the condition is represented as condition code, and two nodes to
676 /// compare, rather than as a combined SetCC node. The operands in order
677 /// are chain, cc, lhs, rhs, block to branch to if condition is true.
680 /// INLINEASM - Represents an inline asm block. This node always has two
681 /// return values: a chain and a flag result. The inputs are as follows:
682 /// Operand #0 : Input chain.
683 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
684 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
685 /// Operand #3 : HasSideEffect, IsAlignStack bits.
686 /// After this, it is followed by a list of operands with this format:
687 /// ConstantSDNode: Flags that encode whether it is a mem or not, the
688 /// of operands that follow, etc. See InlineAsm.h.
689 /// ... however many operands ...
690 /// Operand #last: Optional, an incoming flag.
692 /// The variable width operands are required to represent target addressing
693 /// modes as a single "operand", even though they may have multiple
697 /// INLINEASM_BR - Terminator version of inline asm. Used by asm-goto.
700 /// EH_LABEL - Represents a label in mid basic block used to track
701 /// locations needed for debug and exception handling tables. These nodes
702 /// take a chain as input and return a chain.
705 /// ANNOTATION_LABEL - Represents a mid basic block label used by
706 /// annotations. This should remain within the basic block and be ordered
707 /// with respect to other call instructions, but loads and stores may float
711 /// CATCHPAD - Represents a catchpad instruction.
714 /// CATCHRET - Represents a return from a catch block funclet. Used for
715 /// MSVC compatible exception handling. Takes a chain operand and a
716 /// destination basic block operand.
719 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for
720 /// MSVC compatible exception handling. Takes only a chain operand.
723 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
724 /// value, the same type as the pointer type for the system, and an output
728 /// STACKRESTORE has two operands, an input chain and a pointer to restore
729 /// to it returns an output chain.
732 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
733 /// of a call sequence, and carry arbitrary information that target might
734 /// want to know. The first operand is a chain, the rest are specified by
735 /// the target and not touched by the DAG optimizers.
736 /// Targets that may use stack to pass call arguments define additional
738 /// - size of the call frame part that must be set up within the
739 /// CALLSEQ_START..CALLSEQ_END pair,
740 /// - part of the call frame prepared prior to CALLSEQ_START.
741 /// Both these parameters must be constants, their sum is the total call
743 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
744 CALLSEQ_START
, // Beginning of a call sequence
745 CALLSEQ_END
, // End of a call sequence
747 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
748 /// and the alignment. It returns a pair of values: the vaarg value and a
752 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
753 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
757 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
758 /// pointer, and a SRCVALUE.
761 /// SRCVALUE - This is a node type that holds a Value* that is used to
762 /// make reference to a value in the LLVM IR.
765 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
766 /// reference metadata in the IR.
769 /// PCMARKER - This corresponds to the pcmarker intrinsic.
772 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
773 /// It produces a chain and one i64 value. The only operand is a chain.
774 /// If i64 is not legal, the result will be expanded into smaller values.
775 /// Still, it returns an i64, so targets should set legality for i64.
776 /// The result is the content of the architecture-specific cycle
777 /// counter-like register (or other high accuracy low latency clock source).
780 /// HANDLENODE node - Used as a handle for various purposes.
783 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It
784 /// takes as input a token chain, the pointer to the trampoline, the pointer
785 /// to the nested function, the pointer to pass for the 'nest' parameter, a
786 /// SRCVALUE for the trampoline and another for the nested function
787 /// (allowing targets to access the original Function*).
788 /// It produces a token chain as output.
791 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
792 /// It takes a pointer to the trampoline and produces a (possibly) new
793 /// pointer to the same trampoline with platform-specific adjustments
794 /// applied. The pointer it returns points to an executable block of code.
797 /// TRAP - Trapping instruction
800 /// DEBUGTRAP - Trap intended to get the attention of a debugger.
803 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
804 /// is the chain. The other operands are the address to prefetch,
805 /// read / write specifier, locality specifier and instruction / data cache
809 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
810 /// This corresponds to the fence instruction. It takes an input chain, and
811 /// two integer constants: an AtomicOrdering and a SynchronizationScope.
814 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
815 /// This corresponds to "load atomic" instruction.
818 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
819 /// This corresponds to "store atomic" instruction.
822 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
823 /// For double-word atomic operations:
824 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
826 /// This corresponds to the cmpxchg instruction.
829 /// Val, Success, OUTCHAIN
830 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
831 /// N.b. this is still a strong cmpxchg operation, so
832 /// Success == "Val == cmp".
833 ATOMIC_CMP_SWAP_WITH_SUCCESS
,
835 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
836 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
837 /// For double-word atomic operations:
838 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
839 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
840 /// These correspond to the atomicrmw instruction.
856 // Masked load and store - consecutive vector load and store operations
857 // with additional mask operand that prevents memory accesses to the
860 // Val, OutChain = MLOAD(BasePtr, Mask, PassThru)
861 // OutChain = MSTORE(Value, BasePtr, Mask)
864 // Masked gather and scatter - load and store operations for a vector of
865 // random addresses with additional mask operand that prevents memory
866 // accesses to the masked-off lanes.
868 // Val, OutChain = GATHER(InChain, PassThru, Mask, BasePtr, Index, Scale)
869 // OutChain = SCATTER(InChain, Value, Mask, BasePtr, Index, Scale)
871 // The Index operand can have more vector elements than the other operands
872 // due to type legalization. The extra elements are ignored.
875 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
876 /// is the chain and the second operand is the alloca pointer.
877 LIFETIME_START
, LIFETIME_END
,
879 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
880 /// beginning and end of GC transition sequence, and carry arbitrary
881 /// information that target might need for lowering. The first operand is
882 /// a chain, the rest are specified by the target and not touched by the DAG
883 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
888 /// GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of
889 /// the most recent dynamic alloca. For most targets that would be 0, but
890 /// for some others (e.g. PowerPC, PowerPC64) that would be compile-time
891 /// known nonzero constant. The only operand here is the chain.
892 GET_DYNAMIC_AREA_OFFSET
,
894 /// Generic reduction nodes. These nodes represent horizontal vector
895 /// reduction operations, producing a scalar result.
896 /// The STRICT variants perform reductions in sequential order. The first
897 /// operand is an initial scalar accumulator value, and the second operand
898 /// is the vector to reduce.
899 VECREDUCE_STRICT_FADD
, VECREDUCE_STRICT_FMUL
,
900 /// These reductions are non-strict, and have a single vector operand.
901 VECREDUCE_FADD
, VECREDUCE_FMUL
,
902 /// FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
903 VECREDUCE_FMAX
, VECREDUCE_FMIN
,
904 /// Integer reductions may have a result type larger than the vector element
905 /// type. However, the reduction is performed using the vector element type
906 /// and the value in the top bits is unspecified.
907 VECREDUCE_ADD
, VECREDUCE_MUL
,
908 VECREDUCE_AND
, VECREDUCE_OR
, VECREDUCE_XOR
,
909 VECREDUCE_SMAX
, VECREDUCE_SMIN
, VECREDUCE_UMAX
, VECREDUCE_UMIN
,
911 /// BUILTIN_OP_END - This must be the last enum value in this list.
912 /// The target-specific pre-isel opcode values start here.
916 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
917 /// which do not reference a specific memory location should be less than
918 /// this value. Those that do must not be less than this value, and can
919 /// be used with SelectionDAG::getMemIntrinsicNode.
920 static const int FIRST_TARGET_MEMORY_OPCODE
= BUILTIN_OP_END
+400;
922 //===--------------------------------------------------------------------===//
923 /// MemIndexedMode enum - This enum defines the load / store indexed
924 /// addressing modes.
926 /// UNINDEXED "Normal" load / store. The effective address is already
927 /// computed and is available in the base pointer. The offset
928 /// operand is always undefined. In addition to producing a
929 /// chain, an unindexed load produces one value (result of the
930 /// load); an unindexed store does not produce a value.
932 /// PRE_INC Similar to the unindexed mode where the effective address is
933 /// PRE_DEC the value of the base pointer add / subtract the offset.
934 /// It considers the computation as being folded into the load /
935 /// store operation (i.e. the load / store does the address
936 /// computation as well as performing the memory transaction).
937 /// The base operand is always undefined. In addition to
938 /// producing a chain, pre-indexed load produces two values
939 /// (result of the load and the result of the address
940 /// computation); a pre-indexed store produces one value (result
941 /// of the address computation).
943 /// POST_INC The effective address is the value of the base pointer. The
944 /// POST_DEC value of the offset operand is then added to / subtracted
945 /// from the base after memory transaction. In addition to
946 /// producing a chain, post-indexed load produces two values
947 /// (the result of the load and the result of the base +/- offset
948 /// computation); a post-indexed store produces one value (the
949 /// the result of the base +/- offset computation).
950 enum MemIndexedMode
{
958 static const int LAST_INDEXED_MODE
= POST_DEC
+ 1;
960 //===--------------------------------------------------------------------===//
961 /// MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's
962 /// index parameter when calculating addresses.
964 /// SIGNED_SCALED Addr = Base + ((signed)Index * sizeof(element))
965 /// SIGNED_UNSCALED Addr = Base + (signed)Index
966 /// UNSIGNED_SCALED Addr = Base + ((unsigned)Index * sizeof(element))
967 /// UNSIGNED_UNSCALED Addr = Base + (unsigned)Index
975 static const int LAST_MEM_INDEX_TYPE
= UNSIGNED_UNSCALED
+ 1;
977 //===--------------------------------------------------------------------===//
978 /// LoadExtType enum - This enum defines the three variants of LOADEXT
979 /// (load with extension).
981 /// SEXTLOAD loads the integer operand and sign extends it to a larger
982 /// integer result type.
983 /// ZEXTLOAD loads the integer operand and zero extends it to a larger
984 /// integer result type.
985 /// EXTLOAD is used for two things: floating point extending loads and
986 /// integer extending loads [the top bits are undefined].
994 static const int LAST_LOADEXT_TYPE
= ZEXTLOAD
+ 1;
996 NodeType
getExtForLoadExtType(bool IsFP
, LoadExtType
);
998 //===--------------------------------------------------------------------===//
999 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
1000 /// below work out, when considering SETFALSE (something that never exists
1001 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered
1002 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
1003 /// to. If the "N" column is 1, the result of the comparison is undefined if
1004 /// the input is a NAN.
1006 /// All of these (except for the 'always folded ops') should be handled for
1007 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
1008 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
1010 /// Note that these are laid out in a specific order to allow bit-twiddling
1011 /// to transform conditions.
1013 // Opcode N U L G E Intuitive operation
1014 SETFALSE
, // 0 0 0 0 Always false (always folded)
1015 SETOEQ
, // 0 0 0 1 True if ordered and equal
1016 SETOGT
, // 0 0 1 0 True if ordered and greater than
1017 SETOGE
, // 0 0 1 1 True if ordered and greater than or equal
1018 SETOLT
, // 0 1 0 0 True if ordered and less than
1019 SETOLE
, // 0 1 0 1 True if ordered and less than or equal
1020 SETONE
, // 0 1 1 0 True if ordered and operands are unequal
1021 SETO
, // 0 1 1 1 True if ordered (no nans)
1022 SETUO
, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
1023 SETUEQ
, // 1 0 0 1 True if unordered or equal
1024 SETUGT
, // 1 0 1 0 True if unordered or greater than
1025 SETUGE
, // 1 0 1 1 True if unordered, greater than, or equal
1026 SETULT
, // 1 1 0 0 True if unordered or less than
1027 SETULE
, // 1 1 0 1 True if unordered, less than, or equal
1028 SETUNE
, // 1 1 1 0 True if unordered or not equal
1029 SETTRUE
, // 1 1 1 1 Always true (always folded)
1030 // Don't care operations: undefined if the input is a nan.
1031 SETFALSE2
, // 1 X 0 0 0 Always false (always folded)
1032 SETEQ
, // 1 X 0 0 1 True if equal
1033 SETGT
, // 1 X 0 1 0 True if greater than
1034 SETGE
, // 1 X 0 1 1 True if greater than or equal
1035 SETLT
, // 1 X 1 0 0 True if less than
1036 SETLE
, // 1 X 1 0 1 True if less than or equal
1037 SETNE
, // 1 X 1 1 0 True if not equal
1038 SETTRUE2
, // 1 X 1 1 1 Always true (always folded)
1040 SETCC_INVALID
// Marker value.
1043 /// Return true if this is a setcc instruction that performs a signed
1044 /// comparison when used with integer operands.
1045 inline bool isSignedIntSetCC(CondCode Code
) {
1046 return Code
== SETGT
|| Code
== SETGE
|| Code
== SETLT
|| Code
== SETLE
;
1049 /// Return true if this is a setcc instruction that performs an unsigned
1050 /// comparison when used with integer operands.
1051 inline bool isUnsignedIntSetCC(CondCode Code
) {
1052 return Code
== SETUGT
|| Code
== SETUGE
|| Code
== SETULT
|| Code
== SETULE
;
1055 /// Return true if the specified condition returns true if the two operands to
1056 /// the condition are equal. Note that if one of the two operands is a NaN,
1057 /// this value is meaningless.
1058 inline bool isTrueWhenEqual(CondCode Cond
) {
1059 return ((int)Cond
& 1) != 0;
1062 /// This function returns 0 if the condition is always false if an operand is
1063 /// a NaN, 1 if the condition is always true if the operand is a NaN, and 2 if
1064 /// the condition is undefined if the operand is a NaN.
1065 inline unsigned getUnorderedFlavor(CondCode Cond
) {
1066 return ((int)Cond
>> 3) & 3;
1069 /// Return the operation corresponding to !(X op Y), where 'op' is a valid
1070 /// SetCC operation.
1071 CondCode
getSetCCInverse(CondCode Operation
, bool isInteger
);
1073 /// Return the operation corresponding to (Y op X) when given the operation
1075 CondCode
getSetCCSwappedOperands(CondCode Operation
);
1077 /// Return the result of a logical OR between different comparisons of
1078 /// identical values: ((X op1 Y) | (X op2 Y)). This function returns
1079 /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1080 CondCode
getSetCCOrOperation(CondCode Op1
, CondCode Op2
, bool isInteger
);
1082 /// Return the result of a logical AND between different comparisons of
1083 /// identical values: ((X op1 Y) & (X op2 Y)). This function returns
1084 /// SETCC_INVALID if it is not possible to represent the resultant comparison.
1085 CondCode
getSetCCAndOperation(CondCode Op1
, CondCode Op2
, bool isInteger
);
1087 } // end llvm::ISD namespace
1089 } // end llvm namespace