1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the declaration of the MachineInstr class, which is the
10 // basic representation for all target dependent machine instructions used by
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
18 #include "llvm/ADT/DenseMapInfo.h"
19 #include "llvm/ADT/PointerSumType.h"
20 #include "llvm/ADT/ilist.h"
21 #include "llvm/ADT/ilist_node.h"
22 #include "llvm/ADT/iterator_range.h"
23 #include "llvm/Analysis/AliasAnalysis.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/MachineOperand.h"
26 #include "llvm/CodeGen/TargetOpcodes.h"
27 #include "llvm/IR/DebugInfoMetadata.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCSymbol.h"
32 #include "llvm/Support/ArrayRecycler.h"
33 #include "llvm/Support/TrailingObjects.h"
41 template <typename T
> class ArrayRef
;
43 class DILocalVariable
;
44 class MachineBasicBlock
;
45 class MachineFunction
;
46 class MachineMemOperand
;
47 class MachineRegisterInfo
;
48 class ModuleSlotTracker
;
50 template <typename T
> class SmallVectorImpl
;
53 class TargetInstrInfo
;
54 class TargetRegisterClass
;
55 class TargetRegisterInfo
;
57 //===----------------------------------------------------------------------===//
58 /// Representation of each machine instruction.
60 /// This class isn't a POD type, but it must have a trivial destructor. When a
61 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
62 /// without having their destructor called.
65 : public ilist_node_with_parent
<MachineInstr
, MachineBasicBlock
,
66 ilist_sentinel_tracking
<true>> {
68 using mmo_iterator
= ArrayRef
<MachineMemOperand
*>::iterator
;
70 /// Flags to specify different kinds of comments to output in
71 /// assembly code. These flags carry semantic information not
72 /// otherwise easily derivable from the IR text.
75 ReloadReuse
= 0x1, // higher bits are reserved for target dep comments.
77 TAsmComments
= 0x4 // Target Asm comments should start from this value.
82 FrameSetup
= 1 << 0, // Instruction is used as a part of
83 // function frame setup code.
84 FrameDestroy
= 1 << 1, // Instruction is used as a part of
85 // function frame destruction code.
86 BundledPred
= 1 << 2, // Instruction has bundled predecessors.
87 BundledSucc
= 1 << 3, // Instruction has bundled successors.
88 FmNoNans
= 1 << 4, // Instruction does not support Fast
90 FmNoInfs
= 1 << 5, // Instruction does not support Fast
91 // math infinity values.
92 FmNsz
= 1 << 6, // Instruction is not required to retain
93 // signed zero values.
94 FmArcp
= 1 << 7, // Instruction supports Fast math
95 // reciprocal approximations.
96 FmContract
= 1 << 8, // Instruction supports Fast math
97 // contraction operations like fma.
98 FmAfn
= 1 << 9, // Instruction may map to Fast math
99 // instrinsic approximation.
100 FmReassoc
= 1 << 10, // Instruction supports Fast math
101 // reassociation of operand order.
102 NoUWrap
= 1 << 11, // Instruction supports binary operator
104 NoSWrap
= 1 << 12, // Instruction supports binary operator
106 IsExact
= 1 << 13, // Instruction supports division is
107 // known to be exact.
108 FPExcept
= 1 << 14, // Instruction may raise floating-point
113 const MCInstrDesc
*MCID
; // Instruction descriptor.
114 MachineBasicBlock
*Parent
= nullptr; // Pointer to the owning basic block.
116 // Operands are allocated by an ArrayRecycler.
117 MachineOperand
*Operands
= nullptr; // Pointer to the first operand.
118 unsigned NumOperands
= 0; // Number of operands on instruction.
119 using OperandCapacity
= ArrayRecycler
<MachineOperand
>::Capacity
;
120 OperandCapacity CapOperands
; // Capacity of the Operands array.
122 uint16_t Flags
= 0; // Various bits of additional
123 // information about machine
126 uint8_t AsmPrinterFlags
= 0; // Various bits of information used by
127 // the AsmPrinter to emit helpful
128 // comments. This is *not* semantic
129 // information. Do not use this for
130 // anything other than to convey comment
131 // information to AsmPrinter.
133 /// Internal implementation detail class that provides out-of-line storage for
134 /// extra info used by the machine instruction when this info cannot be stored
135 /// in-line within the instruction itself.
137 /// This has to be defined eagerly due to the implementation constraints of
138 /// `PointerSumType` where it is used.
139 class ExtraInfo final
140 : TrailingObjects
<ExtraInfo
, MachineMemOperand
*, MCSymbol
*> {
142 static ExtraInfo
*create(BumpPtrAllocator
&Allocator
,
143 ArrayRef
<MachineMemOperand
*> MMOs
,
144 MCSymbol
*PreInstrSymbol
= nullptr,
145 MCSymbol
*PostInstrSymbol
= nullptr) {
146 bool HasPreInstrSymbol
= PreInstrSymbol
!= nullptr;
147 bool HasPostInstrSymbol
= PostInstrSymbol
!= nullptr;
148 auto *Result
= new (Allocator
.Allocate(
149 totalSizeToAlloc
<MachineMemOperand
*, MCSymbol
*>(
150 MMOs
.size(), HasPreInstrSymbol
+ HasPostInstrSymbol
),
152 ExtraInfo(MMOs
.size(), HasPreInstrSymbol
, HasPostInstrSymbol
);
154 // Copy the actual data into the trailing objects.
155 std::copy(MMOs
.begin(), MMOs
.end(),
156 Result
->getTrailingObjects
<MachineMemOperand
*>());
158 if (HasPreInstrSymbol
)
159 Result
->getTrailingObjects
<MCSymbol
*>()[0] = PreInstrSymbol
;
160 if (HasPostInstrSymbol
)
161 Result
->getTrailingObjects
<MCSymbol
*>()[HasPreInstrSymbol
] =
167 ArrayRef
<MachineMemOperand
*> getMMOs() const {
168 return makeArrayRef(getTrailingObjects
<MachineMemOperand
*>(), NumMMOs
);
171 MCSymbol
*getPreInstrSymbol() const {
172 return HasPreInstrSymbol
? getTrailingObjects
<MCSymbol
*>()[0] : nullptr;
175 MCSymbol
*getPostInstrSymbol() const {
176 return HasPostInstrSymbol
177 ? getTrailingObjects
<MCSymbol
*>()[HasPreInstrSymbol
]
182 friend TrailingObjects
;
184 // Description of the extra info, used to interpret the actual optional
187 // Note that this is not terribly space optimized. This leaves a great deal
188 // of flexibility to fit more in here later.
190 const bool HasPreInstrSymbol
;
191 const bool HasPostInstrSymbol
;
193 // Implement the `TrailingObjects` internal API.
194 size_t numTrailingObjects(OverloadToken
<MachineMemOperand
*>) const {
197 size_t numTrailingObjects(OverloadToken
<MCSymbol
*>) const {
198 return HasPreInstrSymbol
+ HasPostInstrSymbol
;
201 // Just a boring constructor to allow us to initialize the sizes. Always use
202 // the `create` routine above.
203 ExtraInfo(int NumMMOs
, bool HasPreInstrSymbol
, bool HasPostInstrSymbol
)
204 : NumMMOs(NumMMOs
), HasPreInstrSymbol(HasPreInstrSymbol
),
205 HasPostInstrSymbol(HasPostInstrSymbol
) {}
208 /// Enumeration of the kinds of inline extra info available. It is important
209 /// that the `MachineMemOperand` inline kind has a tag value of zero to make
210 /// it accessible as an `ArrayRef`.
211 enum ExtraInfoInlineKinds
{
214 EIIK_PostInstrSymbol
,
218 // We store extra information about the instruction here. The common case is
219 // expected to be nothing or a single pointer (typically a MMO or a symbol).
220 // We work to optimize this common case by storing it inline here rather than
221 // requiring a separate allocation, but we fall back to an allocation when
222 // multiple pointers are needed.
223 PointerSumType
<ExtraInfoInlineKinds
,
224 PointerSumTypeMember
<EIIK_MMO
, MachineMemOperand
*>,
225 PointerSumTypeMember
<EIIK_PreInstrSymbol
, MCSymbol
*>,
226 PointerSumTypeMember
<EIIK_PostInstrSymbol
, MCSymbol
*>,
227 PointerSumTypeMember
<EIIK_OutOfLine
, ExtraInfo
*>>
230 DebugLoc debugLoc
; // Source line information.
232 // Intrusive list support
233 friend struct ilist_traits
<MachineInstr
>;
234 friend struct ilist_callback_traits
<MachineBasicBlock
>;
235 void setParent(MachineBasicBlock
*P
) { Parent
= P
; }
237 /// This constructor creates a copy of the given
238 /// MachineInstr in the given MachineFunction.
239 MachineInstr(MachineFunction
&, const MachineInstr
&);
241 /// This constructor create a MachineInstr and add the implicit operands.
242 /// It reserves space for number of operands specified by
243 /// MCInstrDesc. An explicit DebugLoc is supplied.
244 MachineInstr(MachineFunction
&, const MCInstrDesc
&tid
, DebugLoc dl
,
247 // MachineInstrs are pool-allocated and owned by MachineFunction.
248 friend class MachineFunction
;
251 MachineInstr(const MachineInstr
&) = delete;
252 MachineInstr
&operator=(const MachineInstr
&) = delete;
253 // Use MachineFunction::DeleteMachineInstr() instead.
254 ~MachineInstr() = delete;
256 const MachineBasicBlock
* getParent() const { return Parent
; }
257 MachineBasicBlock
* getParent() { return Parent
; }
259 /// Return the function that contains the basic block that this instruction
262 /// Note: this is undefined behaviour if the instruction does not have a
264 const MachineFunction
*getMF() const;
265 MachineFunction
*getMF() {
266 return const_cast<MachineFunction
*>(
267 static_cast<const MachineInstr
*>(this)->getMF());
270 /// Return the asm printer flags bitvector.
271 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags
; }
273 /// Clear the AsmPrinter bitvector.
274 void clearAsmPrinterFlags() { AsmPrinterFlags
= 0; }
276 /// Return whether an AsmPrinter flag is set.
277 bool getAsmPrinterFlag(CommentFlag Flag
) const {
278 return AsmPrinterFlags
& Flag
;
281 /// Set a flag for the AsmPrinter.
282 void setAsmPrinterFlag(uint8_t Flag
) {
283 AsmPrinterFlags
|= Flag
;
286 /// Clear specific AsmPrinter flags.
287 void clearAsmPrinterFlag(CommentFlag Flag
) {
288 AsmPrinterFlags
&= ~Flag
;
291 /// Return the MI flags bitvector.
292 uint16_t getFlags() const {
296 /// Return whether an MI flag is set.
297 bool getFlag(MIFlag Flag
) const {
302 void setFlag(MIFlag Flag
) {
303 Flags
|= (uint16_t)Flag
;
306 void setFlags(unsigned flags
) {
307 // Filter out the automatically maintained flags.
308 unsigned Mask
= BundledPred
| BundledSucc
;
309 Flags
= (Flags
& Mask
) | (flags
& ~Mask
);
312 /// clearFlag - Clear a MI flag.
313 void clearFlag(MIFlag Flag
) {
314 Flags
&= ~((uint16_t)Flag
);
317 /// Return true if MI is in a bundle (but not the first MI in a bundle).
319 /// A bundle looks like this before it's finalized:
331 /// In this case, the first MI starts a bundle but is not inside a bundle, the
332 /// next 2 MIs are considered "inside" the bundle.
334 /// After a bundle is finalized, it looks like this:
350 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
351 /// a bundle, but the next three MIs are.
352 bool isInsideBundle() const {
353 return getFlag(BundledPred
);
356 /// Return true if this instruction part of a bundle. This is true
357 /// if either itself or its following instruction is marked "InsideBundle".
358 bool isBundled() const {
359 return isBundledWithPred() || isBundledWithSucc();
362 /// Return true if this instruction is part of a bundle, and it is not the
363 /// first instruction in the bundle.
364 bool isBundledWithPred() const { return getFlag(BundledPred
); }
366 /// Return true if this instruction is part of a bundle, and it is not the
367 /// last instruction in the bundle.
368 bool isBundledWithSucc() const { return getFlag(BundledSucc
); }
370 /// Bundle this instruction with its predecessor. This can be an unbundled
371 /// instruction, or it can be the first instruction in a bundle.
372 void bundleWithPred();
374 /// Bundle this instruction with its successor. This can be an unbundled
375 /// instruction, or it can be the last instruction in a bundle.
376 void bundleWithSucc();
378 /// Break bundle above this instruction.
379 void unbundleFromPred();
381 /// Break bundle below this instruction.
382 void unbundleFromSucc();
384 /// Returns the debug location id of this MachineInstr.
385 const DebugLoc
&getDebugLoc() const { return debugLoc
; }
387 /// Return the debug variable referenced by
388 /// this DBG_VALUE instruction.
389 const DILocalVariable
*getDebugVariable() const;
391 /// Return the complex address expression referenced by
392 /// this DBG_VALUE instruction.
393 const DIExpression
*getDebugExpression() const;
395 /// Return the debug label referenced by
396 /// this DBG_LABEL instruction.
397 const DILabel
*getDebugLabel() const;
399 /// Emit an error referring to the source location of this instruction.
400 /// This should only be used for inline assembly that is somehow
401 /// impossible to compile. Other errors should have been handled much
404 /// If this method returns, the caller should try to recover from the error.
405 void emitError(StringRef Msg
) const;
407 /// Returns the target instruction descriptor of this MachineInstr.
408 const MCInstrDesc
&getDesc() const { return *MCID
; }
410 /// Returns the opcode of this MachineInstr.
411 unsigned getOpcode() const { return MCID
->Opcode
; }
413 /// Retuns the total number of operands.
414 unsigned getNumOperands() const { return NumOperands
; }
416 const MachineOperand
& getOperand(unsigned i
) const {
417 assert(i
< getNumOperands() && "getOperand() out of range!");
420 MachineOperand
& getOperand(unsigned i
) {
421 assert(i
< getNumOperands() && "getOperand() out of range!");
425 /// Returns the total number of definitions.
426 unsigned getNumDefs() const {
427 return getNumExplicitDefs() + MCID
->getNumImplicitDefs();
430 /// Returns true if the instruction has implicit definition.
431 bool hasImplicitDef() const {
432 for (unsigned I
= getNumExplicitOperands(), E
= getNumOperands();
434 const MachineOperand
&MO
= getOperand(I
);
435 if (MO
.isDef() && MO
.isImplicit())
441 /// Returns the implicit operands number.
442 unsigned getNumImplicitOperands() const {
443 return getNumOperands() - getNumExplicitOperands();
446 /// Return true if operand \p OpIdx is a subregister index.
447 bool isOperandSubregIdx(unsigned OpIdx
) const {
448 assert(getOperand(OpIdx
).getType() == MachineOperand::MO_Immediate
&&
449 "Expected MO_Immediate operand type.");
450 if (isExtractSubreg() && OpIdx
== 2)
452 if (isInsertSubreg() && OpIdx
== 3)
454 if (isRegSequence() && OpIdx
> 1 && (OpIdx
% 2) == 0)
456 if (isSubregToReg() && OpIdx
== 3)
461 /// Returns the number of non-implicit operands.
462 unsigned getNumExplicitOperands() const;
464 /// Returns the number of non-implicit definitions.
465 unsigned getNumExplicitDefs() const;
467 /// iterator/begin/end - Iterate over all operands of a machine instruction.
468 using mop_iterator
= MachineOperand
*;
469 using const_mop_iterator
= const MachineOperand
*;
471 mop_iterator
operands_begin() { return Operands
; }
472 mop_iterator
operands_end() { return Operands
+ NumOperands
; }
474 const_mop_iterator
operands_begin() const { return Operands
; }
475 const_mop_iterator
operands_end() const { return Operands
+ NumOperands
; }
477 iterator_range
<mop_iterator
> operands() {
478 return make_range(operands_begin(), operands_end());
480 iterator_range
<const_mop_iterator
> operands() const {
481 return make_range(operands_begin(), operands_end());
483 iterator_range
<mop_iterator
> explicit_operands() {
484 return make_range(operands_begin(),
485 operands_begin() + getNumExplicitOperands());
487 iterator_range
<const_mop_iterator
> explicit_operands() const {
488 return make_range(operands_begin(),
489 operands_begin() + getNumExplicitOperands());
491 iterator_range
<mop_iterator
> implicit_operands() {
492 return make_range(explicit_operands().end(), operands_end());
494 iterator_range
<const_mop_iterator
> implicit_operands() const {
495 return make_range(explicit_operands().end(), operands_end());
497 /// Returns a range over all explicit operands that are register definitions.
498 /// Implicit definition are not included!
499 iterator_range
<mop_iterator
> defs() {
500 return make_range(operands_begin(),
501 operands_begin() + getNumExplicitDefs());
504 iterator_range
<const_mop_iterator
> defs() const {
505 return make_range(operands_begin(),
506 operands_begin() + getNumExplicitDefs());
508 /// Returns a range that includes all operands that are register uses.
509 /// This may include unrelated operands which are not register uses.
510 iterator_range
<mop_iterator
> uses() {
511 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
514 iterator_range
<const_mop_iterator
> uses() const {
515 return make_range(operands_begin() + getNumExplicitDefs(), operands_end());
517 iterator_range
<mop_iterator
> explicit_uses() {
518 return make_range(operands_begin() + getNumExplicitDefs(),
519 operands_begin() + getNumExplicitOperands());
521 iterator_range
<const_mop_iterator
> explicit_uses() const {
522 return make_range(operands_begin() + getNumExplicitDefs(),
523 operands_begin() + getNumExplicitOperands());
526 /// Returns the number of the operand iterator \p I points to.
527 unsigned getOperandNo(const_mop_iterator I
) const {
528 return I
- operands_begin();
531 /// Access to memory operands of the instruction. If there are none, that does
532 /// not imply anything about whether the function accesses memory. Instead,
533 /// the caller must behave conservatively.
534 ArrayRef
<MachineMemOperand
*> memoperands() const {
538 if (Info
.is
<EIIK_MMO
>())
539 return makeArrayRef(Info
.getAddrOfZeroTagPointer(), 1);
541 if (ExtraInfo
*EI
= Info
.get
<EIIK_OutOfLine
>())
542 return EI
->getMMOs();
547 /// Access to memory operands of the instruction.
549 /// If `memoperands_begin() == memoperands_end()`, that does not imply
550 /// anything about whether the function accesses memory. Instead, the caller
551 /// must behave conservatively.
552 mmo_iterator
memoperands_begin() const { return memoperands().begin(); }
554 /// Access to memory operands of the instruction.
556 /// If `memoperands_begin() == memoperands_end()`, that does not imply
557 /// anything about whether the function accesses memory. Instead, the caller
558 /// must behave conservatively.
559 mmo_iterator
memoperands_end() const { return memoperands().end(); }
561 /// Return true if we don't have any memory operands which described the
562 /// memory access done by this instruction. If this is true, calling code
563 /// must be conservative.
564 bool memoperands_empty() const { return memoperands().empty(); }
566 /// Return true if this instruction has exactly one MachineMemOperand.
567 bool hasOneMemOperand() const { return memoperands().size() == 1; }
569 /// Return the number of memory operands.
570 unsigned getNumMemOperands() const { return memoperands().size(); }
572 /// Helper to extract a pre-instruction symbol if one has been added.
573 MCSymbol
*getPreInstrSymbol() const {
576 if (MCSymbol
*S
= Info
.get
<EIIK_PreInstrSymbol
>())
578 if (ExtraInfo
*EI
= Info
.get
<EIIK_OutOfLine
>())
579 return EI
->getPreInstrSymbol();
584 /// Helper to extract a post-instruction symbol if one has been added.
585 MCSymbol
*getPostInstrSymbol() const {
588 if (MCSymbol
*S
= Info
.get
<EIIK_PostInstrSymbol
>())
590 if (ExtraInfo
*EI
= Info
.get
<EIIK_OutOfLine
>())
591 return EI
->getPostInstrSymbol();
596 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
597 /// queries but they are bundle aware.
600 IgnoreBundle
, // Ignore bundles
601 AnyInBundle
, // Return true if any instruction in bundle has property
602 AllInBundle
// Return true if all instructions in bundle have property
605 /// Return true if the instruction (or in the case of a bundle,
606 /// the instructions inside the bundle) has the specified property.
607 /// The first argument is the property being queried.
608 /// The second argument indicates whether the query should look inside
609 /// instruction bundles.
610 bool hasProperty(unsigned MCFlag
, QueryType Type
= AnyInBundle
) const {
611 assert(MCFlag
< 64 &&
612 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.");
613 // Inline the fast path for unbundled or bundle-internal instructions.
614 if (Type
== IgnoreBundle
|| !isBundled() || isBundledWithPred())
615 return getDesc().getFlags() & (1ULL << MCFlag
);
617 // If this is the first instruction in a bundle, take the slow path.
618 return hasPropertyInBundle(1ULL << MCFlag
, Type
);
621 /// Return true if this instruction can have a variable number of operands.
622 /// In this case, the variable operands will be after the normal
623 /// operands but before the implicit definitions and uses (if any are
625 bool isVariadic(QueryType Type
= IgnoreBundle
) const {
626 return hasProperty(MCID::Variadic
, Type
);
629 /// Set if this instruction has an optional definition, e.g.
630 /// ARM instructions which can set condition code if 's' bit is set.
631 bool hasOptionalDef(QueryType Type
= IgnoreBundle
) const {
632 return hasProperty(MCID::HasOptionalDef
, Type
);
635 /// Return true if this is a pseudo instruction that doesn't
636 /// correspond to a real machine instruction.
637 bool isPseudo(QueryType Type
= IgnoreBundle
) const {
638 return hasProperty(MCID::Pseudo
, Type
);
641 bool isReturn(QueryType Type
= AnyInBundle
) const {
642 return hasProperty(MCID::Return
, Type
);
645 /// Return true if this is an instruction that marks the end of an EH scope,
646 /// i.e., a catchpad or a cleanuppad instruction.
647 bool isEHScopeReturn(QueryType Type
= AnyInBundle
) const {
648 return hasProperty(MCID::EHScopeReturn
, Type
);
651 bool isCall(QueryType Type
= AnyInBundle
) const {
652 return hasProperty(MCID::Call
, Type
);
655 /// Returns true if the specified instruction stops control flow
656 /// from executing the instruction immediately following it. Examples include
657 /// unconditional branches and return instructions.
658 bool isBarrier(QueryType Type
= AnyInBundle
) const {
659 return hasProperty(MCID::Barrier
, Type
);
662 /// Returns true if this instruction part of the terminator for a basic block.
663 /// Typically this is things like return and branch instructions.
665 /// Various passes use this to insert code into the bottom of a basic block,
666 /// but before control flow occurs.
667 bool isTerminator(QueryType Type
= AnyInBundle
) const {
668 return hasProperty(MCID::Terminator
, Type
);
671 /// Returns true if this is a conditional, unconditional, or indirect branch.
672 /// Predicates below can be used to discriminate between
673 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
674 /// get more information.
675 bool isBranch(QueryType Type
= AnyInBundle
) const {
676 return hasProperty(MCID::Branch
, Type
);
679 /// Return true if this is an indirect branch, such as a
680 /// branch through a register.
681 bool isIndirectBranch(QueryType Type
= AnyInBundle
) const {
682 return hasProperty(MCID::IndirectBranch
, Type
);
685 /// Return true if this is a branch which may fall
686 /// through to the next instruction or may transfer control flow to some other
687 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
688 /// information about this branch.
689 bool isConditionalBranch(QueryType Type
= AnyInBundle
) const {
690 return isBranch(Type
) & !isBarrier(Type
) & !isIndirectBranch(Type
);
693 /// Return true if this is a branch which always
694 /// transfers control flow to some other block. The
695 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
696 /// about this branch.
697 bool isUnconditionalBranch(QueryType Type
= AnyInBundle
) const {
698 return isBranch(Type
) & isBarrier(Type
) & !isIndirectBranch(Type
);
701 /// Return true if this instruction has a predicate operand that
702 /// controls execution. It may be set to 'always', or may be set to other
703 /// values. There are various methods in TargetInstrInfo that can be used to
704 /// control and modify the predicate in this instruction.
705 bool isPredicable(QueryType Type
= AllInBundle
) const {
706 // If it's a bundle than all bundled instructions must be predicable for this
708 return hasProperty(MCID::Predicable
, Type
);
711 /// Return true if this instruction is a comparison.
712 bool isCompare(QueryType Type
= IgnoreBundle
) const {
713 return hasProperty(MCID::Compare
, Type
);
716 /// Return true if this instruction is a move immediate
717 /// (including conditional moves) instruction.
718 bool isMoveImmediate(QueryType Type
= IgnoreBundle
) const {
719 return hasProperty(MCID::MoveImm
, Type
);
722 /// Return true if this instruction is a register move.
723 /// (including moving values from subreg to reg)
724 bool isMoveReg(QueryType Type
= IgnoreBundle
) const {
725 return hasProperty(MCID::MoveReg
, Type
);
728 /// Return true if this instruction is a bitcast instruction.
729 bool isBitcast(QueryType Type
= IgnoreBundle
) const {
730 return hasProperty(MCID::Bitcast
, Type
);
733 /// Return true if this instruction is a select instruction.
734 bool isSelect(QueryType Type
= IgnoreBundle
) const {
735 return hasProperty(MCID::Select
, Type
);
738 /// Return true if this instruction cannot be safely duplicated.
739 /// For example, if the instruction has a unique labels attached
740 /// to it, duplicating it would cause multiple definition errors.
741 bool isNotDuplicable(QueryType Type
= AnyInBundle
) const {
742 return hasProperty(MCID::NotDuplicable
, Type
);
745 /// Return true if this instruction is convergent.
746 /// Convergent instructions can not be made control-dependent on any
747 /// additional values.
748 bool isConvergent(QueryType Type
= AnyInBundle
) const {
750 unsigned ExtraInfo
= getOperand(InlineAsm::MIOp_ExtraInfo
).getImm();
751 if (ExtraInfo
& InlineAsm::Extra_IsConvergent
)
754 return hasProperty(MCID::Convergent
, Type
);
757 /// Returns true if the specified instruction has a delay slot
758 /// which must be filled by the code generator.
759 bool hasDelaySlot(QueryType Type
= AnyInBundle
) const {
760 return hasProperty(MCID::DelaySlot
, Type
);
763 /// Return true for instructions that can be folded as
764 /// memory operands in other instructions. The most common use for this
765 /// is instructions that are simple loads from memory that don't modify
766 /// the loaded value in any way, but it can also be used for instructions
767 /// that can be expressed as constant-pool loads, such as V_SETALLONES
768 /// on x86, to allow them to be folded when it is beneficial.
769 /// This should only be set on instructions that return a value in their
770 /// only virtual register definition.
771 bool canFoldAsLoad(QueryType Type
= IgnoreBundle
) const {
772 return hasProperty(MCID::FoldableAsLoad
, Type
);
775 /// Return true if this instruction behaves
776 /// the same way as the generic REG_SEQUENCE instructions.
778 /// dX VMOVDRR rY, rZ
780 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
782 /// Note that for the optimizers to be able to take advantage of
783 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
784 /// override accordingly.
785 bool isRegSequenceLike(QueryType Type
= IgnoreBundle
) const {
786 return hasProperty(MCID::RegSequence
, Type
);
789 /// Return true if this instruction behaves
790 /// the same way as the generic EXTRACT_SUBREG instructions.
792 /// rX, rY VMOVRRD dZ
793 /// is equivalent to two EXTRACT_SUBREG:
794 /// rX = EXTRACT_SUBREG dZ, ssub_0
795 /// rY = EXTRACT_SUBREG dZ, ssub_1
797 /// Note that for the optimizers to be able to take advantage of
798 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
799 /// override accordingly.
800 bool isExtractSubregLike(QueryType Type
= IgnoreBundle
) const {
801 return hasProperty(MCID::ExtractSubreg
, Type
);
804 /// Return true if this instruction behaves
805 /// the same way as the generic INSERT_SUBREG instructions.
807 /// dX = VSETLNi32 dY, rZ, Imm
808 /// is equivalent to a INSERT_SUBREG:
809 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
811 /// Note that for the optimizers to be able to take advantage of
812 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
813 /// override accordingly.
814 bool isInsertSubregLike(QueryType Type
= IgnoreBundle
) const {
815 return hasProperty(MCID::InsertSubreg
, Type
);
818 //===--------------------------------------------------------------------===//
819 // Side Effect Analysis
820 //===--------------------------------------------------------------------===//
822 /// Return true if this instruction could possibly read memory.
823 /// Instructions with this flag set are not necessarily simple load
824 /// instructions, they may load a value and modify it, for example.
825 bool mayLoad(QueryType Type
= AnyInBundle
) const {
827 unsigned ExtraInfo
= getOperand(InlineAsm::MIOp_ExtraInfo
).getImm();
828 if (ExtraInfo
& InlineAsm::Extra_MayLoad
)
831 return hasProperty(MCID::MayLoad
, Type
);
834 /// Return true if this instruction could possibly modify memory.
835 /// Instructions with this flag set are not necessarily simple store
836 /// instructions, they may store a modified value based on their operands, or
837 /// may not actually modify anything, for example.
838 bool mayStore(QueryType Type
= AnyInBundle
) const {
840 unsigned ExtraInfo
= getOperand(InlineAsm::MIOp_ExtraInfo
).getImm();
841 if (ExtraInfo
& InlineAsm::Extra_MayStore
)
844 return hasProperty(MCID::MayStore
, Type
);
847 /// Return true if this instruction could possibly read or modify memory.
848 bool mayLoadOrStore(QueryType Type
= AnyInBundle
) const {
849 return mayLoad(Type
) || mayStore(Type
);
852 /// Return true if this instruction could possibly raise a floating-point
853 /// exception. This is the case if the instruction is a floating-point
854 /// instruction that can in principle raise an exception, as indicated
855 /// by the MCID::MayRaiseFPException property, *and* at the same time,
856 /// the instruction is used in a context where we expect floating-point
857 /// exceptions might be enabled, as indicated by the FPExcept MI flag.
858 bool mayRaiseFPException() const {
859 return hasProperty(MCID::MayRaiseFPException
) &&
860 getFlag(MachineInstr::MIFlag::FPExcept
);
863 //===--------------------------------------------------------------------===//
864 // Flags that indicate whether an instruction can be modified by a method.
865 //===--------------------------------------------------------------------===//
867 /// Return true if this may be a 2- or 3-address
868 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
869 /// result if Y and Z are exchanged. If this flag is set, then the
870 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
873 /// Note that this flag may be set on instructions that are only commutable
874 /// sometimes. In these cases, the call to commuteInstruction will fail.
875 /// Also note that some instructions require non-trivial modification to
877 bool isCommutable(QueryType Type
= IgnoreBundle
) const {
878 return hasProperty(MCID::Commutable
, Type
);
881 /// Return true if this is a 2-address instruction
882 /// which can be changed into a 3-address instruction if needed. Doing this
883 /// transformation can be profitable in the register allocator, because it
884 /// means that the instruction can use a 2-address form if possible, but
885 /// degrade into a less efficient form if the source and dest register cannot
886 /// be assigned to the same register. For example, this allows the x86
887 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
888 /// is the same speed as the shift but has bigger code size.
890 /// If this returns true, then the target must implement the
891 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
892 /// is allowed to fail if the transformation isn't valid for this specific
893 /// instruction (e.g. shl reg, 4 on x86).
895 bool isConvertibleTo3Addr(QueryType Type
= IgnoreBundle
) const {
896 return hasProperty(MCID::ConvertibleTo3Addr
, Type
);
899 /// Return true if this instruction requires
900 /// custom insertion support when the DAG scheduler is inserting it into a
901 /// machine basic block. If this is true for the instruction, it basically
902 /// means that it is a pseudo instruction used at SelectionDAG time that is
903 /// expanded out into magic code by the target when MachineInstrs are formed.
905 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
906 /// is used to insert this into the MachineBasicBlock.
907 bool usesCustomInsertionHook(QueryType Type
= IgnoreBundle
) const {
908 return hasProperty(MCID::UsesCustomInserter
, Type
);
911 /// Return true if this instruction requires *adjustment*
912 /// after instruction selection by calling a target hook. For example, this
913 /// can be used to fill in ARM 's' optional operand depending on whether
914 /// the conditional flag register is used.
915 bool hasPostISelHook(QueryType Type
= IgnoreBundle
) const {
916 return hasProperty(MCID::HasPostISelHook
, Type
);
919 /// Returns true if this instruction is a candidate for remat.
920 /// This flag is deprecated, please don't use it anymore. If this
921 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
922 /// verify the instruction is really rematable.
923 bool isRematerializable(QueryType Type
= AllInBundle
) const {
924 // It's only possible to re-mat a bundle if all bundled instructions are
925 // re-materializable.
926 return hasProperty(MCID::Rematerializable
, Type
);
929 /// Returns true if this instruction has the same cost (or less) than a move
930 /// instruction. This is useful during certain types of optimizations
931 /// (e.g., remat during two-address conversion or machine licm)
932 /// where we would like to remat or hoist the instruction, but not if it costs
933 /// more than moving the instruction into the appropriate register. Note, we
934 /// are not marking copies from and to the same register class with this flag.
935 bool isAsCheapAsAMove(QueryType Type
= AllInBundle
) const {
936 // Only returns true for a bundle if all bundled instructions are cheap.
937 return hasProperty(MCID::CheapAsAMove
, Type
);
940 /// Returns true if this instruction source operands
941 /// have special register allocation requirements that are not captured by the
942 /// operand register classes. e.g. ARM::STRD's two source registers must be an
943 /// even / odd pair, ARM::STM registers have to be in ascending order.
944 /// Post-register allocation passes should not attempt to change allocations
945 /// for sources of instructions with this flag.
946 bool hasExtraSrcRegAllocReq(QueryType Type
= AnyInBundle
) const {
947 return hasProperty(MCID::ExtraSrcRegAllocReq
, Type
);
950 /// Returns true if this instruction def operands
951 /// have special register allocation requirements that are not captured by the
952 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
953 /// even / odd pair, ARM::LDM registers have to be in ascending order.
954 /// Post-register allocation passes should not attempt to change allocations
955 /// for definitions of instructions with this flag.
956 bool hasExtraDefRegAllocReq(QueryType Type
= AnyInBundle
) const {
957 return hasProperty(MCID::ExtraDefRegAllocReq
, Type
);
961 CheckDefs
, // Check all operands for equality
962 CheckKillDead
, // Check all operands including kill / dead markers
963 IgnoreDefs
, // Ignore all definitions
964 IgnoreVRegDefs
// Ignore virtual register definitions
967 /// Return true if this instruction is identical to \p Other.
968 /// Two instructions are identical if they have the same opcode and all their
969 /// operands are identical (with respect to MachineOperand::isIdenticalTo()).
970 /// Note that this means liveness related flags (dead, undef, kill) do not
971 /// affect the notion of identical.
972 bool isIdenticalTo(const MachineInstr
&Other
,
973 MICheckType Check
= CheckDefs
) const;
975 /// Unlink 'this' from the containing basic block, and return it without
978 /// This function can not be used on bundled instructions, use
979 /// removeFromBundle() to remove individual instructions from a bundle.
980 MachineInstr
*removeFromParent();
982 /// Unlink this instruction from its basic block and return it without
985 /// If the instruction is part of a bundle, the other instructions in the
986 /// bundle remain bundled.
987 MachineInstr
*removeFromBundle();
989 /// Unlink 'this' from the containing basic block and delete it.
991 /// If this instruction is the header of a bundle, the whole bundle is erased.
992 /// This function can not be used for instructions inside a bundle, use
993 /// eraseFromBundle() to erase individual bundled instructions.
994 void eraseFromParent();
996 /// Unlink 'this' from the containing basic block and delete it.
998 /// For all definitions mark their uses in DBG_VALUE nodes
999 /// as undefined. Otherwise like eraseFromParent().
1000 void eraseFromParentAndMarkDBGValuesForRemoval();
1002 /// Unlink 'this' form its basic block and delete it.
1004 /// If the instruction is part of a bundle, the other instructions in the
1005 /// bundle remain bundled.
1006 void eraseFromBundle();
1008 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL
; }
1009 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL
; }
1010 bool isAnnotationLabel() const {
1011 return getOpcode() == TargetOpcode::ANNOTATION_LABEL
;
1014 /// Returns true if the MachineInstr represents a label.
1015 bool isLabel() const {
1016 return isEHLabel() || isGCLabel() || isAnnotationLabel();
1019 bool isCFIInstruction() const {
1020 return getOpcode() == TargetOpcode::CFI_INSTRUCTION
;
1023 // True if the instruction represents a position in the function.
1024 bool isPosition() const { return isLabel() || isCFIInstruction(); }
1026 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE
; }
1027 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL
; }
1028 bool isDebugInstr() const { return isDebugValue() || isDebugLabel(); }
1030 /// A DBG_VALUE is indirect iff the first operand is a register and
1031 /// the second operand is an immediate.
1032 bool isIndirectDebugValue() const {
1033 return isDebugValue()
1034 && getOperand(0).isReg()
1035 && getOperand(1).isImm();
1038 /// A DBG_VALUE is an entry value iff its debug expression contains the
1039 /// DW_OP_entry_value DWARF operation.
1040 bool isDebugEntryValue() const {
1041 return isDebugValue() && getDebugExpression()->isEntryValue();
1044 /// Return true if the instruction is a debug value which describes a part of
1045 /// a variable as unavailable.
1046 bool isUndefDebugValue() const {
1047 return isDebugValue() && getOperand(0).isReg() && !getOperand(0).getReg().isValid();
1050 bool isPHI() const {
1051 return getOpcode() == TargetOpcode::PHI
||
1052 getOpcode() == TargetOpcode::G_PHI
;
1054 bool isKill() const { return getOpcode() == TargetOpcode::KILL
; }
1055 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF
; }
1056 bool isInlineAsm() const {
1057 return getOpcode() == TargetOpcode::INLINEASM
||
1058 getOpcode() == TargetOpcode::INLINEASM_BR
;
1061 /// FIXME: Seems like a layering violation that the AsmDialect, which is X86
1062 /// specific, be attached to a generic MachineInstr.
1063 bool isMSInlineAsm() const {
1064 return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel
;
1067 bool isStackAligningInlineAsm() const;
1068 InlineAsm::AsmDialect
getInlineAsmDialect() const;
1070 bool isInsertSubreg() const {
1071 return getOpcode() == TargetOpcode::INSERT_SUBREG
;
1074 bool isSubregToReg() const {
1075 return getOpcode() == TargetOpcode::SUBREG_TO_REG
;
1078 bool isRegSequence() const {
1079 return getOpcode() == TargetOpcode::REG_SEQUENCE
;
1082 bool isBundle() const {
1083 return getOpcode() == TargetOpcode::BUNDLE
;
1086 bool isCopy() const {
1087 return getOpcode() == TargetOpcode::COPY
;
1090 bool isFullCopy() const {
1091 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
1094 bool isExtractSubreg() const {
1095 return getOpcode() == TargetOpcode::EXTRACT_SUBREG
;
1098 /// Return true if the instruction behaves like a copy.
1099 /// This does not include native copy instructions.
1100 bool isCopyLike() const {
1101 return isCopy() || isSubregToReg();
1104 /// Return true is the instruction is an identity copy.
1105 bool isIdentityCopy() const {
1106 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1107 getOperand(0).getSubReg() == getOperand(1).getSubReg();
1110 /// Return true if this instruction doesn't produce any output in the form of
1111 /// executable instructions.
1112 bool isMetaInstruction() const {
1113 switch (getOpcode()) {
1116 case TargetOpcode::IMPLICIT_DEF
:
1117 case TargetOpcode::KILL
:
1118 case TargetOpcode::CFI_INSTRUCTION
:
1119 case TargetOpcode::EH_LABEL
:
1120 case TargetOpcode::GC_LABEL
:
1121 case TargetOpcode::DBG_VALUE
:
1122 case TargetOpcode::DBG_LABEL
:
1123 case TargetOpcode::LIFETIME_START
:
1124 case TargetOpcode::LIFETIME_END
:
1129 /// Return true if this is a transient instruction that is either very likely
1130 /// to be eliminated during register allocation (such as copy-like
1131 /// instructions), or if this instruction doesn't have an execution-time cost.
1132 bool isTransient() const {
1133 switch (getOpcode()) {
1135 return isMetaInstruction();
1136 // Copy-like instructions are usually eliminated during register allocation.
1137 case TargetOpcode::PHI
:
1138 case TargetOpcode::G_PHI
:
1139 case TargetOpcode::COPY
:
1140 case TargetOpcode::INSERT_SUBREG
:
1141 case TargetOpcode::SUBREG_TO_REG
:
1142 case TargetOpcode::REG_SEQUENCE
:
1147 /// Return the number of instructions inside the MI bundle, excluding the
1150 /// This is the number of instructions that MachineBasicBlock::iterator
1151 /// skips, 0 for unbundled instructions.
1152 unsigned getBundleSize() const;
1154 /// Return true if the MachineInstr reads the specified register.
1155 /// If TargetRegisterInfo is passed, then it also checks if there
1156 /// is a read of a super-register.
1157 /// This does not count partial redefines of virtual registers as reads:
1158 /// %reg1024:6 = OP.
1159 bool readsRegister(Register Reg
,
1160 const TargetRegisterInfo
*TRI
= nullptr) const {
1161 return findRegisterUseOperandIdx(Reg
, false, TRI
) != -1;
1164 /// Return true if the MachineInstr reads the specified virtual register.
1165 /// Take into account that a partial define is a
1166 /// read-modify-write operation.
1167 bool readsVirtualRegister(Register Reg
) const {
1168 return readsWritesVirtualRegister(Reg
).first
;
1171 /// Return a pair of bools (reads, writes) indicating if this instruction
1172 /// reads or writes Reg. This also considers partial defines.
1173 /// If Ops is not null, all operand indices for Reg are added.
1174 std::pair
<bool,bool> readsWritesVirtualRegister(Register Reg
,
1175 SmallVectorImpl
<unsigned> *Ops
= nullptr) const;
1177 /// Return true if the MachineInstr kills the specified register.
1178 /// If TargetRegisterInfo is passed, then it also checks if there is
1179 /// a kill of a super-register.
1180 bool killsRegister(Register Reg
,
1181 const TargetRegisterInfo
*TRI
= nullptr) const {
1182 return findRegisterUseOperandIdx(Reg
, true, TRI
) != -1;
1185 /// Return true if the MachineInstr fully defines the specified register.
1186 /// If TargetRegisterInfo is passed, then it also checks
1187 /// if there is a def of a super-register.
1188 /// NOTE: It's ignoring subreg indices on virtual registers.
1189 bool definesRegister(Register Reg
,
1190 const TargetRegisterInfo
*TRI
= nullptr) const {
1191 return findRegisterDefOperandIdx(Reg
, false, false, TRI
) != -1;
1194 /// Return true if the MachineInstr modifies (fully define or partially
1195 /// define) the specified register.
1196 /// NOTE: It's ignoring subreg indices on virtual registers.
1197 bool modifiesRegister(Register Reg
, const TargetRegisterInfo
*TRI
) const {
1198 return findRegisterDefOperandIdx(Reg
, false, true, TRI
) != -1;
1201 /// Returns true if the register is dead in this machine instruction.
1202 /// If TargetRegisterInfo is passed, then it also checks
1203 /// if there is a dead def of a super-register.
1204 bool registerDefIsDead(Register Reg
,
1205 const TargetRegisterInfo
*TRI
= nullptr) const {
1206 return findRegisterDefOperandIdx(Reg
, true, false, TRI
) != -1;
1209 /// Returns true if the MachineInstr has an implicit-use operand of exactly
1210 /// the given register (not considering sub/super-registers).
1211 bool hasRegisterImplicitUseOperand(Register Reg
) const;
1213 /// Returns the operand index that is a use of the specific register or -1
1214 /// if it is not found. It further tightens the search criteria to a use
1215 /// that kills the register if isKill is true.
1216 int findRegisterUseOperandIdx(Register Reg
, bool isKill
= false,
1217 const TargetRegisterInfo
*TRI
= nullptr) const;
1219 /// Wrapper for findRegisterUseOperandIdx, it returns
1220 /// a pointer to the MachineOperand rather than an index.
1221 MachineOperand
*findRegisterUseOperand(Register Reg
, bool isKill
= false,
1222 const TargetRegisterInfo
*TRI
= nullptr) {
1223 int Idx
= findRegisterUseOperandIdx(Reg
, isKill
, TRI
);
1224 return (Idx
== -1) ? nullptr : &getOperand(Idx
);
1227 const MachineOperand
*findRegisterUseOperand(
1228 Register Reg
, bool isKill
= false,
1229 const TargetRegisterInfo
*TRI
= nullptr) const {
1230 return const_cast<MachineInstr
*>(this)->
1231 findRegisterUseOperand(Reg
, isKill
, TRI
);
1234 /// Returns the operand index that is a def of the specified register or
1235 /// -1 if it is not found. If isDead is true, defs that are not dead are
1236 /// skipped. If Overlap is true, then it also looks for defs that merely
1237 /// overlap the specified register. If TargetRegisterInfo is non-null,
1238 /// then it also checks if there is a def of a super-register.
1239 /// This may also return a register mask operand when Overlap is true.
1240 int findRegisterDefOperandIdx(Register Reg
,
1241 bool isDead
= false, bool Overlap
= false,
1242 const TargetRegisterInfo
*TRI
= nullptr) const;
1244 /// Wrapper for findRegisterDefOperandIdx, it returns
1245 /// a pointer to the MachineOperand rather than an index.
1247 findRegisterDefOperand(Register Reg
, bool isDead
= false,
1248 bool Overlap
= false,
1249 const TargetRegisterInfo
*TRI
= nullptr) {
1250 int Idx
= findRegisterDefOperandIdx(Reg
, isDead
, Overlap
, TRI
);
1251 return (Idx
== -1) ? nullptr : &getOperand(Idx
);
1254 const MachineOperand
*
1255 findRegisterDefOperand(Register Reg
, bool isDead
= false,
1256 bool Overlap
= false,
1257 const TargetRegisterInfo
*TRI
= nullptr) const {
1258 return const_cast<MachineInstr
*>(this)->findRegisterDefOperand(
1259 Reg
, isDead
, Overlap
, TRI
);
1262 /// Find the index of the first operand in the
1263 /// operand list that is used to represent the predicate. It returns -1 if
1265 int findFirstPredOperandIdx() const;
1267 /// Find the index of the flag word operand that
1268 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
1269 /// getOperand(OpIdx) does not belong to an inline asm operand group.
1271 /// If GroupNo is not NULL, it will receive the number of the operand group
1272 /// containing OpIdx.
1274 /// The flag operand is an immediate that can be decoded with methods like
1275 /// InlineAsm::hasRegClassConstraint().
1276 int findInlineAsmFlagIdx(unsigned OpIdx
, unsigned *GroupNo
= nullptr) const;
1278 /// Compute the static register class constraint for operand OpIdx.
1279 /// For normal instructions, this is derived from the MCInstrDesc.
1280 /// For inline assembly it is derived from the flag words.
1282 /// Returns NULL if the static register class constraint cannot be
1284 const TargetRegisterClass
*
1285 getRegClassConstraint(unsigned OpIdx
,
1286 const TargetInstrInfo
*TII
,
1287 const TargetRegisterInfo
*TRI
) const;
1289 /// Applies the constraints (def/use) implied by this MI on \p Reg to
1290 /// the given \p CurRC.
1291 /// If \p ExploreBundle is set and MI is part of a bundle, all the
1292 /// instructions inside the bundle will be taken into account. In other words,
1293 /// this method accumulates all the constraints of the operand of this MI and
1294 /// the related bundle if MI is a bundle or inside a bundle.
1296 /// Returns the register class that satisfies both \p CurRC and the
1297 /// constraints set by MI. Returns NULL if such a register class does not
1300 /// \pre CurRC must not be NULL.
1301 const TargetRegisterClass
*getRegClassConstraintEffectForVReg(
1302 Register Reg
, const TargetRegisterClass
*CurRC
,
1303 const TargetInstrInfo
*TII
, const TargetRegisterInfo
*TRI
,
1304 bool ExploreBundle
= false) const;
1306 /// Applies the constraints (def/use) implied by the \p OpIdx operand
1307 /// to the given \p CurRC.
1309 /// Returns the register class that satisfies both \p CurRC and the
1310 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
1313 /// \pre CurRC must not be NULL.
1314 /// \pre The operand at \p OpIdx must be a register.
1315 const TargetRegisterClass
*
1316 getRegClassConstraintEffect(unsigned OpIdx
, const TargetRegisterClass
*CurRC
,
1317 const TargetInstrInfo
*TII
,
1318 const TargetRegisterInfo
*TRI
) const;
1320 /// Add a tie between the register operands at DefIdx and UseIdx.
1321 /// The tie will cause the register allocator to ensure that the two
1322 /// operands are assigned the same physical register.
1324 /// Tied operands are managed automatically for explicit operands in the
1325 /// MCInstrDesc. This method is for exceptional cases like inline asm.
1326 void tieOperands(unsigned DefIdx
, unsigned UseIdx
);
1328 /// Given the index of a tied register operand, find the
1329 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1330 /// index of the tied operand which must exist.
1331 unsigned findTiedOperandIdx(unsigned OpIdx
) const;
1333 /// Given the index of a register def operand,
1334 /// check if the register def is tied to a source operand, due to either
1335 /// two-address elimination or inline assembly constraints. Returns the
1336 /// first tied use operand index by reference if UseOpIdx is not null.
1337 bool isRegTiedToUseOperand(unsigned DefOpIdx
,
1338 unsigned *UseOpIdx
= nullptr) const {
1339 const MachineOperand
&MO
= getOperand(DefOpIdx
);
1340 if (!MO
.isReg() || !MO
.isDef() || !MO
.isTied())
1343 *UseOpIdx
= findTiedOperandIdx(DefOpIdx
);
1347 /// Return true if the use operand of the specified index is tied to a def
1348 /// operand. It also returns the def operand index by reference if DefOpIdx
1350 bool isRegTiedToDefOperand(unsigned UseOpIdx
,
1351 unsigned *DefOpIdx
= nullptr) const {
1352 const MachineOperand
&MO
= getOperand(UseOpIdx
);
1353 if (!MO
.isReg() || !MO
.isUse() || !MO
.isTied())
1356 *DefOpIdx
= findTiedOperandIdx(UseOpIdx
);
1360 /// Clears kill flags on all operands.
1361 void clearKillInfo();
1363 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1364 /// properly composing subreg indices where necessary.
1365 void substituteRegister(Register FromReg
, Register ToReg
, unsigned SubIdx
,
1366 const TargetRegisterInfo
&RegInfo
);
1368 /// We have determined MI kills a register. Look for the
1369 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1370 /// add a implicit operand if it's not found. Returns true if the operand
1371 /// exists / is added.
1372 bool addRegisterKilled(Register IncomingReg
,
1373 const TargetRegisterInfo
*RegInfo
,
1374 bool AddIfNotFound
= false);
1376 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes
1377 /// all aliasing registers.
1378 void clearRegisterKills(Register Reg
, const TargetRegisterInfo
*RegInfo
);
1380 /// We have determined MI defined a register without a use.
1381 /// Look for the operand that defines it and mark it as IsDead. If
1382 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1383 /// true if the operand exists / is added.
1384 bool addRegisterDead(Register Reg
, const TargetRegisterInfo
*RegInfo
,
1385 bool AddIfNotFound
= false);
1387 /// Clear all dead flags on operands defining register @p Reg.
1388 void clearRegisterDeads(Register Reg
);
1390 /// Mark all subregister defs of register @p Reg with the undef flag.
1391 /// This function is used when we determined to have a subregister def in an
1392 /// otherwise undefined super register.
1393 void setRegisterDefReadUndef(Register Reg
, bool IsUndef
= true);
1395 /// We have determined MI defines a register. Make sure there is an operand
1397 void addRegisterDefined(Register Reg
,
1398 const TargetRegisterInfo
*RegInfo
= nullptr);
1400 /// Mark every physreg used by this instruction as
1401 /// dead except those in the UsedRegs list.
1403 /// On instructions with register mask operands, also add implicit-def
1404 /// operands for all registers in UsedRegs.
1405 void setPhysRegsDeadExcept(ArrayRef
<Register
> UsedRegs
,
1406 const TargetRegisterInfo
&TRI
);
1408 /// Return true if it is safe to move this instruction. If
1409 /// SawStore is set to true, it means that there is a store (or call) between
1410 /// the instruction's location and its intended destination.
1411 bool isSafeToMove(AliasAnalysis
*AA
, bool &SawStore
) const;
1413 /// Returns true if this instruction's memory access aliases the memory
1414 /// access of Other.
1416 /// Assumes any physical registers used to compute addresses
1417 /// have the same value for both instructions. Returns false if neither
1418 /// instruction writes to memory.
1420 /// @param AA Optional alias analysis, used to compare memory operands.
1421 /// @param Other MachineInstr to check aliasing against.
1422 /// @param UseTBAA Whether to pass TBAA information to alias analysis.
1423 bool mayAlias(AliasAnalysis
*AA
, const MachineInstr
&Other
, bool UseTBAA
) const;
1425 /// Return true if this instruction may have an ordered
1426 /// or volatile memory reference, or if the information describing the memory
1427 /// reference is not available. Return false if it is known to have no
1428 /// ordered or volatile memory references.
1429 bool hasOrderedMemoryRef() const;
1431 /// Return true if this load instruction never traps and points to a memory
1432 /// location whose value doesn't change during the execution of this function.
1434 /// Examples include loading a value from the constant pool or from the
1435 /// argument area of a function (if it does not change). If the instruction
1436 /// does multiple loads, this returns true only if all of the loads are
1437 /// dereferenceable and invariant.
1438 bool isDereferenceableInvariantLoad(AliasAnalysis
*AA
) const;
1440 /// If the specified instruction is a PHI that always merges together the
1441 /// same virtual register, return the register, otherwise return 0.
1442 unsigned isConstantValuePHI() const;
1444 /// Return true if this instruction has side effects that are not modeled
1445 /// by mayLoad / mayStore, etc.
1446 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1447 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1448 /// INLINEASM instruction, in which case the side effect property is encoded
1449 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1451 bool hasUnmodeledSideEffects() const;
1453 /// Returns true if it is illegal to fold a load across this instruction.
1454 bool isLoadFoldBarrier() const;
1456 /// Return true if all the defs of this instruction are dead.
1457 bool allDefsAreDead() const;
1459 /// Return a valid size if the instruction is a spill instruction.
1460 Optional
<unsigned> getSpillSize(const TargetInstrInfo
*TII
) const;
1462 /// Return a valid size if the instruction is a folded spill instruction.
1463 Optional
<unsigned> getFoldedSpillSize(const TargetInstrInfo
*TII
) const;
1465 /// Return a valid size if the instruction is a restore instruction.
1466 Optional
<unsigned> getRestoreSize(const TargetInstrInfo
*TII
) const;
1468 /// Return a valid size if the instruction is a folded restore instruction.
1470 getFoldedRestoreSize(const TargetInstrInfo
*TII
) const;
1472 /// Copy implicit register operands from specified
1473 /// instruction to this instruction.
1474 void copyImplicitOps(MachineFunction
&MF
, const MachineInstr
&MI
);
1476 /// Debugging support
1478 /// Determine the generic type to be printed (if needed) on uses and defs.
1479 LLT
getTypeToPrint(unsigned OpIdx
, SmallBitVector
&PrintedTypes
,
1480 const MachineRegisterInfo
&MRI
) const;
1482 /// Return true when an instruction has tied register that can't be determined
1483 /// by the instruction's descriptor. This is useful for MIR printing, to
1484 /// determine whether we need to print the ties or not.
1485 bool hasComplexRegisterTies() const;
1487 /// Print this MI to \p OS.
1488 /// Don't print information that can be inferred from other instructions if
1489 /// \p IsStandalone is false. It is usually true when only a fragment of the
1490 /// function is printed.
1491 /// Only print the defs and the opcode if \p SkipOpers is true.
1492 /// Otherwise, also print operands if \p SkipDebugLoc is true.
1493 /// Otherwise, also print the debug loc, with a terminating newline.
1494 /// \p TII is used to print the opcode name. If it's not present, but the
1495 /// MI is in a function, the opcode will be printed using the function's TII.
1496 void print(raw_ostream
&OS
, bool IsStandalone
= true, bool SkipOpers
= false,
1497 bool SkipDebugLoc
= false, bool AddNewLine
= true,
1498 const TargetInstrInfo
*TII
= nullptr) const;
1499 void print(raw_ostream
&OS
, ModuleSlotTracker
&MST
, bool IsStandalone
= true,
1500 bool SkipOpers
= false, bool SkipDebugLoc
= false,
1501 bool AddNewLine
= true,
1502 const TargetInstrInfo
*TII
= nullptr) const;
1506 //===--------------------------------------------------------------------===//
1507 // Accessors used to build up machine instructions.
1509 /// Add the specified operand to the instruction. If it is an implicit
1510 /// operand, it is added to the end of the operand list. If it is an
1511 /// explicit operand it is added at the end of the explicit operand list
1512 /// (before the first implicit operand).
1514 /// MF must be the machine function that was used to allocate this
1517 /// MachineInstrBuilder provides a more convenient interface for creating
1518 /// instructions and adding operands.
1519 void addOperand(MachineFunction
&MF
, const MachineOperand
&Op
);
1521 /// Add an operand without providing an MF reference. This only works for
1522 /// instructions that are inserted in a basic block.
1524 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1526 void addOperand(const MachineOperand
&Op
);
1528 /// Replace the instruction descriptor (thus opcode) of
1529 /// the current instruction with a new one.
1530 void setDesc(const MCInstrDesc
&tid
) { MCID
= &tid
; }
1532 /// Replace current source information with new such.
1533 /// Avoid using this, the constructor argument is preferable.
1534 void setDebugLoc(DebugLoc dl
) {
1535 debugLoc
= std::move(dl
);
1536 assert(debugLoc
.hasTrivialDestructor() && "Expected trivial destructor");
1539 /// Erase an operand from an instruction, leaving it with one
1540 /// fewer operand than it started with.
1541 void RemoveOperand(unsigned OpNo
);
1543 /// Clear this MachineInstr's memory reference descriptor list. This resets
1544 /// the memrefs to their most conservative state. This should be used only
1545 /// as a last resort since it greatly pessimizes our knowledge of the memory
1546 /// access performed by the instruction.
1547 void dropMemRefs(MachineFunction
&MF
);
1549 /// Assign this MachineInstr's memory reference descriptor list.
1551 /// Unlike other methods, this *will* allocate them into a new array
1552 /// associated with the provided `MachineFunction`.
1553 void setMemRefs(MachineFunction
&MF
, ArrayRef
<MachineMemOperand
*> MemRefs
);
1555 /// Add a MachineMemOperand to the machine instruction.
1556 /// This function should be used only occasionally. The setMemRefs function
1557 /// is the primary method for setting up a MachineInstr's MemRefs list.
1558 void addMemOperand(MachineFunction
&MF
, MachineMemOperand
*MO
);
1560 /// Clone another MachineInstr's memory reference descriptor list and replace
1563 /// Note that `*this` may be the incoming MI!
1565 /// Prefer this API whenever possible as it can avoid allocations in common
1567 void cloneMemRefs(MachineFunction
&MF
, const MachineInstr
&MI
);
1569 /// Clone the merge of multiple MachineInstrs' memory reference descriptors
1570 /// list and replace ours with it.
1572 /// Note that `*this` may be one of the incoming MIs!
1574 /// Prefer this API whenever possible as it can avoid allocations in common
1576 void cloneMergedMemRefs(MachineFunction
&MF
,
1577 ArrayRef
<const MachineInstr
*> MIs
);
1579 /// Set a symbol that will be emitted just prior to the instruction itself.
1581 /// Setting this to a null pointer will remove any such symbol.
1583 /// FIXME: This is not fully implemented yet.
1584 void setPreInstrSymbol(MachineFunction
&MF
, MCSymbol
*Symbol
);
1586 /// Set a symbol that will be emitted just after the instruction itself.
1588 /// Setting this to a null pointer will remove any such symbol.
1590 /// FIXME: This is not fully implemented yet.
1591 void setPostInstrSymbol(MachineFunction
&MF
, MCSymbol
*Symbol
);
1593 /// Clone another MachineInstr's pre- and post- instruction symbols and
1594 /// replace ours with it.
1595 void cloneInstrSymbols(MachineFunction
&MF
, const MachineInstr
&MI
);
1597 /// Return the MIFlags which represent both MachineInstrs. This
1598 /// should be used when merging two MachineInstrs into one. This routine does
1599 /// not modify the MIFlags of this MachineInstr.
1600 uint16_t mergeFlagsWith(const MachineInstr
& Other
) const;
1602 static uint16_t copyFlagsFromInstruction(const Instruction
&I
);
1604 /// Copy all flags to MachineInst MIFlags
1605 void copyIRFlags(const Instruction
&I
);
1607 /// Break any tie involving OpIdx.
1608 void untieRegOperand(unsigned OpIdx
) {
1609 MachineOperand
&MO
= getOperand(OpIdx
);
1610 if (MO
.isReg() && MO
.isTied()) {
1611 getOperand(findTiedOperandIdx(OpIdx
)).TiedTo
= 0;
1616 /// Add all implicit def and use operands to this instruction.
1617 void addImplicitDefUseOperands(MachineFunction
&MF
);
1619 /// Scan instructions following MI and collect any matching DBG_VALUEs.
1620 void collectDebugValues(SmallVectorImpl
<MachineInstr
*> &DbgValues
);
1622 /// Find all DBG_VALUEs that point to the register def in this instruction
1623 /// and point them to \p Reg instead.
1624 void changeDebugValuesDefReg(Register Reg
);
1626 /// Returns the Intrinsic::ID for this instruction.
1627 /// \pre Must have an intrinsic ID operand.
1628 unsigned getIntrinsicID() const {
1629 return getOperand(getNumExplicitDefs()).getIntrinsicID();
1633 /// If this instruction is embedded into a MachineFunction, return the
1634 /// MachineRegisterInfo object for the current function, otherwise
1636 MachineRegisterInfo
*getRegInfo();
1638 /// Unlink all of the register operands in this instruction from their
1639 /// respective use lists. This requires that the operands already be on their
1641 void RemoveRegOperandsFromUseLists(MachineRegisterInfo
&);
1643 /// Add all of the register operands in this instruction from their
1644 /// respective use lists. This requires that the operands not be on their
1646 void AddRegOperandsToUseLists(MachineRegisterInfo
&);
1648 /// Slow path for hasProperty when we're dealing with a bundle.
1649 bool hasPropertyInBundle(uint64_t Mask
, QueryType Type
) const;
1651 /// Implements the logic of getRegClassConstraintEffectForVReg for the
1652 /// this MI and the given operand index \p OpIdx.
1653 /// If the related operand does not constrained Reg, this returns CurRC.
1654 const TargetRegisterClass
*getRegClassConstraintEffectForVRegImpl(
1655 unsigned OpIdx
, Register Reg
, const TargetRegisterClass
*CurRC
,
1656 const TargetInstrInfo
*TII
, const TargetRegisterInfo
*TRI
) const;
1659 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1660 /// instruction rather than by pointer value.
1661 /// The hashing and equality testing functions ignore definitions so this is
1662 /// useful for CSE, etc.
1663 struct MachineInstrExpressionTrait
: DenseMapInfo
<MachineInstr
*> {
1664 static inline MachineInstr
*getEmptyKey() {
1668 static inline MachineInstr
*getTombstoneKey() {
1669 return reinterpret_cast<MachineInstr
*>(-1);
1672 static unsigned getHashValue(const MachineInstr
* const &MI
);
1674 static bool isEqual(const MachineInstr
* const &LHS
,
1675 const MachineInstr
* const &RHS
) {
1676 if (RHS
== getEmptyKey() || RHS
== getTombstoneKey() ||
1677 LHS
== getEmptyKey() || LHS
== getTombstoneKey())
1679 return LHS
->isIdenticalTo(*RHS
, MachineInstr::IgnoreVRegDefs
);
1683 //===----------------------------------------------------------------------===//
1684 // Debugging Support
1686 inline raw_ostream
& operator<<(raw_ostream
&OS
, const MachineInstr
&MI
) {
1691 } // end namespace llvm
1693 #endif // LLVM_CODEGEN_MACHINEINSTR_H