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[llvm-core.git] / include / llvm / CodeGen / RegisterScavenging.h
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1 //===- RegisterScavenging.h - Machine register scavenging -------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file
10 /// This file declares the machine register scavenger class. It can provide
11 /// information such as unused register at any point in a machine basic block.
12 /// It also provides a mechanism to make registers available by evicting them
13 /// to spill slots.
15 //===----------------------------------------------------------------------===//
17 #ifndef LLVM_CODEGEN_REGISTERSCAVENGING_H
18 #define LLVM_CODEGEN_REGISTERSCAVENGING_H
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/LiveRegUnits.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/MC/LaneBitmask.h"
27 namespace llvm {
29 class MachineInstr;
30 class TargetInstrInfo;
31 class TargetRegisterClass;
32 class TargetRegisterInfo;
34 class RegScavenger {
35 const TargetRegisterInfo *TRI;
36 const TargetInstrInfo *TII;
37 MachineRegisterInfo* MRI;
38 MachineBasicBlock *MBB = nullptr;
39 MachineBasicBlock::iterator MBBI;
40 unsigned NumRegUnits = 0;
42 /// True if RegScavenger is currently tracking the liveness of registers.
43 bool Tracking = false;
45 /// Information on scavenged registers (held in a spill slot).
46 struct ScavengedInfo {
47 ScavengedInfo(int FI = -1) : FrameIndex(FI) {}
49 /// A spill slot used for scavenging a register post register allocation.
50 int FrameIndex;
52 /// If non-zero, the specific register is currently being
53 /// scavenged. That is, it is spilled to this scavenging stack slot.
54 Register Reg;
56 /// The instruction that restores the scavenged register from stack.
57 const MachineInstr *Restore = nullptr;
60 /// A vector of information on scavenged registers.
61 SmallVector<ScavengedInfo, 2> Scavenged;
63 LiveRegUnits LiveUnits;
65 // These BitVectors are only used internally to forward(). They are members
66 // to avoid frequent reallocations.
67 BitVector KillRegUnits, DefRegUnits;
68 BitVector TmpRegUnits;
70 public:
71 RegScavenger() = default;
73 /// Start tracking liveness from the begin of basic block \p MBB.
74 void enterBasicBlock(MachineBasicBlock &MBB);
76 /// Start tracking liveness from the end of basic block \p MBB.
77 /// Use backward() to move towards the beginning of the block. This is
78 /// preferred to enterBasicBlock() and forward() because it does not depend
79 /// on the presence of kill flags.
80 void enterBasicBlockEnd(MachineBasicBlock &MBB);
82 /// Move the internal MBB iterator and update register states.
83 void forward();
85 /// Move the internal MBB iterator and update register states until
86 /// it has processed the specific iterator.
87 void forward(MachineBasicBlock::iterator I) {
88 if (!Tracking && MBB->begin() != I) forward();
89 while (MBBI != I) forward();
92 /// Invert the behavior of forward() on the current instruction (undo the
93 /// changes to the available registers made by forward()).
94 void unprocess();
96 /// Unprocess instructions until you reach the provided iterator.
97 void unprocess(MachineBasicBlock::iterator I) {
98 while (MBBI != I) unprocess();
101 /// Update internal register state and move MBB iterator backwards.
102 /// Contrary to unprocess() this method gives precise results even in the
103 /// absence of kill flags.
104 void backward();
106 /// Call backward() as long as the internal iterator does not point to \p I.
107 void backward(MachineBasicBlock::iterator I) {
108 while (MBBI != I)
109 backward();
112 /// Move the internal MBB iterator but do not update register states.
113 void skipTo(MachineBasicBlock::iterator I) {
114 if (I == MachineBasicBlock::iterator(nullptr))
115 Tracking = false;
116 MBBI = I;
119 MachineBasicBlock::iterator getCurrentPosition() const { return MBBI; }
121 /// Return if a specific register is currently used.
122 bool isRegUsed(Register Reg, bool includeReserved = true) const;
124 /// Return all available registers in the register class in Mask.
125 BitVector getRegsAvailable(const TargetRegisterClass *RC);
127 /// Find an unused register of the specified register class.
128 /// Return 0 if none is found.
129 Register FindUnusedReg(const TargetRegisterClass *RC) const;
131 /// Add a scavenging frame index.
132 void addScavengingFrameIndex(int FI) {
133 Scavenged.push_back(ScavengedInfo(FI));
136 /// Query whether a frame index is a scavenging frame index.
137 bool isScavengingFrameIndex(int FI) const {
138 for (SmallVectorImpl<ScavengedInfo>::const_iterator I = Scavenged.begin(),
139 IE = Scavenged.end(); I != IE; ++I)
140 if (I->FrameIndex == FI)
141 return true;
143 return false;
146 /// Get an array of scavenging frame indices.
147 void getScavengingFrameIndices(SmallVectorImpl<int> &A) const {
148 for (SmallVectorImpl<ScavengedInfo>::const_iterator I = Scavenged.begin(),
149 IE = Scavenged.end(); I != IE; ++I)
150 if (I->FrameIndex >= 0)
151 A.push_back(I->FrameIndex);
154 /// Make a register of the specific register class
155 /// available and do the appropriate bookkeeping. SPAdj is the stack
156 /// adjustment due to call frame, it's passed along to eliminateFrameIndex().
157 /// Returns the scavenged register.
158 /// This is deprecated as it depends on the quality of the kill flags being
159 /// present; Use scavengeRegisterBackwards() instead!
161 /// If \p AllowSpill is false, fail if a spill is required to make the
162 /// register available, and return NoRegister.
163 Register scavengeRegister(const TargetRegisterClass *RC,
164 MachineBasicBlock::iterator I, int SPAdj,
165 bool AllowSpill = true);
166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
167 bool AllowSpill = true) {
168 return scavengeRegister(RegClass, MBBI, SPAdj, AllowSpill);
171 /// Make a register of the specific register class available from the current
172 /// position backwards to the place before \p To. If \p RestoreAfter is true
173 /// this includes the instruction following the current position.
174 /// SPAdj is the stack adjustment due to call frame, it's passed along to
175 /// eliminateFrameIndex().
176 /// Returns the scavenged register.
178 /// If \p AllowSpill is false, fail if a spill is required to make the
179 /// register available, and return NoRegister.
180 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
181 MachineBasicBlock::iterator To,
182 bool RestoreAfter, int SPAdj,
183 bool AllowSpill = true);
185 /// Tell the scavenger a register is used.
186 void setRegUsed(Register Reg, LaneBitmask LaneMask = LaneBitmask::getAll());
188 private:
189 /// Returns true if a register is reserved. It is never "unused".
190 bool isReserved(Register Reg) const { return MRI->isReserved(Reg); }
192 /// setUsed / setUnused - Mark the state of one or a number of register units.
194 void setUsed(const BitVector &RegUnits) {
195 LiveUnits.addUnits(RegUnits);
197 void setUnused(const BitVector &RegUnits) {
198 LiveUnits.removeUnits(RegUnits);
201 /// Processes the current instruction and fill the KillRegUnits and
202 /// DefRegUnits bit vectors.
203 void determineKillsAndDefs();
205 /// Add all Reg Units that Reg contains to BV.
206 void addRegUnits(BitVector &BV, Register Reg);
208 /// Remove all Reg Units that \p Reg contains from \p BV.
209 void removeRegUnits(BitVector &BV, Register Reg);
211 /// Return the candidate register that is unused for the longest after
212 /// StartMI. UseMI is set to the instruction where the search stopped.
214 /// No more than InstrLimit instructions are inspected.
215 Register findSurvivorReg(MachineBasicBlock::iterator StartMI,
216 BitVector &Candidates,
217 unsigned InstrLimit,
218 MachineBasicBlock::iterator &UseMI);
220 /// Initialize RegisterScavenger.
221 void init(MachineBasicBlock &MBB);
223 /// Mark live-in registers of basic block as used.
224 void setLiveInsUsed(const MachineBasicBlock &MBB);
226 /// Spill a register after position \p After and reload it before position
227 /// \p UseMI.
228 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
229 MachineBasicBlock::iterator Before,
230 MachineBasicBlock::iterator &UseMI);
233 /// Replaces all frame index virtual registers with physical registers. Uses the
234 /// register scavenger to find an appropriate register to use.
235 void scavengeFrameVirtualRegs(MachineFunction &MF, RegScavenger &RS);
237 } // end namespace llvm
239 #endif // LLVM_CODEGEN_REGISTERSCAVENGING_H