[Alignment][NFC] Migrate Instructions to Align
[llvm-core.git] / include / llvm / CodeGen / SelectionDAGISel.h
bloba2011cc4b3959e53dcafd75e6ffa562d2735eb02
1 //===-- llvm/CodeGen/SelectionDAGISel.h - Common Base Class------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the SelectionDAGISel class, which is used as the common
10 // base class for SelectionDAG-based instruction selectors.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
15 #define LLVM_CODEGEN_SELECTIONDAGISEL_H
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/CodeGen/TargetSubtargetInfo.h"
20 #include "llvm/IR/BasicBlock.h"
21 #include "llvm/Pass.h"
22 #include <memory>
24 namespace llvm {
25 class FastISel;
26 class SelectionDAGBuilder;
27 class SDValue;
28 class MachineRegisterInfo;
29 class MachineBasicBlock;
30 class MachineFunction;
31 class MachineInstr;
32 class OptimizationRemarkEmitter;
33 class TargetLowering;
34 class TargetLibraryInfo;
35 class FunctionLoweringInfo;
36 class ScheduleHazardRecognizer;
37 class SwiftErrorValueTracking;
38 class GCFunctionInfo;
39 class ScheduleDAGSDNodes;
40 class LoadInst;
42 /// SelectionDAGISel - This is the common base class used for SelectionDAG-based
43 /// pattern-matching instruction selectors.
44 class SelectionDAGISel : public MachineFunctionPass {
45 public:
46 TargetMachine &TM;
47 const TargetLibraryInfo *LibInfo;
48 FunctionLoweringInfo *FuncInfo;
49 SwiftErrorValueTracking *SwiftError;
50 MachineFunction *MF;
51 MachineRegisterInfo *RegInfo;
52 SelectionDAG *CurDAG;
53 SelectionDAGBuilder *SDB;
54 AliasAnalysis *AA;
55 GCFunctionInfo *GFI;
56 CodeGenOpt::Level OptLevel;
57 const TargetInstrInfo *TII;
58 const TargetLowering *TLI;
59 bool FastISelFailed;
60 SmallPtrSet<const Instruction *, 4> ElidedArgCopyInstrs;
62 /// Current optimization remark emitter.
63 /// Used to report things like combines and FastISel failures.
64 std::unique_ptr<OptimizationRemarkEmitter> ORE;
66 static char ID;
68 explicit SelectionDAGISel(TargetMachine &tm,
69 CodeGenOpt::Level OL = CodeGenOpt::Default);
70 ~SelectionDAGISel() override;
72 const TargetLowering *getTargetLowering() const { return TLI; }
74 void getAnalysisUsage(AnalysisUsage &AU) const override;
76 bool runOnMachineFunction(MachineFunction &MF) override;
78 virtual void EmitFunctionEntryCode() {}
80 /// PreprocessISelDAG - This hook allows targets to hack on the graph before
81 /// instruction selection starts.
82 virtual void PreprocessISelDAG() {}
84 /// PostprocessISelDAG() - This hook allows the target to hack on the graph
85 /// right after selection.
86 virtual void PostprocessISelDAG() {}
88 /// Main hook for targets to transform nodes into machine nodes.
89 virtual void Select(SDNode *N) = 0;
91 /// SelectInlineAsmMemoryOperand - Select the specified address as a target
92 /// addressing mode, according to the specified constraint. If this does
93 /// not match or is not implemented, return true. The resultant operands
94 /// (which will appear in the machine instruction) should be added to the
95 /// OutOps vector.
96 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
97 unsigned ConstraintID,
98 std::vector<SDValue> &OutOps) {
99 return true;
102 /// IsProfitableToFold - Returns true if it's profitable to fold the specific
103 /// operand node N of U during instruction selection that starts at Root.
104 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
106 /// IsLegalToFold - Returns true if the specific operand node N of
107 /// U can be folded during instruction selection that starts at Root.
108 /// FIXME: This is a static member function because the MSP430/X86
109 /// targets, which uses it during isel. This could become a proper member.
110 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
111 CodeGenOpt::Level OptLevel,
112 bool IgnoreChains = false);
114 static void InvalidateNodeId(SDNode *N);
115 static int getUninvalidatedNodeId(SDNode *N);
117 static void EnforceNodeIdInvariant(SDNode *N);
119 // Opcodes used by the DAG state machine:
120 enum BuiltinOpcodes {
121 OPC_Scope,
122 OPC_RecordNode,
123 OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
124 OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
125 OPC_RecordMemRef,
126 OPC_CaptureGlueInput,
127 OPC_MoveChild,
128 OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3,
129 OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7,
130 OPC_MoveParent,
131 OPC_CheckSame,
132 OPC_CheckChild0Same, OPC_CheckChild1Same,
133 OPC_CheckChild2Same, OPC_CheckChild3Same,
134 OPC_CheckPatternPredicate,
135 OPC_CheckPredicate,
136 OPC_CheckPredicateWithOperands,
137 OPC_CheckOpcode,
138 OPC_SwitchOpcode,
139 OPC_CheckType,
140 OPC_CheckTypeRes,
141 OPC_SwitchType,
142 OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
143 OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
144 OPC_CheckChild6Type, OPC_CheckChild7Type,
145 OPC_CheckInteger,
146 OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
147 OPC_CheckChild3Integer, OPC_CheckChild4Integer,
148 OPC_CheckCondCode, OPC_CheckChild2CondCode,
149 OPC_CheckValueType,
150 OPC_CheckComplexPat,
151 OPC_CheckAndImm, OPC_CheckOrImm,
152 OPC_CheckImmAllOnesV,
153 OPC_CheckImmAllZerosV,
154 OPC_CheckFoldableChainNode,
156 OPC_EmitInteger,
157 OPC_EmitRegister,
158 OPC_EmitRegister2,
159 OPC_EmitConvertToTarget,
160 OPC_EmitMergeInputChains,
161 OPC_EmitMergeInputChains1_0,
162 OPC_EmitMergeInputChains1_1,
163 OPC_EmitMergeInputChains1_2,
164 OPC_EmitCopyToReg,
165 OPC_EmitCopyToReg2,
166 OPC_EmitNodeXForm,
167 OPC_EmitNode,
168 // Space-optimized forms that implicitly encode number of result VTs.
169 OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2,
170 OPC_MorphNodeTo,
171 // Space-optimized forms that implicitly encode number of result VTs.
172 OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2,
173 OPC_CompleteMatch,
174 // Contains offset in table for pattern being selected
175 OPC_Coverage
178 enum {
179 OPFL_None = 0, // Node has no chain or glue input and isn't variadic.
180 OPFL_Chain = 1, // Node has a chain input.
181 OPFL_GlueInput = 2, // Node has a glue input.
182 OPFL_GlueOutput = 4, // Node has a glue output.
183 OPFL_MemRefs = 8, // Node gets accumulated MemRefs.
184 OPFL_Variadic0 = 1<<4, // Node is variadic, root has 0 fixed inputs.
185 OPFL_Variadic1 = 2<<4, // Node is variadic, root has 1 fixed inputs.
186 OPFL_Variadic2 = 3<<4, // Node is variadic, root has 2 fixed inputs.
187 OPFL_Variadic3 = 4<<4, // Node is variadic, root has 3 fixed inputs.
188 OPFL_Variadic4 = 5<<4, // Node is variadic, root has 4 fixed inputs.
189 OPFL_Variadic5 = 6<<4, // Node is variadic, root has 5 fixed inputs.
190 OPFL_Variadic6 = 7<<4, // Node is variadic, root has 6 fixed inputs.
192 OPFL_VariadicInfo = OPFL_Variadic6
195 /// getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the
196 /// number of fixed arity values that should be skipped when copying from the
197 /// root.
198 static inline int getNumFixedFromVariadicInfo(unsigned Flags) {
199 return ((Flags&OPFL_VariadicInfo) >> 4)-1;
203 protected:
204 /// DAGSize - Size of DAG being instruction selected.
206 unsigned DAGSize;
208 /// ReplaceUses - replace all uses of the old node F with the use
209 /// of the new node T.
210 void ReplaceUses(SDValue F, SDValue T) {
211 CurDAG->ReplaceAllUsesOfValueWith(F, T);
212 EnforceNodeIdInvariant(T.getNode());
215 /// ReplaceUses - replace all uses of the old nodes F with the use
216 /// of the new nodes T.
217 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
218 CurDAG->ReplaceAllUsesOfValuesWith(F, T, Num);
219 for (unsigned i = 0; i < Num; ++i)
220 EnforceNodeIdInvariant(T[i].getNode());
223 /// ReplaceUses - replace all uses of the old node F with the use
224 /// of the new node T.
225 void ReplaceUses(SDNode *F, SDNode *T) {
226 CurDAG->ReplaceAllUsesWith(F, T);
227 EnforceNodeIdInvariant(T);
230 /// Replace all uses of \c F with \c T, then remove \c F from the DAG.
231 void ReplaceNode(SDNode *F, SDNode *T) {
232 CurDAG->ReplaceAllUsesWith(F, T);
233 EnforceNodeIdInvariant(T);
234 CurDAG->RemoveDeadNode(F);
237 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
238 /// by tblgen. Others should not call it.
239 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
240 const SDLoc &DL);
242 /// getPatternForIndex - Patterns selected by tablegen during ISEL
243 virtual StringRef getPatternForIndex(unsigned index) {
244 llvm_unreachable("Tblgen should generate the implementation of this!");
247 /// getIncludePathForIndex - get the td source location of pattern instantiation
248 virtual StringRef getIncludePathForIndex(unsigned index) {
249 llvm_unreachable("Tblgen should generate the implementation of this!");
251 public:
252 // Calls to these predicates are generated by tblgen.
253 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
254 int64_t DesiredMaskS) const;
255 bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
256 int64_t DesiredMaskS) const;
259 /// CheckPatternPredicate - This function is generated by tblgen in the
260 /// target. It runs the specified pattern predicate and returns true if it
261 /// succeeds or false if it fails. The number is a private implementation
262 /// detail to the code tblgen produces.
263 virtual bool CheckPatternPredicate(unsigned PredNo) const {
264 llvm_unreachable("Tblgen should generate the implementation of this!");
267 /// CheckNodePredicate - This function is generated by tblgen in the target.
268 /// It runs node predicate number PredNo and returns true if it succeeds or
269 /// false if it fails. The number is a private implementation
270 /// detail to the code tblgen produces.
271 virtual bool CheckNodePredicate(SDNode *N, unsigned PredNo) const {
272 llvm_unreachable("Tblgen should generate the implementation of this!");
275 /// CheckNodePredicateWithOperands - This function is generated by tblgen in
276 /// the target.
277 /// It runs node predicate number PredNo and returns true if it succeeds or
278 /// false if it fails. The number is a private implementation detail to the
279 /// code tblgen produces.
280 virtual bool CheckNodePredicateWithOperands(
281 SDNode *N, unsigned PredNo,
282 const SmallVectorImpl<SDValue> &Operands) const {
283 llvm_unreachable("Tblgen should generate the implementation of this!");
286 virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,
287 unsigned PatternNo,
288 SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {
289 llvm_unreachable("Tblgen should generate the implementation of this!");
292 virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {
293 llvm_unreachable("Tblgen should generate this!");
296 void SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
297 unsigned TableSize);
299 /// Return true if complex patterns for this target can mutate the
300 /// DAG.
301 virtual bool ComplexPatternFuncMutatesDAG() const {
302 return false;
305 bool isOrEquivalentToAdd(const SDNode *N) const;
307 private:
309 // Calls to these functions are generated by tblgen.
310 void Select_INLINEASM(SDNode *N, bool Branch);
311 void Select_READ_REGISTER(SDNode *Op);
312 void Select_WRITE_REGISTER(SDNode *Op);
313 void Select_UNDEF(SDNode *N);
314 void CannotYetSelect(SDNode *N);
316 private:
317 void DoInstructionSelection();
318 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
319 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo);
321 SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
323 /// Prepares the landing pad to take incoming values or do other EH
324 /// personality specific tasks. Returns true if the block should be
325 /// instruction selected, false if no code should be emitted for it.
326 bool PrepareEHLandingPad();
328 /// Perform instruction selection on all basic blocks in the function.
329 void SelectAllBasicBlocks(const Function &Fn);
331 /// Perform instruction selection on a single basic block, for
332 /// instructions between \p Begin and \p End. \p HadTailCall will be set
333 /// to true if a call in the block was translated as a tail call.
334 void SelectBasicBlock(BasicBlock::const_iterator Begin,
335 BasicBlock::const_iterator End,
336 bool &HadTailCall);
337 void FinishBasicBlock();
339 void CodeGenAndEmitDAG();
341 /// Generate instructions for lowering the incoming arguments of the
342 /// given function.
343 void LowerArguments(const Function &F);
345 void ComputeLiveOutVRegInfo();
347 /// Create the scheduler. If a specific scheduler was specified
348 /// via the SchedulerRegistry, use it, otherwise select the
349 /// one preferred by the target.
351 ScheduleDAGSDNodes *CreateScheduler();
353 /// OpcodeOffset - This is a cache used to dispatch efficiently into isel
354 /// state machines that start with a OPC_SwitchOpcode node.
355 std::vector<unsigned> OpcodeOffset;
357 void UpdateChains(SDNode *NodeToMatch, SDValue InputChain,
358 SmallVectorImpl<SDNode *> &ChainNodesMatched,
359 bool isMorphNodeTo);
364 #endif /* LLVM_CODEGEN_SELECTIONDAGISEL_H */