1 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This file describes how to lower LLVM code to machine code. This has two
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
17 /// In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
31 #include "llvm/Analysis/LegacyDivergenceAnalysis.h"
32 #include "llvm/CodeGen/DAGCombine.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/RuntimeLibcalls.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGNodes.h"
37 #include "llvm/CodeGen/TargetCallingConv.h"
38 #include "llvm/CodeGen/ValueTypes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/CallSite.h"
41 #include "llvm/IR/CallingConv.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instruction.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/MC/MCRegisterInfo.h"
51 #include "llvm/Support/Alignment.h"
52 #include "llvm/Support/AtomicOrdering.h"
53 #include "llvm/Support/Casting.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/MachineValueType.h"
56 #include "llvm/Target/TargetMachine.h"
69 class BranchProbability
;
74 class FunctionLoweringInfo
;
79 class MachineBasicBlock
;
80 class MachineFunction
;
82 class MachineJumpTableInfo
;
84 class MachineRegisterInfo
;
88 class TargetRegisterClass
;
89 class TargetLibraryInfo
;
90 class TargetRegisterInfo
;
96 None
, // No preference
97 Source
, // Follow source order.
98 RegPressure
, // Scheduling for lowest register pressure.
99 Hybrid
, // Scheduling for both latency and register pressure.
100 ILP
, // Scheduling for ILP in low register pressure mode.
101 VLIW
// Scheduling for VLIW targets.
104 } // end namespace Sched
106 /// This base class for TargetLowering contains the SelectionDAG-independent
107 /// parts that can be used from the rest of CodeGen.
108 class TargetLoweringBase
{
110 /// This enum indicates whether operations are valid for a target, and if not,
111 /// what action should be used to make them valid.
112 enum LegalizeAction
: uint8_t {
113 Legal
, // The target natively supports this operation.
114 Promote
, // This operation should be executed in a larger type.
115 Expand
, // Try to expand this to other ops, otherwise use a libcall.
116 LibCall
, // Don't try to expand this to other ops, always use a libcall.
117 Custom
// Use the LowerOperation hook to implement custom lowering.
120 /// This enum indicates whether a types are legal for a target, and if not,
121 /// what action should be used to make them valid.
122 enum LegalizeTypeAction
: uint8_t {
123 TypeLegal
, // The target natively supports this type.
124 TypePromoteInteger
, // Replace this integer with a larger one.
125 TypeExpandInteger
, // Split this integer into two of half the size.
126 TypeSoftenFloat
, // Convert this float to a same size integer type.
127 TypeExpandFloat
, // Split this float into two of half the size.
128 TypeScalarizeVector
, // Replace this one-element vector with its element.
129 TypeSplitVector
, // Split this vector into two of half the size.
130 TypeWidenVector
, // This vector should be widened into a larger vector.
131 TypePromoteFloat
// Replace this float with a larger one.
134 /// LegalizeKind holds the legalization kind that needs to happen to EVT
135 /// in order to type-legalize it.
136 using LegalizeKind
= std::pair
<LegalizeTypeAction
, EVT
>;
138 /// Enum that describes how the target represents true/false values.
139 enum BooleanContent
{
140 UndefinedBooleanContent
, // Only bit 0 counts, the rest can hold garbage.
141 ZeroOrOneBooleanContent
, // All bits zero except for bit 0.
142 ZeroOrNegativeOneBooleanContent
// All bits equal to bit 0.
145 /// Enum that describes what type of support for selects the target has.
146 enum SelectSupportKind
{
147 ScalarValSelect
, // The target supports scalar selects (ex: cmov).
148 ScalarCondVectorVal
, // The target supports selects with a scalar condition
149 // and vector values (ex: cmov).
150 VectorMaskSelect
// The target supports vector selects with a vector
151 // mask (ex: x86 blends).
154 /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
155 /// to, if at all. Exists because different targets have different levels of
156 /// support for these atomic instructions, and also have different options
157 /// w.r.t. what they should expand to.
158 enum class AtomicExpansionKind
{
159 None
, // Don't expand the instruction.
160 LLSC
, // Expand the instruction into loadlinked/storeconditional; used
162 LLOnly
, // Expand the (load) instruction into just a load-linked, which has
163 // greater atomic guarantees than a normal load.
164 CmpXChg
, // Expand the instruction into cmpxchg; used by at least X86.
165 MaskedIntrinsic
, // Use a target-specific intrinsic for the LL/SC loop.
168 /// Enum that specifies when a multiplication should be expanded.
169 enum class MulExpansionKind
{
170 Always
, // Always expand the instruction.
171 OnlyLegalOrCustom
, // Only expand when the resulting instructions are legal
177 Value
*Val
= nullptr;
178 SDValue Node
= SDValue();
188 bool IsSwiftSelf
: 1;
189 bool IsSwiftError
: 1;
190 uint16_t Alignment
= 0;
191 Type
*ByValType
= nullptr;
194 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
195 IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
196 IsSwiftSelf(false), IsSwiftError(false) {}
198 void setAttributes(const CallBase
*Call
, unsigned ArgIdx
);
200 void setAttributes(ImmutableCallSite
*CS
, unsigned ArgIdx
) {
201 return setAttributes(cast
<CallBase
>(CS
->getInstruction()), ArgIdx
);
204 using ArgListTy
= std::vector
<ArgListEntry
>;
206 virtual void markLibCallAttributes(MachineFunction
*MF
, unsigned CC
,
207 ArgListTy
&Args
) const {};
209 static ISD::NodeType
getExtendForContent(BooleanContent Content
) {
211 case UndefinedBooleanContent
:
212 // Extend by adding rubbish bits.
213 return ISD::ANY_EXTEND
;
214 case ZeroOrOneBooleanContent
:
215 // Extend by adding zero bits.
216 return ISD::ZERO_EXTEND
;
217 case ZeroOrNegativeOneBooleanContent
:
218 // Extend by copying the sign bit.
219 return ISD::SIGN_EXTEND
;
221 llvm_unreachable("Invalid content kind");
224 /// NOTE: The TargetMachine owns TLOF.
225 explicit TargetLoweringBase(const TargetMachine
&TM
);
226 TargetLoweringBase(const TargetLoweringBase
&) = delete;
227 TargetLoweringBase
&operator=(const TargetLoweringBase
&) = delete;
228 virtual ~TargetLoweringBase() = default;
231 /// Initialize all of the actions to default values.
235 const TargetMachine
&getTargetMachine() const { return TM
; }
237 virtual bool useSoftFloat() const { return false; }
239 /// Return the pointer type for the given address space, defaults to
240 /// the pointer type from the data layout.
241 /// FIXME: The default needs to be removed once all the code is updated.
242 virtual MVT
getPointerTy(const DataLayout
&DL
, uint32_t AS
= 0) const {
243 return MVT::getIntegerVT(DL
.getPointerSizeInBits(AS
));
246 /// Return the in-memory pointer type for the given address space, defaults to
247 /// the pointer type from the data layout. FIXME: The default needs to be
248 /// removed once all the code is updated.
249 MVT
getPointerMemTy(const DataLayout
&DL
, uint32_t AS
= 0) const {
250 return MVT::getIntegerVT(DL
.getPointerSizeInBits(AS
));
253 /// Return the type for frame index, which is determined by
254 /// the alloca address space specified through the data layout.
255 MVT
getFrameIndexTy(const DataLayout
&DL
) const {
256 return getPointerTy(DL
, DL
.getAllocaAddrSpace());
259 /// Return the type for operands of fence.
260 /// TODO: Let fence operands be of i32 type and remove this.
261 virtual MVT
getFenceOperandTy(const DataLayout
&DL
) const {
262 return getPointerTy(DL
);
265 /// EVT is not used in-tree, but is used by out-of-tree target.
266 /// A documentation for this function would be nice...
267 virtual MVT
getScalarShiftAmountTy(const DataLayout
&, EVT
) const;
269 EVT
getShiftAmountTy(EVT LHSTy
, const DataLayout
&DL
,
270 bool LegalTypes
= true) const;
272 /// Returns the type to be used for the index operand of:
273 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
274 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
275 virtual MVT
getVectorIdxTy(const DataLayout
&DL
) const {
276 return getPointerTy(DL
);
279 virtual bool isSelectSupported(SelectSupportKind
/*kind*/) const {
283 /// Return true if it is profitable to convert a select of FP constants into
284 /// a constant pool load whose address depends on the select condition. The
285 /// parameter may be used to differentiate a select with FP compare from
287 virtual bool reduceSelectOfFPConstantLoads(EVT CmpOpVT
) const {
291 /// Return true if multiple condition registers are available.
292 bool hasMultipleConditionRegisters() const {
293 return HasMultipleConditionRegisters
;
296 /// Return true if the target has BitExtract instructions.
297 bool hasExtractBitsInsn() const { return HasExtractBitsInsn
; }
299 /// Return the preferred vector type legalization action.
300 virtual TargetLoweringBase::LegalizeTypeAction
301 getPreferredVectorAction(MVT VT
) const {
302 // The default action for one element vectors is to scalarize
303 if (VT
.getVectorNumElements() == 1)
304 return TypeScalarizeVector
;
305 // The default action for an odd-width vector is to widen.
306 if (!VT
.isPow2VectorType())
307 return TypeWidenVector
;
308 // The default action for other vectors is to promote
309 return TypePromoteInteger
;
312 // There are two general methods for expanding a BUILD_VECTOR node:
313 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
315 // 2. Build the vector on the stack and then load it.
316 // If this function returns true, then method (1) will be used, subject to
317 // the constraint that all of the necessary shuffles are legal (as determined
318 // by isShuffleMaskLegal). If this function returns false, then method (2) is
319 // always used. The vector type, and the number of defined values, are
322 shouldExpandBuildVectorWithShuffles(EVT
/* VT */,
323 unsigned DefinedValues
) const {
324 return DefinedValues
< 3;
327 /// Return true if integer divide is usually cheaper than a sequence of
328 /// several shifts, adds, and multiplies for this target.
329 /// The definition of "cheaper" may depend on whether we're optimizing
330 /// for speed or for size.
331 virtual bool isIntDivCheap(EVT VT
, AttributeList Attr
) const { return false; }
333 /// Return true if the target can handle a standalone remainder operation.
334 virtual bool hasStandaloneRem(EVT VT
) const {
338 /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
339 virtual bool isFsqrtCheap(SDValue X
, SelectionDAG
&DAG
) const {
340 // Default behavior is to replace SQRT(X) with X*RSQRT(X).
344 /// Reciprocal estimate status values used by the functions below.
345 enum ReciprocalEstimate
: int {
351 /// Return a ReciprocalEstimate enum value for a square root of the given type
352 /// based on the function's attributes. If the operation is not overridden by
353 /// the function's attributes, "Unspecified" is returned and target defaults
354 /// are expected to be used for instruction selection.
355 int getRecipEstimateSqrtEnabled(EVT VT
, MachineFunction
&MF
) const;
357 /// Return a ReciprocalEstimate enum value for a division of the given type
358 /// based on the function's attributes. If the operation is not overridden by
359 /// the function's attributes, "Unspecified" is returned and target defaults
360 /// are expected to be used for instruction selection.
361 int getRecipEstimateDivEnabled(EVT VT
, MachineFunction
&MF
) const;
363 /// Return the refinement step count for a square root of the given type based
364 /// on the function's attributes. If the operation is not overridden by
365 /// the function's attributes, "Unspecified" is returned and target defaults
366 /// are expected to be used for instruction selection.
367 int getSqrtRefinementSteps(EVT VT
, MachineFunction
&MF
) const;
369 /// Return the refinement step count for a division of the given type based
370 /// on the function's attributes. If the operation is not overridden by
371 /// the function's attributes, "Unspecified" is returned and target defaults
372 /// are expected to be used for instruction selection.
373 int getDivRefinementSteps(EVT VT
, MachineFunction
&MF
) const;
375 /// Returns true if target has indicated at least one type should be bypassed.
376 bool isSlowDivBypassed() const { return !BypassSlowDivWidths
.empty(); }
378 /// Returns map of slow types for division or remainder with corresponding
380 const DenseMap
<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
381 return BypassSlowDivWidths
;
384 /// Return true if Flow Control is an expensive operation that should be
386 bool isJumpExpensive() const { return JumpIsExpensive
; }
388 /// Return true if selects are only cheaper than branches if the branch is
389 /// unlikely to be predicted right.
390 bool isPredictableSelectExpensive() const {
391 return PredictableSelectIsExpensive
;
394 /// If a branch or a select condition is skewed in one direction by more than
395 /// this factor, it is very likely to be predicted correctly.
396 virtual BranchProbability
getPredictableBranchThreshold() const;
398 /// Return true if the following transform is beneficial:
399 /// fold (conv (load x)) -> (load (conv*)x)
400 /// On architectures that don't natively support some vector loads
401 /// efficiently, casting the load to a smaller vector of larger types and
402 /// loading is more efficient, however, this can be undone by optimizations in
404 virtual bool isLoadBitCastBeneficial(EVT LoadVT
, EVT BitcastVT
,
405 const SelectionDAG
&DAG
,
406 const MachineMemOperand
&MMO
) const {
407 // Don't do if we could do an indexed load on the original type, but not on
409 if (!LoadVT
.isSimple() || !BitcastVT
.isSimple())
412 MVT LoadMVT
= LoadVT
.getSimpleVT();
414 // Don't bother doing this if it's just going to be promoted again later, as
415 // doing so might interfere with other combines.
416 if (getOperationAction(ISD::LOAD
, LoadMVT
) == Promote
&&
417 getTypeToPromoteTo(ISD::LOAD
, LoadMVT
) == BitcastVT
.getSimpleVT())
421 return allowsMemoryAccess(*DAG
.getContext(), DAG
.getDataLayout(), BitcastVT
,
425 /// Return true if the following transform is beneficial:
426 /// (store (y (conv x)), y*)) -> (store x, (x*))
427 virtual bool isStoreBitCastBeneficial(EVT StoreVT
, EVT BitcastVT
,
428 const SelectionDAG
&DAG
,
429 const MachineMemOperand
&MMO
) const {
430 // Default to the same logic as loads.
431 return isLoadBitCastBeneficial(StoreVT
, BitcastVT
, DAG
, MMO
);
434 /// Return true if it is expected to be cheaper to do a store of a non-zero
435 /// vector constant with the given size and type for the address space than to
436 /// store the individual scalar element constants.
437 virtual bool storeOfVectorConstantIsCheap(EVT MemVT
,
439 unsigned AddrSpace
) const {
443 /// Allow store merging for the specified type after legalization in addition
444 /// to before legalization. This may transform stores that do not exist
445 /// earlier (for example, stores created from intrinsics).
446 virtual bool mergeStoresAfterLegalization(EVT MemVT
) const {
450 /// Returns if it's reasonable to merge stores to MemVT size.
451 virtual bool canMergeStoresTo(unsigned AS
, EVT MemVT
,
452 const SelectionDAG
&DAG
) const {
456 /// Return true if it is cheap to speculate a call to intrinsic cttz.
457 virtual bool isCheapToSpeculateCttz() const {
461 /// Return true if it is cheap to speculate a call to intrinsic ctlz.
462 virtual bool isCheapToSpeculateCtlz() const {
466 /// Return true if ctlz instruction is fast.
467 virtual bool isCtlzFast() const {
471 /// Return true if it is safe to transform an integer-domain bitwise operation
472 /// into the equivalent floating-point operation. This should be set to true
473 /// if the target has IEEE-754-compliant fabs/fneg operations for the input
475 virtual bool hasBitPreservingFPLogic(EVT VT
) const {
479 /// Return true if it is cheaper to split the store of a merged int val
480 /// from a pair of smaller values into multiple stores.
481 virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy
, EVT HTy
) const {
485 /// Return if the target supports combining a
488 /// %andResult = and %val1, #mask
489 /// %icmpResult = icmp %andResult, 0
491 /// into a single machine instruction of a form like:
493 /// cc = test %register, #mask
495 virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction
&AndI
) const {
499 /// Use bitwise logic to make pairs of compares more efficient. For example:
500 /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
501 /// This should be true when it takes more than one instruction to lower
502 /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
503 /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
504 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT
) const {
508 /// Return the preferred operand type if the target has a quick way to compare
509 /// integer values of the given size. Assume that any legal integer type can
510 /// be compared efficiently. Targets may override this to allow illegal wide
511 /// types to return a vector type if there is support to compare that type.
512 virtual MVT
hasFastEqualityCompare(unsigned NumBits
) const {
513 MVT VT
= MVT::getIntegerVT(NumBits
);
514 return isTypeLegal(VT
) ? VT
: MVT::INVALID_SIMPLE_VALUE_TYPE
;
517 /// Return true if the target should transform:
518 /// (X & Y) == Y ---> (~X & Y) == 0
519 /// (X & Y) != Y ---> (~X & Y) != 0
521 /// This may be profitable if the target has a bitwise and-not operation that
522 /// sets comparison flags. A target may want to limit the transformation based
523 /// on the type of Y or if Y is a constant.
525 /// Note that the transform will not occur if Y is known to be a power-of-2
526 /// because a mask and compare of a single bit can be handled by inverting the
527 /// predicate, for example:
528 /// (X & 8) == 8 ---> (X & 8) != 0
529 virtual bool hasAndNotCompare(SDValue Y
) const {
533 /// Return true if the target has a bitwise and-not operation:
535 /// This can be used to simplify select or other instructions.
536 virtual bool hasAndNot(SDValue X
) const {
537 // If the target has the more complex version of this operation, assume that
538 // it has this operation too.
539 return hasAndNotCompare(X
);
542 /// Return true if the target has a bit-test instruction:
543 /// (X & (1 << Y)) ==/!= 0
544 /// This knowledge can be used to prevent breaking the pattern,
545 /// or creating it if it could be recognized.
546 virtual bool hasBitTest(SDValue X
, SDValue Y
) const { return false; }
548 /// There are two ways to clear extreme bits (either low or high):
549 /// Mask: x & (-1 << y) (the instcombine canonical form)
550 /// Shifts: x >> y << y
551 /// Return true if the variant with 2 variable shifts is preferred.
552 /// Return false if there is no preference.
553 virtual bool shouldFoldMaskToVariableShiftPair(SDValue X
) const {
554 // By default, let's assume that no one prefers shifts.
558 /// Return true if it is profitable to fold a pair of shifts into a mask.
559 /// This is usually true on most targets. But some targets, like Thumb1,
560 /// have immediate shift instructions, but no immediate "and" instruction;
561 /// this makes the fold unprofitable.
562 virtual bool shouldFoldConstantShiftPairToMask(const SDNode
*N
,
563 CombineLevel Level
) const {
567 /// Should we tranform the IR-optimal check for whether given truncation
568 /// down into KeptBits would be truncating or not:
569 /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits)
570 /// Into it's more traditional form:
571 /// ((%x << C) a>> C) dstcond %x
572 /// Return true if we should transform.
573 /// Return false if there is no preference.
574 virtual bool shouldTransformSignedTruncationCheck(EVT XVT
,
575 unsigned KeptBits
) const {
576 // By default, let's assume that no one prefers shifts.
580 /// Given the pattern
581 /// (X & (C l>>/<< Y)) ==/!= 0
582 /// return true if it should be transformed into:
583 /// ((X <</l>> Y) & C) ==/!= 0
584 /// WARNING: if 'X' is a constant, the fold may deadlock!
585 /// FIXME: we could avoid passing XC, but we can't use isConstOrConstSplat()
586 /// here because it can end up being not linked in.
587 virtual bool shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd(
588 SDValue X
, ConstantSDNode
*XC
, ConstantSDNode
*CC
, SDValue Y
,
589 unsigned OldShiftOpcode
, unsigned NewShiftOpcode
,
590 SelectionDAG
&DAG
) const {
591 if (hasBitTest(X
, Y
)) {
592 // One interesting pattern that we'd want to form is 'bit test':
593 // ((1 << Y) & C) ==/!= 0
594 // But we also need to be careful not to try to reverse that fold.
596 // Is this '1 << Y' ?
597 if (OldShiftOpcode
== ISD::SHL
&& CC
->isOne())
598 return false; // Keep the 'bit test' pattern.
600 // Will it be '1 << Y' after the transform ?
601 if (XC
&& NewShiftOpcode
== ISD::SHL
&& XC
->isOne())
602 return true; // Do form the 'bit test' pattern.
605 // If 'X' is a constant, and we transform, then we will immediately
606 // try to undo the fold, thus causing endless combine loop.
607 // So by default, let's assume everyone prefers the fold
608 // iff 'X' is not a constant.
612 /// These two forms are equivalent:
613 /// sub %y, (xor %x, -1)
614 /// add (add %x, 1), %y
615 /// The variant with two add's is IR-canonical.
616 /// Some targets may prefer one to the other.
617 virtual bool preferIncOfAddToSubOfNot(EVT VT
) const {
618 // By default, let's assume that everyone prefers the form with two add's.
622 /// Return true if the target wants to use the optimization that
623 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
624 /// promotedInst1(...(promotedInstN(ext(load)))).
625 bool enableExtLdPromotion() const { return EnableExtLdPromotion
; }
627 /// Return true if the target can combine store(extractelement VectorTy,
629 /// \p Cost[out] gives the cost of that transformation when this is true.
630 virtual bool canCombineStoreAndExtract(Type
*VectorTy
, Value
*Idx
,
631 unsigned &Cost
) const {
635 /// Return true if inserting a scalar into a variable element of an undef
636 /// vector is more efficiently handled by splatting the scalar instead.
637 virtual bool shouldSplatInsEltVarIndex(EVT
) const {
641 /// Return true if target always beneficiates from combining into FMA for a
642 /// given value type. This must typically return false on targets where FMA
643 /// takes more cycles to execute than FADD.
644 virtual bool enableAggressiveFMAFusion(EVT VT
) const {
648 /// Return the ValueType of the result of SETCC operations.
649 virtual EVT
getSetCCResultType(const DataLayout
&DL
, LLVMContext
&Context
,
652 /// Return the ValueType for comparison libcalls. Comparions libcalls include
653 /// floating point comparion calls, and Ordered/Unordered check calls on
654 /// floating point numbers.
656 MVT::SimpleValueType
getCmpLibcallReturnType() const;
658 /// For targets without i1 registers, this gives the nature of the high-bits
659 /// of boolean values held in types wider than i1.
661 /// "Boolean values" are special true/false values produced by nodes like
662 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
663 /// Not to be confused with general values promoted from i1. Some cpus
664 /// distinguish between vectors of boolean and scalars; the isVec parameter
665 /// selects between the two kinds. For example on X86 a scalar boolean should
666 /// be zero extended from i1, while the elements of a vector of booleans
667 /// should be sign extended from i1.
669 /// Some cpus also treat floating point types the same way as they treat
670 /// vectors instead of the way they treat scalars.
671 BooleanContent
getBooleanContents(bool isVec
, bool isFloat
) const {
673 return BooleanVectorContents
;
674 return isFloat
? BooleanFloatContents
: BooleanContents
;
677 BooleanContent
getBooleanContents(EVT Type
) const {
678 return getBooleanContents(Type
.isVector(), Type
.isFloatingPoint());
681 /// Return target scheduling preference.
682 Sched::Preference
getSchedulingPreference() const {
683 return SchedPreferenceInfo
;
686 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
687 /// for different nodes. This function returns the preference (or none) for
689 virtual Sched::Preference
getSchedulingPreference(SDNode
*) const {
693 /// Return the register class that should be used for the specified value
695 virtual const TargetRegisterClass
*getRegClassFor(MVT VT
, bool isDivergent
= false) const {
697 const TargetRegisterClass
*RC
= RegClassForVT
[VT
.SimpleTy
];
698 assert(RC
&& "This value type is not natively supported!");
702 /// Allows target to decide about the register class of the
703 /// specific value that is live outside the defining block.
704 /// Returns true if the value needs uniform register class.
705 virtual bool requiresUniformRegister(MachineFunction
&MF
,
706 const Value
*) const {
710 /// Return the 'representative' register class for the specified value
713 /// The 'representative' register class is the largest legal super-reg
714 /// register class for the register class of the value type. For example, on
715 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
716 /// register class is GR64 on x86_64.
717 virtual const TargetRegisterClass
*getRepRegClassFor(MVT VT
) const {
718 const TargetRegisterClass
*RC
= RepRegClassForVT
[VT
.SimpleTy
];
722 /// Return the cost of the 'representative' register class for the specified
724 virtual uint8_t getRepRegClassCostFor(MVT VT
) const {
725 return RepRegClassCostForVT
[VT
.SimpleTy
];
728 /// Return true if SHIFT instructions should be expanded to SHIFT_PARTS
729 /// instructions, and false if a library call is preferred (e.g for code-size
731 virtual bool shouldExpandShift(SelectionDAG
&DAG
, SDNode
*N
) const {
735 /// Return true if the target has native support for the specified value type.
736 /// This means that it has a register that directly holds it without
737 /// promotions or expansions.
738 bool isTypeLegal(EVT VT
) const {
739 assert(!VT
.isSimple() ||
740 (unsigned)VT
.getSimpleVT().SimpleTy
< array_lengthof(RegClassForVT
));
741 return VT
.isSimple() && RegClassForVT
[VT
.getSimpleVT().SimpleTy
] != nullptr;
744 class ValueTypeActionImpl
{
745 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
746 /// that indicates how instruction selection should deal with the type.
747 LegalizeTypeAction ValueTypeActions
[MVT::LAST_VALUETYPE
];
750 ValueTypeActionImpl() {
751 std::fill(std::begin(ValueTypeActions
), std::end(ValueTypeActions
),
755 LegalizeTypeAction
getTypeAction(MVT VT
) const {
756 return ValueTypeActions
[VT
.SimpleTy
];
759 void setTypeAction(MVT VT
, LegalizeTypeAction Action
) {
760 ValueTypeActions
[VT
.SimpleTy
] = Action
;
764 const ValueTypeActionImpl
&getValueTypeActions() const {
765 return ValueTypeActions
;
768 /// Return how we should legalize values of this type, either it is already
769 /// legal (return 'Legal') or we need to promote it to a larger type (return
770 /// 'Promote'), or we need to expand it into multiple registers of smaller
771 /// integer type (return 'Expand'). 'Custom' is not an option.
772 LegalizeTypeAction
getTypeAction(LLVMContext
&Context
, EVT VT
) const {
773 return getTypeConversion(Context
, VT
).first
;
775 LegalizeTypeAction
getTypeAction(MVT VT
) const {
776 return ValueTypeActions
.getTypeAction(VT
);
779 /// For types supported by the target, this is an identity function. For
780 /// types that must be promoted to larger types, this returns the larger type
781 /// to promote to. For integer types that are larger than the largest integer
782 /// register, this contains one step in the expansion to get to the smaller
783 /// register. For illegal floating point types, this returns the integer type
785 EVT
getTypeToTransformTo(LLVMContext
&Context
, EVT VT
) const {
786 return getTypeConversion(Context
, VT
).second
;
789 /// For types supported by the target, this is an identity function. For
790 /// types that must be expanded (i.e. integer types that are larger than the
791 /// largest integer register or illegal floating point types), this returns
792 /// the largest legal type it will be expanded to.
793 EVT
getTypeToExpandTo(LLVMContext
&Context
, EVT VT
) const {
794 assert(!VT
.isVector());
796 switch (getTypeAction(Context
, VT
)) {
799 case TypeExpandInteger
:
800 VT
= getTypeToTransformTo(Context
, VT
);
803 llvm_unreachable("Type is not legal nor is it to be expanded!");
808 /// Vector types are broken down into some number of legal first class types.
809 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
810 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
811 /// turns into 4 EVT::i32 values with both PPC and X86.
813 /// This method returns the number of registers needed, and the VT for each
814 /// register. It also returns the VT and quantity of the intermediate values
815 /// before they are promoted/expanded.
816 unsigned getVectorTypeBreakdown(LLVMContext
&Context
, EVT VT
,
818 unsigned &NumIntermediates
,
819 MVT
&RegisterVT
) const;
821 /// Certain targets such as MIPS require that some types such as vectors are
822 /// always broken down into scalars in some contexts. This occurs even if the
823 /// vector type is legal.
824 virtual unsigned getVectorTypeBreakdownForCallingConv(
825 LLVMContext
&Context
, CallingConv::ID CC
, EVT VT
, EVT
&IntermediateVT
,
826 unsigned &NumIntermediates
, MVT
&RegisterVT
) const {
827 return getVectorTypeBreakdown(Context
, VT
, IntermediateVT
, NumIntermediates
,
831 struct IntrinsicInfo
{
832 unsigned opc
= 0; // target opcode
833 EVT memVT
; // memory VT
835 // value representing memory location
836 PointerUnion
<const Value
*, const PseudoSourceValue
*> ptrVal
;
838 int offset
= 0; // offset off of ptrVal
839 unsigned size
= 0; // the size of the memory location
840 // (taken from memVT if zero)
841 MaybeAlign align
= Align::None(); // alignment
843 MachineMemOperand::Flags flags
= MachineMemOperand::MONone
;
844 IntrinsicInfo() = default;
847 /// Given an intrinsic, checks if on the target the intrinsic will need to map
848 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
849 /// true and store the intrinsic information into the IntrinsicInfo that was
850 /// passed to the function.
851 virtual bool getTgtMemIntrinsic(IntrinsicInfo
&, const CallInst
&,
853 unsigned /*Intrinsic*/) const {
857 /// Returns true if the target can instruction select the specified FP
858 /// immediate natively. If false, the legalizer will materialize the FP
859 /// immediate as a load from a constant pool.
860 virtual bool isFPImmLegal(const APFloat
& /*Imm*/, EVT
/*VT*/,
861 bool ForCodeSize
= false) const {
865 /// Targets can use this to indicate that they only support *some*
866 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
867 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
869 virtual bool isShuffleMaskLegal(ArrayRef
<int> /*Mask*/, EVT
/*VT*/) const {
873 /// Returns true if the operation can trap for the value type.
875 /// VT must be a legal type. By default, we optimistically assume most
876 /// operations don't trap except for integer divide and remainder.
877 virtual bool canOpTrap(unsigned Op
, EVT VT
) const;
879 /// Similar to isShuffleMaskLegal. Targets can use this to indicate if there
880 /// is a suitable VECTOR_SHUFFLE that can be used to replace a VAND with a
881 /// constant pool entry.
882 virtual bool isVectorClearMaskLegal(ArrayRef
<int> /*Mask*/,
887 /// Return how this operation should be treated: either it is legal, needs to
888 /// be promoted to a larger size, needs to be expanded to some other code
889 /// sequence, or the target has a custom expander for it.
890 LegalizeAction
getOperationAction(unsigned Op
, EVT VT
) const {
891 if (VT
.isExtended()) return Expand
;
892 // If a target-specific SDNode requires legalization, require the target
893 // to provide custom legalization for it.
894 if (Op
>= array_lengthof(OpActions
[0])) return Custom
;
895 return OpActions
[(unsigned)VT
.getSimpleVT().SimpleTy
][Op
];
898 /// Custom method defined by each target to indicate if an operation which
899 /// may require a scale is supported natively by the target.
900 /// If not, the operation is illegal.
901 virtual bool isSupportedFixedPointOperation(unsigned Op
, EVT VT
,
902 unsigned Scale
) const {
906 /// Some fixed point operations may be natively supported by the target but
907 /// only for specific scales. This method allows for checking
908 /// if the width is supported by the target for a given operation that may
910 LegalizeAction
getFixedPointOperationAction(unsigned Op
, EVT VT
,
911 unsigned Scale
) const {
912 auto Action
= getOperationAction(Op
, VT
);
916 // This operation is supported in this type but may only work on specific
921 llvm_unreachable("Unexpected fixed point operation.");
923 case ISD::SMULFIXSAT
:
925 case ISD::UMULFIXSAT
:
926 Supported
= isSupportedFixedPointOperation(Op
, VT
, Scale
);
930 return Supported
? Action
: Expand
;
933 // If Op is a strict floating-point operation, return the result
934 // of getOperationAction for the equivalent non-strict operation.
935 LegalizeAction
getStrictFPOperationAction(unsigned Op
, EVT VT
) const {
938 default: llvm_unreachable("Unexpected FP pseudo-opcode");
939 case ISD::STRICT_FADD
: EqOpc
= ISD::FADD
; break;
940 case ISD::STRICT_FSUB
: EqOpc
= ISD::FSUB
; break;
941 case ISD::STRICT_FMUL
: EqOpc
= ISD::FMUL
; break;
942 case ISD::STRICT_FDIV
: EqOpc
= ISD::FDIV
; break;
943 case ISD::STRICT_FREM
: EqOpc
= ISD::FREM
; break;
944 case ISD::STRICT_FSQRT
: EqOpc
= ISD::FSQRT
; break;
945 case ISD::STRICT_FPOW
: EqOpc
= ISD::FPOW
; break;
946 case ISD::STRICT_FPOWI
: EqOpc
= ISD::FPOWI
; break;
947 case ISD::STRICT_FMA
: EqOpc
= ISD::FMA
; break;
948 case ISD::STRICT_FSIN
: EqOpc
= ISD::FSIN
; break;
949 case ISD::STRICT_FCOS
: EqOpc
= ISD::FCOS
; break;
950 case ISD::STRICT_FEXP
: EqOpc
= ISD::FEXP
; break;
951 case ISD::STRICT_FEXP2
: EqOpc
= ISD::FEXP2
; break;
952 case ISD::STRICT_FLOG
: EqOpc
= ISD::FLOG
; break;
953 case ISD::STRICT_FLOG10
: EqOpc
= ISD::FLOG10
; break;
954 case ISD::STRICT_FLOG2
: EqOpc
= ISD::FLOG2
; break;
955 case ISD::STRICT_FRINT
: EqOpc
= ISD::FRINT
; break;
956 case ISD::STRICT_FNEARBYINT
: EqOpc
= ISD::FNEARBYINT
; break;
957 case ISD::STRICT_FMAXNUM
: EqOpc
= ISD::FMAXNUM
; break;
958 case ISD::STRICT_FMINNUM
: EqOpc
= ISD::FMINNUM
; break;
959 case ISD::STRICT_FCEIL
: EqOpc
= ISD::FCEIL
; break;
960 case ISD::STRICT_FFLOOR
: EqOpc
= ISD::FFLOOR
; break;
961 case ISD::STRICT_FROUND
: EqOpc
= ISD::FROUND
; break;
962 case ISD::STRICT_FTRUNC
: EqOpc
= ISD::FTRUNC
; break;
963 case ISD::STRICT_FP_TO_SINT
: EqOpc
= ISD::FP_TO_SINT
; break;
964 case ISD::STRICT_FP_TO_UINT
: EqOpc
= ISD::FP_TO_UINT
; break;
965 case ISD::STRICT_FP_ROUND
: EqOpc
= ISD::FP_ROUND
; break;
966 case ISD::STRICT_FP_EXTEND
: EqOpc
= ISD::FP_EXTEND
; break;
969 return getOperationAction(EqOpc
, VT
);
972 /// Return true if the specified operation is legal on this target or can be
973 /// made legal with custom lowering. This is used to help guide high-level
974 /// lowering decisions.
975 bool isOperationLegalOrCustom(unsigned Op
, EVT VT
) const {
976 return (VT
== MVT::Other
|| isTypeLegal(VT
)) &&
977 (getOperationAction(Op
, VT
) == Legal
||
978 getOperationAction(Op
, VT
) == Custom
);
981 /// Return true if the specified operation is legal on this target or can be
982 /// made legal using promotion. This is used to help guide high-level lowering
984 bool isOperationLegalOrPromote(unsigned Op
, EVT VT
) const {
985 return (VT
== MVT::Other
|| isTypeLegal(VT
)) &&
986 (getOperationAction(Op
, VT
) == Legal
||
987 getOperationAction(Op
, VT
) == Promote
);
990 /// Return true if the specified operation is legal on this target or can be
991 /// made legal with custom lowering or using promotion. This is used to help
992 /// guide high-level lowering decisions.
993 bool isOperationLegalOrCustomOrPromote(unsigned Op
, EVT VT
) const {
994 return (VT
== MVT::Other
|| isTypeLegal(VT
)) &&
995 (getOperationAction(Op
, VT
) == Legal
||
996 getOperationAction(Op
, VT
) == Custom
||
997 getOperationAction(Op
, VT
) == Promote
);
1000 /// Return true if the operation uses custom lowering, regardless of whether
1001 /// the type is legal or not.
1002 bool isOperationCustom(unsigned Op
, EVT VT
) const {
1003 return getOperationAction(Op
, VT
) == Custom
;
1006 /// Return true if lowering to a jump table is allowed.
1007 virtual bool areJTsAllowed(const Function
*Fn
) const {
1008 if (Fn
->getFnAttribute("no-jump-tables").getValueAsString() == "true")
1011 return isOperationLegalOrCustom(ISD::BR_JT
, MVT::Other
) ||
1012 isOperationLegalOrCustom(ISD::BRIND
, MVT::Other
);
1015 /// Check whether the range [Low,High] fits in a machine word.
1016 bool rangeFitsInWord(const APInt
&Low
, const APInt
&High
,
1017 const DataLayout
&DL
) const {
1018 // FIXME: Using the pointer type doesn't seem ideal.
1019 uint64_t BW
= DL
.getIndexSizeInBits(0u);
1020 uint64_t Range
= (High
- Low
).getLimitedValue(UINT64_MAX
- 1) + 1;
1024 /// Return true if lowering to a jump table is suitable for a set of case
1025 /// clusters which may contain \p NumCases cases, \p Range range of values.
1026 virtual bool isSuitableForJumpTable(const SwitchInst
*SI
, uint64_t NumCases
,
1027 uint64_t Range
) const {
1028 // FIXME: This function check the maximum table size and density, but the
1029 // minimum size is not checked. It would be nice if the minimum size is
1030 // also combined within this function. Currently, the minimum size check is
1031 // performed in findJumpTable() in SelectionDAGBuiler and
1032 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
1033 const bool OptForSize
= SI
->getParent()->getParent()->hasOptSize();
1034 const unsigned MinDensity
= getMinimumJumpTableDensity(OptForSize
);
1035 const unsigned MaxJumpTableSize
= getMaximumJumpTableSize();
1037 // Check whether the number of cases is small enough and
1038 // the range is dense enough for a jump table.
1039 if ((OptForSize
|| Range
<= MaxJumpTableSize
) &&
1040 (NumCases
* 100 >= Range
* MinDensity
)) {
1046 /// Return true if lowering to a bit test is suitable for a set of case
1047 /// clusters which contains \p NumDests unique destinations, \p Low and
1048 /// \p High as its lowest and highest case values, and expects \p NumCmps
1049 /// case value comparisons. Check if the number of destinations, comparison
1050 /// metric, and range are all suitable.
1051 bool isSuitableForBitTests(unsigned NumDests
, unsigned NumCmps
,
1052 const APInt
&Low
, const APInt
&High
,
1053 const DataLayout
&DL
) const {
1054 // FIXME: I don't think NumCmps is the correct metric: a single case and a
1055 // range of cases both require only one branch to lower. Just looking at the
1056 // number of clusters and destinations should be enough to decide whether to
1059 // To lower a range with bit tests, the range must fit the bitwidth of a
1061 if (!rangeFitsInWord(Low
, High
, DL
))
1064 // Decide whether it's profitable to lower this range with bit tests. Each
1065 // destination requires a bit test and branch, and there is an overall range
1066 // check branch. For a small number of clusters, separate comparisons might
1067 // be cheaper, and for many destinations, splitting the range might be
1069 return (NumDests
== 1 && NumCmps
>= 3) || (NumDests
== 2 && NumCmps
>= 5) ||
1070 (NumDests
== 3 && NumCmps
>= 6);
1073 /// Return true if the specified operation is illegal on this target or
1074 /// unlikely to be made legal with custom lowering. This is used to help guide
1075 /// high-level lowering decisions.
1076 bool isOperationExpand(unsigned Op
, EVT VT
) const {
1077 return (!isTypeLegal(VT
) || getOperationAction(Op
, VT
) == Expand
);
1080 /// Return true if the specified operation is legal on this target.
1081 bool isOperationLegal(unsigned Op
, EVT VT
) const {
1082 return (VT
== MVT::Other
|| isTypeLegal(VT
)) &&
1083 getOperationAction(Op
, VT
) == Legal
;
1086 /// Return how this load with extension should be treated: either it is legal,
1087 /// needs to be promoted to a larger size, needs to be expanded to some other
1088 /// code sequence, or the target has a custom expander for it.
1089 LegalizeAction
getLoadExtAction(unsigned ExtType
, EVT ValVT
,
1091 if (ValVT
.isExtended() || MemVT
.isExtended()) return Expand
;
1092 unsigned ValI
= (unsigned) ValVT
.getSimpleVT().SimpleTy
;
1093 unsigned MemI
= (unsigned) MemVT
.getSimpleVT().SimpleTy
;
1094 assert(ExtType
< ISD::LAST_LOADEXT_TYPE
&& ValI
< MVT::LAST_VALUETYPE
&&
1095 MemI
< MVT::LAST_VALUETYPE
&& "Table isn't big enough!");
1096 unsigned Shift
= 4 * ExtType
;
1097 return (LegalizeAction
)((LoadExtActions
[ValI
][MemI
] >> Shift
) & 0xf);
1100 /// Return true if the specified load with extension is legal on this target.
1101 bool isLoadExtLegal(unsigned ExtType
, EVT ValVT
, EVT MemVT
) const {
1102 return getLoadExtAction(ExtType
, ValVT
, MemVT
) == Legal
;
1105 /// Return true if the specified load with extension is legal or custom
1107 bool isLoadExtLegalOrCustom(unsigned ExtType
, EVT ValVT
, EVT MemVT
) const {
1108 return getLoadExtAction(ExtType
, ValVT
, MemVT
) == Legal
||
1109 getLoadExtAction(ExtType
, ValVT
, MemVT
) == Custom
;
1112 /// Return how this store with truncation should be treated: either it is
1113 /// legal, needs to be promoted to a larger size, needs to be expanded to some
1114 /// other code sequence, or the target has a custom expander for it.
1115 LegalizeAction
getTruncStoreAction(EVT ValVT
, EVT MemVT
) const {
1116 if (ValVT
.isExtended() || MemVT
.isExtended()) return Expand
;
1117 unsigned ValI
= (unsigned) ValVT
.getSimpleVT().SimpleTy
;
1118 unsigned MemI
= (unsigned) MemVT
.getSimpleVT().SimpleTy
;
1119 assert(ValI
< MVT::LAST_VALUETYPE
&& MemI
< MVT::LAST_VALUETYPE
&&
1120 "Table isn't big enough!");
1121 return TruncStoreActions
[ValI
][MemI
];
1124 /// Return true if the specified store with truncation is legal on this
1126 bool isTruncStoreLegal(EVT ValVT
, EVT MemVT
) const {
1127 return isTypeLegal(ValVT
) && getTruncStoreAction(ValVT
, MemVT
) == Legal
;
1130 /// Return true if the specified store with truncation has solution on this
1132 bool isTruncStoreLegalOrCustom(EVT ValVT
, EVT MemVT
) const {
1133 return isTypeLegal(ValVT
) &&
1134 (getTruncStoreAction(ValVT
, MemVT
) == Legal
||
1135 getTruncStoreAction(ValVT
, MemVT
) == Custom
);
1138 /// Return how the indexed load should be treated: either it is legal, needs
1139 /// to be promoted to a larger size, needs to be expanded to some other code
1140 /// sequence, or the target has a custom expander for it.
1142 getIndexedLoadAction(unsigned IdxMode
, MVT VT
) const {
1143 assert(IdxMode
< ISD::LAST_INDEXED_MODE
&& VT
.isValid() &&
1144 "Table isn't big enough!");
1145 unsigned Ty
= (unsigned)VT
.SimpleTy
;
1146 return (LegalizeAction
)((IndexedModeActions
[Ty
][IdxMode
] & 0xf0) >> 4);
1149 /// Return true if the specified indexed load is legal on this target.
1150 bool isIndexedLoadLegal(unsigned IdxMode
, EVT VT
) const {
1151 return VT
.isSimple() &&
1152 (getIndexedLoadAction(IdxMode
, VT
.getSimpleVT()) == Legal
||
1153 getIndexedLoadAction(IdxMode
, VT
.getSimpleVT()) == Custom
);
1156 /// Return how the indexed store should be treated: either it is legal, needs
1157 /// to be promoted to a larger size, needs to be expanded to some other code
1158 /// sequence, or the target has a custom expander for it.
1160 getIndexedStoreAction(unsigned IdxMode
, MVT VT
) const {
1161 assert(IdxMode
< ISD::LAST_INDEXED_MODE
&& VT
.isValid() &&
1162 "Table isn't big enough!");
1163 unsigned Ty
= (unsigned)VT
.SimpleTy
;
1164 return (LegalizeAction
)(IndexedModeActions
[Ty
][IdxMode
] & 0x0f);
1167 /// Return true if the specified indexed load is legal on this target.
1168 bool isIndexedStoreLegal(unsigned IdxMode
, EVT VT
) const {
1169 return VT
.isSimple() &&
1170 (getIndexedStoreAction(IdxMode
, VT
.getSimpleVT()) == Legal
||
1171 getIndexedStoreAction(IdxMode
, VT
.getSimpleVT()) == Custom
);
1174 /// Return how the condition code should be treated: either it is legal, needs
1175 /// to be expanded to some other code sequence, or the target has a custom
1176 /// expander for it.
1178 getCondCodeAction(ISD::CondCode CC
, MVT VT
) const {
1179 assert((unsigned)CC
< array_lengthof(CondCodeActions
) &&
1180 ((unsigned)VT
.SimpleTy
>> 3) < array_lengthof(CondCodeActions
[0]) &&
1181 "Table isn't big enough!");
1182 // See setCondCodeAction for how this is encoded.
1183 uint32_t Shift
= 4 * (VT
.SimpleTy
& 0x7);
1184 uint32_t Value
= CondCodeActions
[CC
][VT
.SimpleTy
>> 3];
1185 LegalizeAction Action
= (LegalizeAction
) ((Value
>> Shift
) & 0xF);
1186 assert(Action
!= Promote
&& "Can't promote condition code!");
1190 /// Return true if the specified condition code is legal on this target.
1191 bool isCondCodeLegal(ISD::CondCode CC
, MVT VT
) const {
1192 return getCondCodeAction(CC
, VT
) == Legal
;
1195 /// Return true if the specified condition code is legal or custom on this
1197 bool isCondCodeLegalOrCustom(ISD::CondCode CC
, MVT VT
) const {
1198 return getCondCodeAction(CC
, VT
) == Legal
||
1199 getCondCodeAction(CC
, VT
) == Custom
;
1202 /// If the action for this operation is to promote, this method returns the
1203 /// ValueType to promote to.
1204 MVT
getTypeToPromoteTo(unsigned Op
, MVT VT
) const {
1205 assert(getOperationAction(Op
, VT
) == Promote
&&
1206 "This operation isn't promoted!");
1208 // See if this has an explicit type specified.
1209 std::map
<std::pair
<unsigned, MVT::SimpleValueType
>,
1210 MVT::SimpleValueType
>::const_iterator PTTI
=
1211 PromoteToType
.find(std::make_pair(Op
, VT
.SimpleTy
));
1212 if (PTTI
!= PromoteToType
.end()) return PTTI
->second
;
1214 assert((VT
.isInteger() || VT
.isFloatingPoint()) &&
1215 "Cannot autopromote this type, add it with AddPromotedToType.");
1219 NVT
= (MVT::SimpleValueType
)(NVT
.SimpleTy
+1);
1220 assert(NVT
.isInteger() == VT
.isInteger() && NVT
!= MVT::isVoid
&&
1221 "Didn't find type to promote to!");
1222 } while (!isTypeLegal(NVT
) ||
1223 getOperationAction(Op
, NVT
) == Promote
);
1227 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1228 /// operations except for the pointer size. If AllowUnknown is true, this
1229 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1230 /// otherwise it will assert.
1231 EVT
getValueType(const DataLayout
&DL
, Type
*Ty
,
1232 bool AllowUnknown
= false) const {
1233 // Lower scalar pointers to native pointer types.
1234 if (auto *PTy
= dyn_cast
<PointerType
>(Ty
))
1235 return getPointerTy(DL
, PTy
->getAddressSpace());
1237 if (auto *VTy
= dyn_cast
<VectorType
>(Ty
)) {
1238 Type
*EltTy
= VTy
->getElementType();
1239 // Lower vectors of pointers to native pointer types.
1240 if (auto *PTy
= dyn_cast
<PointerType
>(EltTy
)) {
1241 EVT
PointerTy(getPointerTy(DL
, PTy
->getAddressSpace()));
1242 EltTy
= PointerTy
.getTypeForEVT(Ty
->getContext());
1244 return EVT::getVectorVT(Ty
->getContext(), EVT::getEVT(EltTy
, false),
1245 VTy
->getElementCount());
1248 return EVT::getEVT(Ty
, AllowUnknown
);
1251 EVT
getMemValueType(const DataLayout
&DL
, Type
*Ty
,
1252 bool AllowUnknown
= false) const {
1253 // Lower scalar pointers to native pointer types.
1254 if (PointerType
*PTy
= dyn_cast
<PointerType
>(Ty
))
1255 return getPointerMemTy(DL
, PTy
->getAddressSpace());
1256 else if (VectorType
*VTy
= dyn_cast
<VectorType
>(Ty
)) {
1257 Type
*Elm
= VTy
->getElementType();
1258 if (PointerType
*PT
= dyn_cast
<PointerType
>(Elm
)) {
1259 EVT
PointerTy(getPointerMemTy(DL
, PT
->getAddressSpace()));
1260 Elm
= PointerTy
.getTypeForEVT(Ty
->getContext());
1262 return EVT::getVectorVT(Ty
->getContext(), EVT::getEVT(Elm
, false),
1263 VTy
->getNumElements());
1266 return getValueType(DL
, Ty
, AllowUnknown
);
1270 /// Return the MVT corresponding to this LLVM type. See getValueType.
1271 MVT
getSimpleValueType(const DataLayout
&DL
, Type
*Ty
,
1272 bool AllowUnknown
= false) const {
1273 return getValueType(DL
, Ty
, AllowUnknown
).getSimpleVT();
1276 /// Return the desired alignment for ByVal or InAlloca aggregate function
1277 /// arguments in the caller parameter area. This is the actual alignment, not
1279 virtual unsigned getByValTypeAlignment(Type
*Ty
, const DataLayout
&DL
) const;
1281 /// Return the type of registers that this ValueType will eventually require.
1282 MVT
getRegisterType(MVT VT
) const {
1283 assert((unsigned)VT
.SimpleTy
< array_lengthof(RegisterTypeForVT
));
1284 return RegisterTypeForVT
[VT
.SimpleTy
];
1287 /// Return the type of registers that this ValueType will eventually require.
1288 MVT
getRegisterType(LLVMContext
&Context
, EVT VT
) const {
1289 if (VT
.isSimple()) {
1290 assert((unsigned)VT
.getSimpleVT().SimpleTy
<
1291 array_lengthof(RegisterTypeForVT
));
1292 return RegisterTypeForVT
[VT
.getSimpleVT().SimpleTy
];
1294 if (VT
.isVector()) {
1297 unsigned NumIntermediates
;
1298 (void)getVectorTypeBreakdown(Context
, VT
, VT1
,
1299 NumIntermediates
, RegisterVT
);
1302 if (VT
.isInteger()) {
1303 return getRegisterType(Context
, getTypeToTransformTo(Context
, VT
));
1305 llvm_unreachable("Unsupported extended type!");
1308 /// Return the number of registers that this ValueType will eventually
1311 /// This is one for any types promoted to live in larger registers, but may be
1312 /// more than one for types (like i64) that are split into pieces. For types
1313 /// like i140, which are first promoted then expanded, it is the number of
1314 /// registers needed to hold all the bits of the original type. For an i140
1315 /// on a 32 bit machine this means 5 registers.
1316 unsigned getNumRegisters(LLVMContext
&Context
, EVT VT
) const {
1317 if (VT
.isSimple()) {
1318 assert((unsigned)VT
.getSimpleVT().SimpleTy
<
1319 array_lengthof(NumRegistersForVT
));
1320 return NumRegistersForVT
[VT
.getSimpleVT().SimpleTy
];
1322 if (VT
.isVector()) {
1325 unsigned NumIntermediates
;
1326 return getVectorTypeBreakdown(Context
, VT
, VT1
, NumIntermediates
, VT2
);
1328 if (VT
.isInteger()) {
1329 unsigned BitWidth
= VT
.getSizeInBits();
1330 unsigned RegWidth
= getRegisterType(Context
, VT
).getSizeInBits();
1331 return (BitWidth
+ RegWidth
- 1) / RegWidth
;
1333 llvm_unreachable("Unsupported extended type!");
1336 /// Certain combinations of ABIs, Targets and features require that types
1337 /// are legal for some operations and not for other operations.
1338 /// For MIPS all vector types must be passed through the integer register set.
1339 virtual MVT
getRegisterTypeForCallingConv(LLVMContext
&Context
,
1340 CallingConv::ID CC
, EVT VT
) const {
1341 return getRegisterType(Context
, VT
);
1344 /// Certain targets require unusual breakdowns of certain types. For MIPS,
1345 /// this occurs when a vector type is used, as vector are passed through the
1346 /// integer register set.
1347 virtual unsigned getNumRegistersForCallingConv(LLVMContext
&Context
,
1350 return getNumRegisters(Context
, VT
);
1353 /// Certain targets have context senstive alignment requirements, where one
1354 /// type has the alignment requirement of another type.
1355 virtual unsigned getABIAlignmentForCallingConv(Type
*ArgTy
,
1356 DataLayout DL
) const {
1357 return DL
.getABITypeAlignment(ArgTy
);
1360 /// If true, then instruction selection should seek to shrink the FP constant
1361 /// of the specified type to a smaller type in order to save space and / or
1363 virtual bool ShouldShrinkFPConstant(EVT
) const { return true; }
1365 /// Return true if it is profitable to reduce a load to a smaller type.
1366 /// Example: (i16 (trunc (i32 (load x))) -> i16 load x
1367 virtual bool shouldReduceLoadWidth(SDNode
*Load
, ISD::LoadExtType ExtTy
,
1369 // By default, assume that it is cheaper to extract a subvector from a wide
1370 // vector load rather than creating multiple narrow vector loads.
1371 if (NewVT
.isVector() && !Load
->hasOneUse())
1377 /// When splitting a value of the specified type into parts, does the Lo
1378 /// or Hi part come first? This usually follows the endianness, except
1379 /// for ppcf128, where the Hi part always comes first.
1380 bool hasBigEndianPartOrdering(EVT VT
, const DataLayout
&DL
) const {
1381 return DL
.isBigEndian() || VT
== MVT::ppcf128
;
1384 /// If true, the target has custom DAG combine transformations that it can
1385 /// perform for the specified node.
1386 bool hasTargetDAGCombine(ISD::NodeType NT
) const {
1387 assert(unsigned(NT
>> 3) < array_lengthof(TargetDAGCombineArray
));
1388 return TargetDAGCombineArray
[NT
>> 3] & (1 << (NT
&7));
1391 unsigned getGatherAllAliasesMaxDepth() const {
1392 return GatherAllAliasesMaxDepth
;
1395 /// Returns the size of the platform's va_list object.
1396 virtual unsigned getVaListSizeInBits(const DataLayout
&DL
) const {
1397 return getPointerTy(DL
).getSizeInBits();
1400 /// Get maximum # of store operations permitted for llvm.memset
1402 /// This function returns the maximum number of store operations permitted
1403 /// to replace a call to llvm.memset. The value is set by the target at the
1404 /// performance threshold for such a replacement. If OptSize is true,
1405 /// return the limit for functions that have OptSize attribute.
1406 unsigned getMaxStoresPerMemset(bool OptSize
) const {
1407 return OptSize
? MaxStoresPerMemsetOptSize
: MaxStoresPerMemset
;
1410 /// Get maximum # of store operations permitted for llvm.memcpy
1412 /// This function returns the maximum number of store operations permitted
1413 /// to replace a call to llvm.memcpy. The value is set by the target at the
1414 /// performance threshold for such a replacement. If OptSize is true,
1415 /// return the limit for functions that have OptSize attribute.
1416 unsigned getMaxStoresPerMemcpy(bool OptSize
) const {
1417 return OptSize
? MaxStoresPerMemcpyOptSize
: MaxStoresPerMemcpy
;
1420 /// \brief Get maximum # of store operations to be glued together
1422 /// This function returns the maximum number of store operations permitted
1423 /// to glue together during lowering of llvm.memcpy. The value is set by
1424 // the target at the performance threshold for such a replacement.
1425 virtual unsigned getMaxGluedStoresPerMemcpy() const {
1426 return MaxGluedStoresPerMemcpy
;
1429 /// Get maximum # of load operations permitted for memcmp
1431 /// This function returns the maximum number of load operations permitted
1432 /// to replace a call to memcmp. The value is set by the target at the
1433 /// performance threshold for such a replacement. If OptSize is true,
1434 /// return the limit for functions that have OptSize attribute.
1435 unsigned getMaxExpandSizeMemcmp(bool OptSize
) const {
1436 return OptSize
? MaxLoadsPerMemcmpOptSize
: MaxLoadsPerMemcmp
;
1439 /// Get maximum # of store operations permitted for llvm.memmove
1441 /// This function returns the maximum number of store operations permitted
1442 /// to replace a call to llvm.memmove. The value is set by the target at the
1443 /// performance threshold for such a replacement. If OptSize is true,
1444 /// return the limit for functions that have OptSize attribute.
1445 unsigned getMaxStoresPerMemmove(bool OptSize
) const {
1446 return OptSize
? MaxStoresPerMemmoveOptSize
: MaxStoresPerMemmove
;
1449 /// Determine if the target supports unaligned memory accesses.
1451 /// This function returns true if the target allows unaligned memory accesses
1452 /// of the specified type in the given address space. If true, it also returns
1453 /// whether the unaligned memory access is "fast" in the last argument by
1454 /// reference. This is used, for example, in situations where an array
1455 /// copy/move/set is converted to a sequence of store operations. Its use
1456 /// helps to ensure that such replacements don't generate code that causes an
1457 /// alignment error (trap) on the target machine.
1458 virtual bool allowsMisalignedMemoryAccesses(
1459 EVT
, unsigned AddrSpace
= 0, unsigned Align
= 1,
1460 MachineMemOperand::Flags Flags
= MachineMemOperand::MONone
,
1461 bool * /*Fast*/ = nullptr) const {
1465 /// LLT handling variant.
1466 virtual bool allowsMisalignedMemoryAccesses(
1467 LLT
, unsigned AddrSpace
= 0, unsigned Align
= 1,
1468 MachineMemOperand::Flags Flags
= MachineMemOperand::MONone
,
1469 bool * /*Fast*/ = nullptr) const {
1473 /// Return true if the target supports a memory access of this type for the
1474 /// given address space and alignment. If the access is allowed, the optional
1475 /// final parameter returns if the access is also fast (as defined by the
1478 allowsMemoryAccess(LLVMContext
&Context
, const DataLayout
&DL
, EVT VT
,
1479 unsigned AddrSpace
= 0, unsigned Alignment
= 1,
1480 MachineMemOperand::Flags Flags
= MachineMemOperand::MONone
,
1481 bool *Fast
= nullptr) const;
1483 /// Return true if the target supports a memory access of this type for the
1484 /// given MachineMemOperand. If the access is allowed, the optional
1485 /// final parameter returns if the access is also fast (as defined by the
1487 bool allowsMemoryAccess(LLVMContext
&Context
, const DataLayout
&DL
, EVT VT
,
1488 const MachineMemOperand
&MMO
,
1489 bool *Fast
= nullptr) const;
1491 /// Returns the target specific optimal type for load and store operations as
1492 /// a result of memset, memcpy, and memmove lowering.
1494 /// If DstAlign is zero that means it's safe to destination alignment can
1495 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1496 /// a need to check it against alignment requirement, probably because the
1497 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1498 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1499 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1500 /// does not need to be loaded. It returns EVT::Other if the type should be
1501 /// determined using generic target-independent logic.
1503 getOptimalMemOpType(uint64_t /*Size*/, unsigned /*DstAlign*/,
1504 unsigned /*SrcAlign*/, bool /*IsMemset*/,
1505 bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1506 const AttributeList
& /*FuncAttributes*/) const {
1511 /// LLT returning variant.
1513 getOptimalMemOpLLT(uint64_t /*Size*/, unsigned /*DstAlign*/,
1514 unsigned /*SrcAlign*/, bool /*IsMemset*/,
1515 bool /*ZeroMemset*/, bool /*MemcpyStrSrc*/,
1516 const AttributeList
& /*FuncAttributes*/) const {
1520 /// Returns true if it's safe to use load / store of the specified type to
1521 /// expand memcpy / memset inline.
1523 /// This is mostly true for all types except for some special cases. For
1524 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1525 /// fstpl which also does type conversion. Note the specified type doesn't
1526 /// have to be legal as the hook is used before type legalization.
1527 virtual bool isSafeMemOpType(MVT
/*VT*/) const { return true; }
1529 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1530 bool usesUnderscoreSetJmp() const {
1531 return UseUnderscoreSetJmp
;
1534 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1535 bool usesUnderscoreLongJmp() const {
1536 return UseUnderscoreLongJmp
;
1539 /// Return lower limit for number of blocks in a jump table.
1540 virtual unsigned getMinimumJumpTableEntries() const;
1542 /// Return lower limit of the density in a jump table.
1543 unsigned getMinimumJumpTableDensity(bool OptForSize
) const;
1545 /// Return upper limit for number of entries in a jump table.
1546 /// Zero if no limit.
1547 unsigned getMaximumJumpTableSize() const;
1549 virtual bool isJumpTableRelative() const {
1550 return TM
.isPositionIndependent();
1553 /// If a physical register, this specifies the register that
1554 /// llvm.savestack/llvm.restorestack should save and restore.
1555 unsigned getStackPointerRegisterToSaveRestore() const {
1556 return StackPointerRegisterToSaveRestore
;
1559 /// If a physical register, this returns the register that receives the
1560 /// exception address on entry to an EH pad.
1562 getExceptionPointerRegister(const Constant
*PersonalityFn
) const {
1563 // 0 is guaranteed to be the NoRegister value on all targets
1567 /// If a physical register, this returns the register that receives the
1568 /// exception typeid on entry to a landing pad.
1570 getExceptionSelectorRegister(const Constant
*PersonalityFn
) const {
1571 // 0 is guaranteed to be the NoRegister value on all targets
1575 virtual bool needsFixedCatchObjects() const {
1576 report_fatal_error("Funclet EH is not implemented for this target");
1579 /// Return the minimum stack alignment of an argument.
1580 llvm::Align
getMinStackArgumentAlignment() const {
1581 return MinStackArgumentAlignment
;
1584 /// Return the minimum function alignment.
1585 llvm::Align
getMinFunctionAlignment() const { return MinFunctionAlignment
; }
1587 /// Return the preferred function alignment.
1588 llvm::Align
getPrefFunctionAlignment() const { return PrefFunctionAlignment
; }
1590 /// Return the preferred loop alignment.
1591 virtual llvm::Align
getPrefLoopAlignment(MachineLoop
*ML
= nullptr) const {
1592 return PrefLoopAlignment
;
1595 /// Should loops be aligned even when the function is marked OptSize (but not
1597 virtual bool alignLoopsWithOptSize() const {
1601 /// If the target has a standard location for the stack protector guard,
1602 /// returns the address of that location. Otherwise, returns nullptr.
1603 /// DEPRECATED: please override useLoadStackGuardNode and customize
1604 /// LOAD_STACK_GUARD, or customize \@llvm.stackguard().
1605 virtual Value
*getIRStackGuard(IRBuilder
<> &IRB
) const;
1607 /// Inserts necessary declarations for SSP (stack protection) purpose.
1608 /// Should be used only when getIRStackGuard returns nullptr.
1609 virtual void insertSSPDeclarations(Module
&M
) const;
1611 /// Return the variable that's previously inserted by insertSSPDeclarations,
1612 /// if any, otherwise return nullptr. Should be used only when
1613 /// getIRStackGuard returns nullptr.
1614 virtual Value
*getSDagStackGuard(const Module
&M
) const;
1616 /// If this function returns true, stack protection checks should XOR the
1617 /// frame pointer (or whichever pointer is used to address locals) into the
1618 /// stack guard value before checking it. getIRStackGuard must return nullptr
1619 /// if this returns true.
1620 virtual bool useStackGuardXorFP() const { return false; }
1622 /// If the target has a standard stack protection check function that
1623 /// performs validation and error handling, returns the function. Otherwise,
1624 /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1625 /// Should be used only when getIRStackGuard returns nullptr.
1626 virtual Function
*getSSPStackGuardCheck(const Module
&M
) const;
1629 Value
*getDefaultSafeStackPointerLocation(IRBuilder
<> &IRB
,
1633 /// Returns the target-specific address of the unsafe stack pointer.
1634 virtual Value
*getSafeStackPointerLocation(IRBuilder
<> &IRB
) const;
1636 /// Returns the name of the symbol used to emit stack probes or the empty
1637 /// string if not applicable.
1638 virtual StringRef
getStackProbeSymbolName(MachineFunction
&MF
) const {
1642 /// Returns true if a cast between SrcAS and DestAS is a noop.
1643 virtual bool isNoopAddrSpaceCast(unsigned SrcAS
, unsigned DestAS
) const {
1647 /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1648 /// are happy to sink it into basic blocks. A cast may be free, but not
1649 /// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
1650 virtual bool isFreeAddrSpaceCast(unsigned SrcAS
, unsigned DestAS
) const {
1651 return isNoopAddrSpaceCast(SrcAS
, DestAS
);
1654 /// Return true if the pointer arguments to CI should be aligned by aligning
1655 /// the object whose address is being passed. If so then MinSize is set to the
1656 /// minimum size the object must be to be aligned and PrefAlign is set to the
1657 /// preferred alignment.
1658 virtual bool shouldAlignPointerArgs(CallInst
* /*CI*/, unsigned & /*MinSize*/,
1659 unsigned & /*PrefAlign*/) const {
1663 //===--------------------------------------------------------------------===//
1664 /// \name Helpers for TargetTransformInfo implementations
1667 /// Get the ISD node that corresponds to the Instruction class opcode.
1668 int InstructionOpcodeToISD(unsigned Opcode
) const;
1670 /// Estimate the cost of type-legalization and the legalized type.
1671 std::pair
<int, MVT
> getTypeLegalizationCost(const DataLayout
&DL
,
1676 //===--------------------------------------------------------------------===//
1677 /// \name Helpers for atomic expansion.
1680 /// Returns the maximum atomic operation size (in bits) supported by
1681 /// the backend. Atomic operations greater than this size (as well
1682 /// as ones that are not naturally aligned), will be expanded by
1683 /// AtomicExpandPass into an __atomic_* library call.
1684 unsigned getMaxAtomicSizeInBitsSupported() const {
1685 return MaxAtomicSizeInBitsSupported
;
1688 /// Returns the size of the smallest cmpxchg or ll/sc instruction
1689 /// the backend supports. Any smaller operations are widened in
1690 /// AtomicExpandPass.
1692 /// Note that *unlike* operations above the maximum size, atomic ops
1693 /// are still natively supported below the minimum; they just
1694 /// require a more complex expansion.
1695 unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits
; }
1697 /// Whether the target supports unaligned atomic operations.
1698 bool supportsUnalignedAtomics() const { return SupportsUnalignedAtomics
; }
1700 /// Whether AtomicExpandPass should automatically insert fences and reduce
1701 /// ordering for this atomic. This should be true for most architectures with
1702 /// weak memory ordering. Defaults to false.
1703 virtual bool shouldInsertFencesForAtomic(const Instruction
*I
) const {
1707 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1708 /// corresponding pointee type. This may entail some non-trivial operations to
1709 /// truncate or reconstruct types that will be illegal in the backend. See
1710 /// ARMISelLowering for an example implementation.
1711 virtual Value
*emitLoadLinked(IRBuilder
<> &Builder
, Value
*Addr
,
1712 AtomicOrdering Ord
) const {
1713 llvm_unreachable("Load linked unimplemented on this target");
1716 /// Perform a store-conditional operation to Addr. Return the status of the
1717 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1718 virtual Value
*emitStoreConditional(IRBuilder
<> &Builder
, Value
*Val
,
1719 Value
*Addr
, AtomicOrdering Ord
) const {
1720 llvm_unreachable("Store conditional unimplemented on this target");
1723 /// Perform a masked atomicrmw using a target-specific intrinsic. This
1724 /// represents the core LL/SC loop which will be lowered at a late stage by
1726 virtual Value
*emitMaskedAtomicRMWIntrinsic(IRBuilder
<> &Builder
,
1728 Value
*AlignedAddr
, Value
*Incr
,
1729 Value
*Mask
, Value
*ShiftAmt
,
1730 AtomicOrdering Ord
) const {
1731 llvm_unreachable("Masked atomicrmw expansion unimplemented on this target");
1734 /// Perform a masked cmpxchg using a target-specific intrinsic. This
1735 /// represents the core LL/SC loop which will be lowered at a late stage by
1737 virtual Value
*emitMaskedAtomicCmpXchgIntrinsic(
1738 IRBuilder
<> &Builder
, AtomicCmpXchgInst
*CI
, Value
*AlignedAddr
,
1739 Value
*CmpVal
, Value
*NewVal
, Value
*Mask
, AtomicOrdering Ord
) const {
1740 llvm_unreachable("Masked cmpxchg expansion unimplemented on this target");
1743 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1744 /// It is called by AtomicExpandPass before expanding an
1745 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1746 /// if shouldInsertFencesForAtomic returns true.
1748 /// Inst is the original atomic instruction, prior to other expansions that
1749 /// may be performed.
1751 /// This function should either return a nullptr, or a pointer to an IR-level
1752 /// Instruction*. Even complex fence sequences can be represented by a
1753 /// single Instruction* through an intrinsic to be lowered later.
1754 /// Backends should override this method to produce target-specific intrinsic
1755 /// for their fences.
1756 /// FIXME: Please note that the default implementation here in terms of
1757 /// IR-level fences exists for historical/compatibility reasons and is
1758 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1759 /// consistency. For example, consider the following example:
1760 /// atomic<int> x = y = 0;
1761 /// int r1, r2, r3, r4;
1772 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1773 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1774 /// IR-level fences can prevent it.
1776 virtual Instruction
*emitLeadingFence(IRBuilder
<> &Builder
, Instruction
*Inst
,
1777 AtomicOrdering Ord
) const {
1778 if (isReleaseOrStronger(Ord
) && Inst
->hasAtomicStore())
1779 return Builder
.CreateFence(Ord
);
1784 virtual Instruction
*emitTrailingFence(IRBuilder
<> &Builder
,
1786 AtomicOrdering Ord
) const {
1787 if (isAcquireOrStronger(Ord
))
1788 return Builder
.CreateFence(Ord
);
1794 // Emits code that executes when the comparison result in the ll/sc
1795 // expansion of a cmpxchg instruction is such that the store-conditional will
1796 // not execute. This makes it possible to balance out the load-linked with
1797 // a dedicated instruction, if desired.
1798 // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1799 // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1800 virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder
<> &Builder
) const {}
1802 /// Returns true if the given (atomic) store should be expanded by the
1803 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1804 virtual bool shouldExpandAtomicStoreInIR(StoreInst
*SI
) const {
1808 /// Returns true if arguments should be sign-extended in lib calls.
1809 virtual bool shouldSignExtendTypeInLibCall(EVT Type
, bool IsSigned
) const {
1813 /// Returns true if arguments should be extended in lib calls.
1814 virtual bool shouldExtendTypeInLibCall(EVT Type
) const {
1818 /// Returns how the given (atomic) load should be expanded by the
1819 /// IR-level AtomicExpand pass.
1820 virtual AtomicExpansionKind
shouldExpandAtomicLoadInIR(LoadInst
*LI
) const {
1821 return AtomicExpansionKind::None
;
1824 /// Returns how the given atomic cmpxchg should be expanded by the IR-level
1825 /// AtomicExpand pass.
1826 virtual AtomicExpansionKind
1827 shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst
*AI
) const {
1828 return AtomicExpansionKind::None
;
1831 /// Returns how the IR-level AtomicExpand pass should expand the given
1832 /// AtomicRMW, if at all. Default is to never expand.
1833 virtual AtomicExpansionKind
shouldExpandAtomicRMWInIR(AtomicRMWInst
*RMW
) const {
1834 return RMW
->isFloatingPointOperation() ?
1835 AtomicExpansionKind::CmpXChg
: AtomicExpansionKind::None
;
1838 /// On some platforms, an AtomicRMW that never actually modifies the value
1839 /// (such as fetch_add of 0) can be turned into a fence followed by an
1840 /// atomic load. This may sound useless, but it makes it possible for the
1841 /// processor to keep the cacheline shared, dramatically improving
1842 /// performance. And such idempotent RMWs are useful for implementing some
1843 /// kinds of locks, see for example (justification + benchmarks):
1844 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1845 /// This method tries doing that transformation, returning the atomic load if
1846 /// it succeeds, and nullptr otherwise.
1847 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1848 /// another round of expansion.
1850 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst
*RMWI
) const {
1854 /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1855 /// SIGN_EXTEND, or ANY_EXTEND).
1856 virtual ISD::NodeType
getExtendForAtomicOps() const {
1857 return ISD::ZERO_EXTEND
;
1862 /// Returns true if we should normalize
1863 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1864 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1865 /// that it saves us from materializing N0 and N1 in an integer register.
1866 /// Targets that are able to perform and/or on flags should return false here.
1867 virtual bool shouldNormalizeToSelectSequence(LLVMContext
&Context
,
1869 // If a target has multiple condition registers, then it likely has logical
1870 // operations on those registers.
1871 if (hasMultipleConditionRegisters())
1873 // Only do the transform if the value won't be split into multiple
1875 LegalizeTypeAction Action
= getTypeAction(Context
, VT
);
1876 return Action
!= TypeExpandInteger
&& Action
!= TypeExpandFloat
&&
1877 Action
!= TypeSplitVector
;
1880 virtual bool isProfitableToCombineMinNumMaxNum(EVT VT
) const { return true; }
1882 /// Return true if a select of constants (select Cond, C1, C2) should be
1883 /// transformed into simple math ops with the condition value. For example:
1884 /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1885 virtual bool convertSelectOfConstantsToMath(EVT VT
) const {
1889 /// Return true if it is profitable to transform an integer
1890 /// multiplication-by-constant into simpler operations like shifts and adds.
1891 /// This may be true if the target does not directly support the
1892 /// multiplication operation for the specified type or the sequence of simpler
1893 /// ops is faster than the multiply.
1894 virtual bool decomposeMulByConstant(LLVMContext
&Context
,
1895 EVT VT
, SDValue C
) const {
1899 /// Return true if it is more correct/profitable to use strict FP_TO_INT
1900 /// conversion operations - canonicalizing the FP source value instead of
1901 /// converting all cases and then selecting based on value.
1902 /// This may be true if the target throws exceptions for out of bounds
1903 /// conversions or has fast FP CMOV.
1904 virtual bool shouldUseStrictFP_TO_INT(EVT FpVT
, EVT IntVT
,
1905 bool IsSigned
) const {
1909 //===--------------------------------------------------------------------===//
1910 // TargetLowering Configuration Methods - These methods should be invoked by
1911 // the derived class constructor to configure this object for the target.
1914 /// Specify how the target extends the result of integer and floating point
1915 /// boolean values from i1 to a wider type. See getBooleanContents.
1916 void setBooleanContents(BooleanContent Ty
) {
1917 BooleanContents
= Ty
;
1918 BooleanFloatContents
= Ty
;
1921 /// Specify how the target extends the result of integer and floating point
1922 /// boolean values from i1 to a wider type. See getBooleanContents.
1923 void setBooleanContents(BooleanContent IntTy
, BooleanContent FloatTy
) {
1924 BooleanContents
= IntTy
;
1925 BooleanFloatContents
= FloatTy
;
1928 /// Specify how the target extends the result of a vector boolean value from a
1929 /// vector of i1 to a wider type. See getBooleanContents.
1930 void setBooleanVectorContents(BooleanContent Ty
) {
1931 BooleanVectorContents
= Ty
;
1934 /// Specify the target scheduling preference.
1935 void setSchedulingPreference(Sched::Preference Pref
) {
1936 SchedPreferenceInfo
= Pref
;
1939 /// Indicate whether this target prefers to use _setjmp to implement
1940 /// llvm.setjmp or the version without _. Defaults to false.
1941 void setUseUnderscoreSetJmp(bool Val
) {
1942 UseUnderscoreSetJmp
= Val
;
1945 /// Indicate whether this target prefers to use _longjmp to implement
1946 /// llvm.longjmp or the version without _. Defaults to false.
1947 void setUseUnderscoreLongJmp(bool Val
) {
1948 UseUnderscoreLongJmp
= Val
;
1951 /// Indicate the minimum number of blocks to generate jump tables.
1952 void setMinimumJumpTableEntries(unsigned Val
);
1954 /// Indicate the maximum number of entries in jump tables.
1955 /// Set to zero to generate unlimited jump tables.
1956 void setMaximumJumpTableSize(unsigned);
1958 /// If set to a physical register, this specifies the register that
1959 /// llvm.savestack/llvm.restorestack should save and restore.
1960 void setStackPointerRegisterToSaveRestore(unsigned R
) {
1961 StackPointerRegisterToSaveRestore
= R
;
1964 /// Tells the code generator that the target has multiple (allocatable)
1965 /// condition registers that can be used to store the results of comparisons
1966 /// for use by selects and conditional branches. With multiple condition
1967 /// registers, the code generator will not aggressively sink comparisons into
1968 /// the blocks of their users.
1969 void setHasMultipleConditionRegisters(bool hasManyRegs
= true) {
1970 HasMultipleConditionRegisters
= hasManyRegs
;
1973 /// Tells the code generator that the target has BitExtract instructions.
1974 /// The code generator will aggressively sink "shift"s into the blocks of
1975 /// their users if the users will generate "and" instructions which can be
1976 /// combined with "shift" to BitExtract instructions.
1977 void setHasExtractBitsInsn(bool hasExtractInsn
= true) {
1978 HasExtractBitsInsn
= hasExtractInsn
;
1981 /// Tells the code generator not to expand logic operations on comparison
1982 /// predicates into separate sequences that increase the amount of flow
1984 void setJumpIsExpensive(bool isExpensive
= true);
1986 /// Tells the code generator which bitwidths to bypass.
1987 void addBypassSlowDiv(unsigned int SlowBitWidth
, unsigned int FastBitWidth
) {
1988 BypassSlowDivWidths
[SlowBitWidth
] = FastBitWidth
;
1991 /// Add the specified register class as an available regclass for the
1992 /// specified value type. This indicates the selector can handle values of
1993 /// that class natively.
1994 void addRegisterClass(MVT VT
, const TargetRegisterClass
*RC
) {
1995 assert((unsigned)VT
.SimpleTy
< array_lengthof(RegClassForVT
));
1996 RegClassForVT
[VT
.SimpleTy
] = RC
;
1999 /// Return the largest legal super-reg register class of the register class
2000 /// for the specified type and its associated "cost".
2001 virtual std::pair
<const TargetRegisterClass
*, uint8_t>
2002 findRepresentativeClass(const TargetRegisterInfo
*TRI
, MVT VT
) const;
2004 /// Once all of the register classes are added, this allows us to compute
2005 /// derived properties we expose.
2006 void computeRegisterProperties(const TargetRegisterInfo
*TRI
);
2008 /// Indicate that the specified operation does not work with the specified
2009 /// type and indicate what to do about it. Note that VT may refer to either
2010 /// the type of a result or that of an operand of Op.
2011 void setOperationAction(unsigned Op
, MVT VT
,
2012 LegalizeAction Action
) {
2013 assert(Op
< array_lengthof(OpActions
[0]) && "Table isn't big enough!");
2014 OpActions
[(unsigned)VT
.SimpleTy
][Op
] = Action
;
2017 /// Indicate that the specified load with extension does not work with the
2018 /// specified type and indicate what to do about it.
2019 void setLoadExtAction(unsigned ExtType
, MVT ValVT
, MVT MemVT
,
2020 LegalizeAction Action
) {
2021 assert(ExtType
< ISD::LAST_LOADEXT_TYPE
&& ValVT
.isValid() &&
2022 MemVT
.isValid() && "Table isn't big enough!");
2023 assert((unsigned)Action
< 0x10 && "too many bits for bitfield array");
2024 unsigned Shift
= 4 * ExtType
;
2025 LoadExtActions
[ValVT
.SimpleTy
][MemVT
.SimpleTy
] &= ~((uint16_t)0xF << Shift
);
2026 LoadExtActions
[ValVT
.SimpleTy
][MemVT
.SimpleTy
] |= (uint16_t)Action
<< Shift
;
2029 /// Indicate that the specified truncating store does not work with the
2030 /// specified type and indicate what to do about it.
2031 void setTruncStoreAction(MVT ValVT
, MVT MemVT
,
2032 LegalizeAction Action
) {
2033 assert(ValVT
.isValid() && MemVT
.isValid() && "Table isn't big enough!");
2034 TruncStoreActions
[(unsigned)ValVT
.SimpleTy
][MemVT
.SimpleTy
] = Action
;
2037 /// Indicate that the specified indexed load does or does not work with the
2038 /// specified type and indicate what to do abort it.
2040 /// NOTE: All indexed mode loads are initialized to Expand in
2041 /// TargetLowering.cpp
2042 void setIndexedLoadAction(unsigned IdxMode
, MVT VT
,
2043 LegalizeAction Action
) {
2044 assert(VT
.isValid() && IdxMode
< ISD::LAST_INDEXED_MODE
&&
2045 (unsigned)Action
< 0xf && "Table isn't big enough!");
2046 // Load action are kept in the upper half.
2047 IndexedModeActions
[(unsigned)VT
.SimpleTy
][IdxMode
] &= ~0xf0;
2048 IndexedModeActions
[(unsigned)VT
.SimpleTy
][IdxMode
] |= ((uint8_t)Action
) <<4;
2051 /// Indicate that the specified indexed store does or does not work with the
2052 /// specified type and indicate what to do about it.
2054 /// NOTE: All indexed mode stores are initialized to Expand in
2055 /// TargetLowering.cpp
2056 void setIndexedStoreAction(unsigned IdxMode
, MVT VT
,
2057 LegalizeAction Action
) {
2058 assert(VT
.isValid() && IdxMode
< ISD::LAST_INDEXED_MODE
&&
2059 (unsigned)Action
< 0xf && "Table isn't big enough!");
2060 // Store action are kept in the lower half.
2061 IndexedModeActions
[(unsigned)VT
.SimpleTy
][IdxMode
] &= ~0x0f;
2062 IndexedModeActions
[(unsigned)VT
.SimpleTy
][IdxMode
] |= ((uint8_t)Action
);
2065 /// Indicate that the specified condition code is or isn't supported on the
2066 /// target and indicate what to do about it.
2067 void setCondCodeAction(ISD::CondCode CC
, MVT VT
,
2068 LegalizeAction Action
) {
2069 assert(VT
.isValid() && (unsigned)CC
< array_lengthof(CondCodeActions
) &&
2070 "Table isn't big enough!");
2071 assert((unsigned)Action
< 0x10 && "too many bits for bitfield array");
2072 /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
2073 /// value and the upper 29 bits index into the second dimension of the array
2074 /// to select what 32-bit value to use.
2075 uint32_t Shift
= 4 * (VT
.SimpleTy
& 0x7);
2076 CondCodeActions
[CC
][VT
.SimpleTy
>> 3] &= ~((uint32_t)0xF << Shift
);
2077 CondCodeActions
[CC
][VT
.SimpleTy
>> 3] |= (uint32_t)Action
<< Shift
;
2080 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
2081 /// to trying a larger integer/fp until it can find one that works. If that
2082 /// default is insufficient, this method can be used by the target to override
2084 void AddPromotedToType(unsigned Opc
, MVT OrigVT
, MVT DestVT
) {
2085 PromoteToType
[std::make_pair(Opc
, OrigVT
.SimpleTy
)] = DestVT
.SimpleTy
;
2088 /// Convenience method to set an operation to Promote and specify the type
2089 /// in a single call.
2090 void setOperationPromotedToType(unsigned Opc
, MVT OrigVT
, MVT DestVT
) {
2091 setOperationAction(Opc
, OrigVT
, Promote
);
2092 AddPromotedToType(Opc
, OrigVT
, DestVT
);
2095 /// Targets should invoke this method for each target independent node that
2096 /// they want to provide a custom DAG combiner for by implementing the
2097 /// PerformDAGCombine virtual method.
2098 void setTargetDAGCombine(ISD::NodeType NT
) {
2099 assert(unsigned(NT
>> 3) < array_lengthof(TargetDAGCombineArray
));
2100 TargetDAGCombineArray
[NT
>> 3] |= 1 << (NT
&7);
2103 /// Set the target's minimum function alignment.
2104 void setMinFunctionAlignment(llvm::Align Align
) {
2105 MinFunctionAlignment
= Align
;
2108 /// Set the target's preferred function alignment. This should be set if
2109 /// there is a performance benefit to higher-than-minimum alignment
2110 void setPrefFunctionAlignment(llvm::Align Align
) {
2111 PrefFunctionAlignment
= Align
;
2114 /// Set the target's preferred loop alignment. Default alignment is one, it
2115 /// means the target does not care about loop alignment. The target may also
2116 /// override getPrefLoopAlignment to provide per-loop values.
2117 void setPrefLoopAlignment(llvm::Align Align
) { PrefLoopAlignment
= Align
; }
2119 /// Set the minimum stack alignment of an argument.
2120 void setMinStackArgumentAlignment(llvm::Align Align
) {
2121 MinStackArgumentAlignment
= Align
;
2124 /// Set the maximum atomic operation size supported by the
2125 /// backend. Atomic operations greater than this size (as well as
2126 /// ones that are not naturally aligned), will be expanded by
2127 /// AtomicExpandPass into an __atomic_* library call.
2128 void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits
) {
2129 MaxAtomicSizeInBitsSupported
= SizeInBits
;
2132 /// Sets the minimum cmpxchg or ll/sc size supported by the backend.
2133 void setMinCmpXchgSizeInBits(unsigned SizeInBits
) {
2134 MinCmpXchgSizeInBits
= SizeInBits
;
2137 /// Sets whether unaligned atomic operations are supported.
2138 void setSupportsUnalignedAtomics(bool UnalignedSupported
) {
2139 SupportsUnalignedAtomics
= UnalignedSupported
;
2143 //===--------------------------------------------------------------------===//
2144 // Addressing mode description hooks (used by LSR etc).
2147 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
2148 /// instructions reading the address. This allows as much computation as
2149 /// possible to be done in the address mode for that operand. This hook lets
2150 /// targets also pass back when this should be done on intrinsics which
2152 virtual bool getAddrModeArguments(IntrinsicInst
* /*I*/,
2153 SmallVectorImpl
<Value
*> &/*Ops*/,
2154 Type
*&/*AccessTy*/) const {
2158 /// This represents an addressing mode of:
2159 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
2160 /// If BaseGV is null, there is no BaseGV.
2161 /// If BaseOffs is zero, there is no base offset.
2162 /// If HasBaseReg is false, there is no base register.
2163 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
2166 GlobalValue
*BaseGV
= nullptr;
2167 int64_t BaseOffs
= 0;
2168 bool HasBaseReg
= false;
2170 AddrMode() = default;
2173 /// Return true if the addressing mode represented by AM is legal for this
2174 /// target, for a load/store of the specified type.
2176 /// The type may be VoidTy, in which case only return true if the addressing
2177 /// mode is legal for a load/store of any legal type. TODO: Handle
2178 /// pre/postinc as well.
2180 /// If the address space cannot be determined, it will be -1.
2182 /// TODO: Remove default argument
2183 virtual bool isLegalAddressingMode(const DataLayout
&DL
, const AddrMode
&AM
,
2184 Type
*Ty
, unsigned AddrSpace
,
2185 Instruction
*I
= nullptr) const;
2187 /// Return the cost of the scaling factor used in the addressing mode
2188 /// represented by AM for this target, for a load/store of the specified type.
2190 /// If the AM is supported, the return value must be >= 0.
2191 /// If the AM is not supported, it returns a negative value.
2192 /// TODO: Handle pre/postinc as well.
2193 /// TODO: Remove default argument
2194 virtual int getScalingFactorCost(const DataLayout
&DL
, const AddrMode
&AM
,
2195 Type
*Ty
, unsigned AS
= 0) const {
2196 // Default: assume that any scaling factor used in a legal AM is free.
2197 if (isLegalAddressingMode(DL
, AM
, Ty
, AS
))
2202 /// Return true if the specified immediate is legal icmp immediate, that is
2203 /// the target has icmp instructions which can compare a register against the
2204 /// immediate without having to materialize the immediate into a register.
2205 virtual bool isLegalICmpImmediate(int64_t) const {
2209 /// Return true if the specified immediate is legal add immediate, that is the
2210 /// target has add instructions which can add a register with the immediate
2211 /// without having to materialize the immediate into a register.
2212 virtual bool isLegalAddImmediate(int64_t) const {
2216 /// Return true if the specified immediate is legal for the value input of a
2217 /// store instruction.
2218 virtual bool isLegalStoreImmediate(int64_t Value
) const {
2219 // Default implementation assumes that at least 0 works since it is likely
2220 // that a zero register exists or a zero immediate is allowed.
2224 /// Return true if it's significantly cheaper to shift a vector by a uniform
2225 /// scalar than by an amount which will vary across each lane. On x86, for
2226 /// example, there is a "psllw" instruction for the former case, but no simple
2227 /// instruction for a general "a << b" operation on vectors.
2228 virtual bool isVectorShiftByScalarCheap(Type
*Ty
) const {
2232 /// Returns true if the opcode is a commutative binary operation.
2233 virtual bool isCommutativeBinOp(unsigned Opcode
) const {
2234 // FIXME: This should get its info from the td file.
2244 case ISD::SMUL_LOHI
:
2245 case ISD::UMUL_LOHI
:
2259 case ISD::FMINNUM_IEEE
:
2260 case ISD::FMAXNUM_IEEE
:
2264 default: return false;
2268 /// Return true if the node is a math/logic binary operator.
2269 virtual bool isBinOp(unsigned Opcode
) const {
2270 // A commutative binop must be a binop.
2271 if (isCommutativeBinOp(Opcode
))
2273 // These are non-commutative binops.
2292 /// Return true if it's free to truncate a value of type FromTy to type
2293 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
2294 /// by referencing its sub-register AX.
2295 /// Targets must return false when FromTy <= ToTy.
2296 virtual bool isTruncateFree(Type
*FromTy
, Type
*ToTy
) const {
2300 /// Return true if a truncation from FromTy to ToTy is permitted when deciding
2301 /// whether a call is in tail position. Typically this means that both results
2302 /// would be assigned to the same register or stack slot, but it could mean
2303 /// the target performs adequate checks of its own before proceeding with the
2304 /// tail call. Targets must return false when FromTy <= ToTy.
2305 virtual bool allowTruncateForTailCall(Type
*FromTy
, Type
*ToTy
) const {
2309 virtual bool isTruncateFree(EVT FromVT
, EVT ToVT
) const {
2313 virtual bool isProfitableToHoist(Instruction
*I
) const { return true; }
2315 /// Return true if the extension represented by \p I is free.
2316 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
2317 /// this method can use the context provided by \p I to decide
2318 /// whether or not \p I is free.
2319 /// This method extends the behavior of the is[Z|FP]ExtFree family.
2320 /// In other words, if is[Z|FP]Free returns true, then this method
2321 /// returns true as well. The converse is not true.
2322 /// The target can perform the adequate checks by overriding isExtFreeImpl.
2323 /// \pre \p I must be a sign, zero, or fp extension.
2324 bool isExtFree(const Instruction
*I
) const {
2325 switch (I
->getOpcode()) {
2326 case Instruction::FPExt
:
2327 if (isFPExtFree(EVT::getEVT(I
->getType()),
2328 EVT::getEVT(I
->getOperand(0)->getType())))
2331 case Instruction::ZExt
:
2332 if (isZExtFree(I
->getOperand(0)->getType(), I
->getType()))
2335 case Instruction::SExt
:
2338 llvm_unreachable("Instruction is not an extension");
2340 return isExtFreeImpl(I
);
2343 /// Return true if \p Load and \p Ext can form an ExtLoad.
2344 /// For example, in AArch64
2345 /// %L = load i8, i8* %ptr
2346 /// %E = zext i8 %L to i32
2347 /// can be lowered into one load instruction
2349 bool isExtLoad(const LoadInst
*Load
, const Instruction
*Ext
,
2350 const DataLayout
&DL
) const {
2351 EVT VT
= getValueType(DL
, Ext
->getType());
2352 EVT LoadVT
= getValueType(DL
, Load
->getType());
2354 // If the load has other users and the truncate is not free, the ext
2355 // probably isn't free.
2356 if (!Load
->hasOneUse() && (isTypeLegal(LoadVT
) || !isTypeLegal(VT
)) &&
2357 !isTruncateFree(Ext
->getType(), Load
->getType()))
2360 // Check whether the target supports casts folded into loads.
2362 if (isa
<ZExtInst
>(Ext
))
2363 LType
= ISD::ZEXTLOAD
;
2365 assert(isa
<SExtInst
>(Ext
) && "Unexpected ext type!");
2366 LType
= ISD::SEXTLOAD
;
2369 return isLoadExtLegal(LType
, VT
, LoadVT
);
2372 /// Return true if any actual instruction that defines a value of type FromTy
2373 /// implicitly zero-extends the value to ToTy in the result register.
2375 /// The function should return true when it is likely that the truncate can
2376 /// be freely folded with an instruction defining a value of FromTy. If
2377 /// the defining instruction is unknown (because you're looking at a
2378 /// function argument, PHI, etc.) then the target may require an
2379 /// explicit truncate, which is not necessarily free, but this function
2380 /// does not deal with those cases.
2381 /// Targets must return false when FromTy >= ToTy.
2382 virtual bool isZExtFree(Type
*FromTy
, Type
*ToTy
) const {
2386 virtual bool isZExtFree(EVT FromTy
, EVT ToTy
) const {
2390 /// Return true if sign-extension from FromTy to ToTy is cheaper than
2392 virtual bool isSExtCheaperThanZExt(EVT FromTy
, EVT ToTy
) const {
2396 /// Return true if sinking I's operands to the same basic block as I is
2397 /// profitable, e.g. because the operands can be folded into a target
2398 /// instruction during instruction selection. After calling the function
2399 /// \p Ops contains the Uses to sink ordered by dominance (dominating users
2401 virtual bool shouldSinkOperands(Instruction
*I
,
2402 SmallVectorImpl
<Use
*> &Ops
) const {
2406 /// Return true if the target supplies and combines to a paired load
2407 /// two loaded values of type LoadedType next to each other in memory.
2408 /// RequiredAlignment gives the minimal alignment constraints that must be met
2409 /// to be able to select this paired load.
2411 /// This information is *not* used to generate actual paired loads, but it is
2412 /// used to generate a sequence of loads that is easier to combine into a
2414 /// For instance, something like this:
2415 /// a = load i64* addr
2416 /// b = trunc i64 a to i32
2417 /// c = lshr i64 a, 32
2418 /// d = trunc i64 c to i32
2419 /// will be optimized into:
2420 /// b = load i32* addr1
2421 /// d = load i32* addr2
2422 /// Where addr1 = addr2 +/- sizeof(i32).
2424 /// In other words, unless the target performs a post-isel load combining,
2425 /// this information should not be provided because it will generate more
2427 virtual bool hasPairedLoad(EVT
/*LoadedType*/,
2428 unsigned & /*RequiredAlignment*/) const {
2432 /// Return true if the target has a vector blend instruction.
2433 virtual bool hasVectorBlend() const { return false; }
2435 /// Get the maximum supported factor for interleaved memory accesses.
2436 /// Default to be the minimum interleave factor: 2.
2437 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2439 /// Lower an interleaved load to target specific intrinsics. Return
2440 /// true on success.
2442 /// \p LI is the vector load instruction.
2443 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2444 /// \p Indices is the corresponding indices for each shufflevector.
2445 /// \p Factor is the interleave factor.
2446 virtual bool lowerInterleavedLoad(LoadInst
*LI
,
2447 ArrayRef
<ShuffleVectorInst
*> Shuffles
,
2448 ArrayRef
<unsigned> Indices
,
2449 unsigned Factor
) const {
2453 /// Lower an interleaved store to target specific intrinsics. Return
2454 /// true on success.
2456 /// \p SI is the vector store instruction.
2457 /// \p SVI is the shufflevector to RE-interleave the stored vector.
2458 /// \p Factor is the interleave factor.
2459 virtual bool lowerInterleavedStore(StoreInst
*SI
, ShuffleVectorInst
*SVI
,
2460 unsigned Factor
) const {
2464 /// Return true if zero-extending the specific node Val to type VT2 is free
2465 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2466 /// because it's folded such as X86 zero-extending loads).
2467 virtual bool isZExtFree(SDValue Val
, EVT VT2
) const {
2468 return isZExtFree(Val
.getValueType(), VT2
);
2471 /// Return true if an fpext operation is free (for instance, because
2472 /// single-precision floating-point numbers are implicitly extended to
2473 /// double-precision).
2474 virtual bool isFPExtFree(EVT DestVT
, EVT SrcVT
) const {
2475 assert(SrcVT
.isFloatingPoint() && DestVT
.isFloatingPoint() &&
2476 "invalid fpext types");
2480 /// Return true if an fpext operation input to an \p Opcode operation is free
2481 /// (for instance, because half-precision floating-point numbers are
2482 /// implicitly extended to float-precision) for an FMA instruction.
2483 virtual bool isFPExtFoldable(unsigned Opcode
, EVT DestVT
, EVT SrcVT
) const {
2484 assert(DestVT
.isFloatingPoint() && SrcVT
.isFloatingPoint() &&
2485 "invalid fpext types");
2486 return isFPExtFree(DestVT
, SrcVT
);
2489 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2490 /// extend node) is profitable.
2491 virtual bool isVectorLoadExtDesirable(SDValue ExtVal
) const { return false; }
2493 /// Return true if an fneg operation is free to the point where it is never
2494 /// worthwhile to replace it with a bitwise operation.
2495 virtual bool isFNegFree(EVT VT
) const {
2496 assert(VT
.isFloatingPoint());
2500 /// Return true if an fabs operation is free to the point where it is never
2501 /// worthwhile to replace it with a bitwise operation.
2502 virtual bool isFAbsFree(EVT VT
) const {
2503 assert(VT
.isFloatingPoint());
2507 /// Return true if an FMA operation is faster than a pair of fmul and fadd
2508 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2509 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2511 /// NOTE: This may be called before legalization on types for which FMAs are
2512 /// not legal, but should return true if those types will eventually legalize
2513 /// to types that support FMAs. After legalization, it will only be called on
2514 /// types that support FMAs (via Legal or Custom actions)
2515 virtual bool isFMAFasterThanFMulAndFAdd(EVT
) const {
2519 /// Return true if it's profitable to narrow operations of type VT1 to
2520 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2522 virtual bool isNarrowingProfitable(EVT
/*VT1*/, EVT
/*VT2*/) const {
2526 /// Return true if it is beneficial to convert a load of a constant to
2527 /// just the constant itself.
2528 /// On some targets it might be more efficient to use a combination of
2529 /// arithmetic instructions to materialize the constant instead of loading it
2530 /// from a constant pool.
2531 virtual bool shouldConvertConstantLoadToIntImm(const APInt
&Imm
,
2536 /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2537 /// from this source type with this index. This is needed because
2538 /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2539 /// the first element, and only the target knows which lowering is cheap.
2540 virtual bool isExtractSubvectorCheap(EVT ResVT
, EVT SrcVT
,
2541 unsigned Index
) const {
2545 /// Try to convert an extract element of a vector binary operation into an
2546 /// extract element followed by a scalar operation.
2547 virtual bool shouldScalarizeBinop(SDValue VecOp
) const {
2551 /// Return true if extraction of a scalar element from the given vector type
2552 /// at the given index is cheap. For example, if scalar operations occur on
2553 /// the same register file as vector operations, then an extract element may
2554 /// be a sub-register rename rather than an actual instruction.
2555 virtual bool isExtractVecEltCheap(EVT VT
, unsigned Index
) const {
2559 /// Try to convert math with an overflow comparison into the corresponding DAG
2560 /// node operation. Targets may want to override this independently of whether
2561 /// the operation is legal/custom for the given type because it may obscure
2562 /// matching of other patterns.
2563 virtual bool shouldFormOverflowOp(unsigned Opcode
, EVT VT
) const {
2564 // TODO: The default logic is inherited from code in CodeGenPrepare.
2565 // The opcode should not make a difference by default?
2566 if (Opcode
!= ISD::UADDO
)
2569 // Allow the transform as long as we have an integer type that is not
2570 // obviously illegal and unsupported.
2573 return VT
.isSimple() || !isOperationExpand(Opcode
, VT
);
2576 // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2577 // even if the vector itself has multiple uses.
2578 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT
) const {
2582 // Return true if CodeGenPrepare should consider splitting large offset of a
2583 // GEP to make the GEP fit into the addressing mode and can be sunk into the
2584 // same blocks of its users.
2585 virtual bool shouldConsiderGEPOffsetSplit() const { return false; }
2587 //===--------------------------------------------------------------------===//
2588 // Runtime Library hooks
2591 /// Rename the default libcall routine name for the specified libcall.
2592 void setLibcallName(RTLIB::Libcall Call
, const char *Name
) {
2593 LibcallRoutineNames
[Call
] = Name
;
2596 /// Get the libcall routine name for the specified libcall.
2597 const char *getLibcallName(RTLIB::Libcall Call
) const {
2598 return LibcallRoutineNames
[Call
];
2601 /// Override the default CondCode to be used to test the result of the
2602 /// comparison libcall against zero.
2603 void setCmpLibcallCC(RTLIB::Libcall Call
, ISD::CondCode CC
) {
2604 CmpLibcallCCs
[Call
] = CC
;
2607 /// Get the CondCode that's to be used to test the result of the comparison
2608 /// libcall against zero.
2609 ISD::CondCode
getCmpLibcallCC(RTLIB::Libcall Call
) const {
2610 return CmpLibcallCCs
[Call
];
2613 /// Set the CallingConv that should be used for the specified libcall.
2614 void setLibcallCallingConv(RTLIB::Libcall Call
, CallingConv::ID CC
) {
2615 LibcallCallingConvs
[Call
] = CC
;
2618 /// Get the CallingConv that should be used for the specified libcall.
2619 CallingConv::ID
getLibcallCallingConv(RTLIB::Libcall Call
) const {
2620 return LibcallCallingConvs
[Call
];
2623 /// Execute target specific actions to finalize target lowering.
2624 /// This is used to set extra flags in MachineFrameInformation and freezing
2625 /// the set of reserved registers.
2626 /// The default implementation just freezes the set of reserved registers.
2627 virtual void finalizeLowering(MachineFunction
&MF
) const;
2630 const TargetMachine
&TM
;
2632 /// Tells the code generator that the target has multiple (allocatable)
2633 /// condition registers that can be used to store the results of comparisons
2634 /// for use by selects and conditional branches. With multiple condition
2635 /// registers, the code generator will not aggressively sink comparisons into
2636 /// the blocks of their users.
2637 bool HasMultipleConditionRegisters
;
2639 /// Tells the code generator that the target has BitExtract instructions.
2640 /// The code generator will aggressively sink "shift"s into the blocks of
2641 /// their users if the users will generate "and" instructions which can be
2642 /// combined with "shift" to BitExtract instructions.
2643 bool HasExtractBitsInsn
;
2645 /// Tells the code generator to bypass slow divide or remainder
2646 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2647 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2648 /// div/rem when the operands are positive and less than 256.
2649 DenseMap
<unsigned int, unsigned int> BypassSlowDivWidths
;
2651 /// Tells the code generator that it shouldn't generate extra flow control
2652 /// instructions and should attempt to combine flow control instructions via
2654 bool JumpIsExpensive
;
2656 /// This target prefers to use _setjmp to implement llvm.setjmp.
2658 /// Defaults to false.
2659 bool UseUnderscoreSetJmp
;
2661 /// This target prefers to use _longjmp to implement llvm.longjmp.
2663 /// Defaults to false.
2664 bool UseUnderscoreLongJmp
;
2666 /// Information about the contents of the high-bits in boolean values held in
2667 /// a type wider than i1. See getBooleanContents.
2668 BooleanContent BooleanContents
;
2670 /// Information about the contents of the high-bits in boolean values held in
2671 /// a type wider than i1. See getBooleanContents.
2672 BooleanContent BooleanFloatContents
;
2674 /// Information about the contents of the high-bits in boolean vector values
2675 /// when the element type is wider than i1. See getBooleanContents.
2676 BooleanContent BooleanVectorContents
;
2678 /// The target scheduling preference: shortest possible total cycles or lowest
2680 Sched::Preference SchedPreferenceInfo
;
2682 /// The minimum alignment that any argument on the stack needs to have.
2683 llvm::Align MinStackArgumentAlignment
;
2685 /// The minimum function alignment (used when optimizing for size, and to
2686 /// prevent explicitly provided alignment from leading to incorrect code).
2687 llvm::Align MinFunctionAlignment
;
2689 /// The preferred function alignment (used when alignment unspecified and
2690 /// optimizing for speed).
2691 llvm::Align PrefFunctionAlignment
;
2693 /// The preferred loop alignment (in log2 bot in bytes).
2694 llvm::Align PrefLoopAlignment
;
2696 /// Size in bits of the maximum atomics size the backend supports.
2697 /// Accesses larger than this will be expanded by AtomicExpandPass.
2698 unsigned MaxAtomicSizeInBitsSupported
;
2700 /// Size in bits of the minimum cmpxchg or ll/sc operation the
2701 /// backend supports.
2702 unsigned MinCmpXchgSizeInBits
;
2704 /// This indicates if the target supports unaligned atomic operations.
2705 bool SupportsUnalignedAtomics
;
2707 /// If set to a physical register, this specifies the register that
2708 /// llvm.savestack/llvm.restorestack should save and restore.
2709 unsigned StackPointerRegisterToSaveRestore
;
2711 /// This indicates the default register class to use for each ValueType the
2712 /// target supports natively.
2713 const TargetRegisterClass
*RegClassForVT
[MVT::LAST_VALUETYPE
];
2714 unsigned char NumRegistersForVT
[MVT::LAST_VALUETYPE
];
2715 MVT RegisterTypeForVT
[MVT::LAST_VALUETYPE
];
2717 /// This indicates the "representative" register class to use for each
2718 /// ValueType the target supports natively. This information is used by the
2719 /// scheduler to track register pressure. By default, the representative
2720 /// register class is the largest legal super-reg register class of the
2721 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2722 /// representative class would be GR32.
2723 const TargetRegisterClass
*RepRegClassForVT
[MVT::LAST_VALUETYPE
];
2725 /// This indicates the "cost" of the "representative" register class for each
2726 /// ValueType. The cost is used by the scheduler to approximate register
2728 uint8_t RepRegClassCostForVT
[MVT::LAST_VALUETYPE
];
2730 /// For any value types we are promoting or expanding, this contains the value
2731 /// type that we are changing to. For Expanded types, this contains one step
2732 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2733 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2734 /// the same type (e.g. i32 -> i32).
2735 MVT TransformToType
[MVT::LAST_VALUETYPE
];
2737 /// For each operation and each value type, keep a LegalizeAction that
2738 /// indicates how instruction selection should deal with the operation. Most
2739 /// operations are Legal (aka, supported natively by the target), but
2740 /// operations that are not should be described. Note that operations on
2741 /// non-legal value types are not described here.
2742 LegalizeAction OpActions
[MVT::LAST_VALUETYPE
][ISD::BUILTIN_OP_END
];
2744 /// For each load extension type and each value type, keep a LegalizeAction
2745 /// that indicates how instruction selection should deal with a load of a
2746 /// specific value type and extension type. Uses 4-bits to store the action
2747 /// for each of the 4 load ext types.
2748 uint16_t LoadExtActions
[MVT::LAST_VALUETYPE
][MVT::LAST_VALUETYPE
];
2750 /// For each value type pair keep a LegalizeAction that indicates whether a
2751 /// truncating store of a specific value type and truncating type is legal.
2752 LegalizeAction TruncStoreActions
[MVT::LAST_VALUETYPE
][MVT::LAST_VALUETYPE
];
2754 /// For each indexed mode and each value type, keep a pair of LegalizeAction
2755 /// that indicates how instruction selection should deal with the load /
2758 /// The first dimension is the value_type for the reference. The second
2759 /// dimension represents the various modes for load store.
2760 uint8_t IndexedModeActions
[MVT::LAST_VALUETYPE
][ISD::LAST_INDEXED_MODE
];
2762 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2763 /// indicates how instruction selection should deal with the condition code.
2765 /// Because each CC action takes up 4 bits, we need to have the array size be
2766 /// large enough to fit all of the value types. This can be done by rounding
2767 /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2768 uint32_t CondCodeActions
[ISD::SETCC_INVALID
][(MVT::LAST_VALUETYPE
+ 7) / 8];
2770 ValueTypeActionImpl ValueTypeActions
;
2773 LegalizeKind
getTypeConversion(LLVMContext
&Context
, EVT VT
) const;
2775 /// Targets can specify ISD nodes that they would like PerformDAGCombine
2776 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2779 TargetDAGCombineArray
[(ISD::BUILTIN_OP_END
+CHAR_BIT
-1)/CHAR_BIT
];
2781 /// For operations that must be promoted to a specific type, this holds the
2782 /// destination type. This map should be sparse, so don't hold it as an
2785 /// Targets add entries to this map with AddPromotedToType(..), clients access
2786 /// this with getTypeToPromoteTo(..).
2787 std::map
<std::pair
<unsigned, MVT::SimpleValueType
>, MVT::SimpleValueType
>
2790 /// Stores the name each libcall.
2791 const char *LibcallRoutineNames
[RTLIB::UNKNOWN_LIBCALL
+ 1];
2793 /// The ISD::CondCode that should be used to test the result of each of the
2794 /// comparison libcall against zero.
2795 ISD::CondCode CmpLibcallCCs
[RTLIB::UNKNOWN_LIBCALL
];
2797 /// Stores the CallingConv that should be used for each libcall.
2798 CallingConv::ID LibcallCallingConvs
[RTLIB::UNKNOWN_LIBCALL
];
2800 /// Set default libcall names and calling conventions.
2801 void InitLibcalls(const Triple
&TT
);
2804 /// Return true if the extension represented by \p I is free.
2805 /// \pre \p I is a sign, zero, or fp extension and
2806 /// is[Z|FP]ExtFree of the related types is not true.
2807 virtual bool isExtFreeImpl(const Instruction
*I
) const { return false; }
2809 /// Depth that GatherAllAliases should should continue looking for chain
2810 /// dependencies when trying to find a more preferable chain. As an
2811 /// approximation, this should be more than the number of consecutive stores
2812 /// expected to be merged.
2813 unsigned GatherAllAliasesMaxDepth
;
2815 /// \brief Specify maximum number of store instructions per memset call.
2817 /// When lowering \@llvm.memset this field specifies the maximum number of
2818 /// store operations that may be substituted for the call to memset. Targets
2819 /// must set this value based on the cost threshold for that target. Targets
2820 /// should assume that the memset will be done using as many of the largest
2821 /// store operations first, followed by smaller ones, if necessary, per
2822 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2823 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2824 /// store. This only applies to setting a constant array of a constant size.
2825 unsigned MaxStoresPerMemset
;
2826 /// Likewise for functions with the OptSize attribute.
2827 unsigned MaxStoresPerMemsetOptSize
;
2829 /// \brief Specify maximum number of store instructions per memcpy call.
2831 /// When lowering \@llvm.memcpy this field specifies the maximum number of
2832 /// store operations that may be substituted for a call to memcpy. Targets
2833 /// must set this value based on the cost threshold for that target. Targets
2834 /// should assume that the memcpy will be done using as many of the largest
2835 /// store operations first, followed by smaller ones, if necessary, per
2836 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2837 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2838 /// and one 1-byte store. This only applies to copying a constant array of
2840 unsigned MaxStoresPerMemcpy
;
2841 /// Likewise for functions with the OptSize attribute.
2842 unsigned MaxStoresPerMemcpyOptSize
;
2843 /// \brief Specify max number of store instructions to glue in inlined memcpy.
2845 /// When memcpy is inlined based on MaxStoresPerMemcpy, specify maximum number
2846 /// of store instructions to keep together. This helps in pairing and
2847 // vectorization later on.
2848 unsigned MaxGluedStoresPerMemcpy
= 0;
2850 /// \brief Specify maximum number of load instructions per memcmp call.
2852 /// When lowering \@llvm.memcmp this field specifies the maximum number of
2853 /// pairs of load operations that may be substituted for a call to memcmp.
2854 /// Targets must set this value based on the cost threshold for that target.
2855 /// Targets should assume that the memcmp will be done using as many of the
2856 /// largest load operations first, followed by smaller ones, if necessary, per
2857 /// alignment restrictions. For example, loading 7 bytes on a 32-bit machine
2858 /// with 32-bit alignment would result in one 4-byte load, a one 2-byte load
2859 /// and one 1-byte load. This only applies to copying a constant array of
2861 unsigned MaxLoadsPerMemcmp
;
2862 /// Likewise for functions with the OptSize attribute.
2863 unsigned MaxLoadsPerMemcmpOptSize
;
2865 /// \brief Specify maximum number of store instructions per memmove call.
2867 /// When lowering \@llvm.memmove this field specifies the maximum number of
2868 /// store instructions that may be substituted for a call to memmove. Targets
2869 /// must set this value based on the cost threshold for that target. Targets
2870 /// should assume that the memmove will be done using as many of the largest
2871 /// store operations first, followed by smaller ones, if necessary, per
2872 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2873 /// with 8-bit alignment would result in nine 1-byte stores. This only
2874 /// applies to copying a constant array of constant size.
2875 unsigned MaxStoresPerMemmove
;
2876 /// Likewise for functions with the OptSize attribute.
2877 unsigned MaxStoresPerMemmoveOptSize
;
2879 /// Tells the code generator that select is more expensive than a branch if
2880 /// the branch is usually predicted right.
2881 bool PredictableSelectIsExpensive
;
2883 /// \see enableExtLdPromotion.
2884 bool EnableExtLdPromotion
;
2886 /// Return true if the value types that can be represented by the specified
2887 /// register class are all legal.
2888 bool isLegalRC(const TargetRegisterInfo
&TRI
,
2889 const TargetRegisterClass
&RC
) const;
2891 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2892 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2893 MachineBasicBlock
*emitPatchPoint(MachineInstr
&MI
,
2894 MachineBasicBlock
*MBB
) const;
2896 /// Replace/modify the XRay custom event operands with target-dependent
2898 MachineBasicBlock
*emitXRayCustomEvent(MachineInstr
&MI
,
2899 MachineBasicBlock
*MBB
) const;
2901 /// Replace/modify the XRay typed event operands with target-dependent
2903 MachineBasicBlock
*emitXRayTypedEvent(MachineInstr
&MI
,
2904 MachineBasicBlock
*MBB
) const;
2907 /// This class defines information used to lower LLVM code to legal SelectionDAG
2908 /// operators that the target instruction selector can accept natively.
2910 /// This class also defines callbacks that targets must implement to lower
2911 /// target-specific constructs to SelectionDAG operators.
2912 class TargetLowering
: public TargetLoweringBase
{
2914 struct DAGCombinerInfo
;
2915 struct MakeLibCallOptions
;
2917 TargetLowering(const TargetLowering
&) = delete;
2918 TargetLowering
&operator=(const TargetLowering
&) = delete;
2920 /// NOTE: The TargetMachine owns TLOF.
2921 explicit TargetLowering(const TargetMachine
&TM
);
2923 bool isPositionIndependent() const;
2925 virtual bool isSDNodeSourceOfDivergence(const SDNode
*N
,
2926 FunctionLoweringInfo
*FLI
,
2927 LegacyDivergenceAnalysis
*DA
) const {
2931 virtual bool isSDNodeAlwaysUniform(const SDNode
* N
) const {
2935 /// Returns true by value, base pointer and offset pointer and addressing mode
2936 /// by reference if the node's address can be legally represented as
2937 /// pre-indexed load / store address.
2938 virtual bool getPreIndexedAddressParts(SDNode
* /*N*/, SDValue
&/*Base*/,
2939 SDValue
&/*Offset*/,
2940 ISD::MemIndexedMode
&/*AM*/,
2941 SelectionDAG
&/*DAG*/) const {
2945 /// Returns true by value, base pointer and offset pointer and addressing mode
2946 /// by reference if this node can be combined with a load / store to form a
2947 /// post-indexed load / store.
2948 virtual bool getPostIndexedAddressParts(SDNode
* /*N*/, SDNode
* /*Op*/,
2950 SDValue
&/*Offset*/,
2951 ISD::MemIndexedMode
&/*AM*/,
2952 SelectionDAG
&/*DAG*/) const {
2956 /// Returns true if the specified base+offset is a legal indexed addressing
2957 /// mode for this target. \p MI is the load or store instruction that is being
2958 /// considered for transformation.
2959 virtual bool isIndexingLegal(MachineInstr
&MI
, Register Base
, Register Offset
,
2960 bool IsPre
, MachineRegisterInfo
&MRI
) const {
2964 /// Return the entry encoding for a jump table in the current function. The
2965 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2966 virtual unsigned getJumpTableEncoding() const;
2968 virtual const MCExpr
*
2969 LowerCustomJumpTableEntry(const MachineJumpTableInfo
* /*MJTI*/,
2970 const MachineBasicBlock
* /*MBB*/, unsigned /*uid*/,
2971 MCContext
&/*Ctx*/) const {
2972 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2975 /// Returns relocation base for the given PIC jumptable.
2976 virtual SDValue
getPICJumpTableRelocBase(SDValue Table
,
2977 SelectionDAG
&DAG
) const;
2979 /// This returns the relocation base for the given PIC jumptable, the same as
2980 /// getPICJumpTableRelocBase, but as an MCExpr.
2981 virtual const MCExpr
*
2982 getPICJumpTableRelocBaseExpr(const MachineFunction
*MF
,
2983 unsigned JTI
, MCContext
&Ctx
) const;
2985 /// Return true if folding a constant offset with the given GlobalAddress is
2986 /// legal. It is frequently not legal in PIC relocation models.
2987 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode
*GA
) const;
2989 bool isInTailCallPosition(SelectionDAG
&DAG
, SDNode
*Node
,
2990 SDValue
&Chain
) const;
2992 void softenSetCCOperands(SelectionDAG
&DAG
, EVT VT
, SDValue
&NewLHS
,
2993 SDValue
&NewRHS
, ISD::CondCode
&CCCode
,
2994 const SDLoc
&DL
, const SDValue OldLHS
,
2995 const SDValue OldRHS
) const;
2997 /// Returns a pair of (return value, chain).
2998 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2999 std::pair
<SDValue
, SDValue
> makeLibCall(SelectionDAG
&DAG
, RTLIB::Libcall LC
,
3000 EVT RetVT
, ArrayRef
<SDValue
> Ops
,
3001 MakeLibCallOptions CallOptions
,
3002 const SDLoc
&dl
) const;
3004 /// Check whether parameters to a call that are passed in callee saved
3005 /// registers are the same as from the calling function. This needs to be
3006 /// checked for tail call eligibility.
3007 bool parametersInCSRMatch(const MachineRegisterInfo
&MRI
,
3008 const uint32_t *CallerPreservedMask
,
3009 const SmallVectorImpl
<CCValAssign
> &ArgLocs
,
3010 const SmallVectorImpl
<SDValue
> &OutVals
) const;
3012 //===--------------------------------------------------------------------===//
3013 // TargetLowering Optimization Methods
3016 /// A convenience struct that encapsulates a DAG, and two SDValues for
3017 /// returning information from TargetLowering to its clients that want to
3019 struct TargetLoweringOpt
{
3026 explicit TargetLoweringOpt(SelectionDAG
&InDAG
,
3028 DAG(InDAG
), LegalTys(LT
), LegalOps(LO
) {}
3030 bool LegalTypes() const { return LegalTys
; }
3031 bool LegalOperations() const { return LegalOps
; }
3033 bool CombineTo(SDValue O
, SDValue N
) {
3040 /// Determines the optimal series of memory ops to replace the memset / memcpy.
3041 /// Return true if the number of memory ops is below the threshold (Limit).
3042 /// It returns the types of the sequence of memory ops to perform
3043 /// memset / memcpy by reference.
3044 bool findOptimalMemOpLowering(std::vector
<EVT
> &MemOps
,
3045 unsigned Limit
, uint64_t Size
,
3046 unsigned DstAlign
, unsigned SrcAlign
,
3051 unsigned DstAS
, unsigned SrcAS
,
3052 const AttributeList
&FuncAttributes
) const;
3054 /// Check to see if the specified operand of the specified instruction is a
3055 /// constant integer. If so, check to see if there are any bits set in the
3056 /// constant that are not demanded. If so, shrink the constant and return
3058 bool ShrinkDemandedConstant(SDValue Op
, const APInt
&Demanded
,
3059 TargetLoweringOpt
&TLO
) const;
3061 // Target hook to do target-specific const optimization, which is called by
3062 // ShrinkDemandedConstant. This function should return true if the target
3063 // doesn't want ShrinkDemandedConstant to further optimize the constant.
3064 virtual bool targetShrinkDemandedConstant(SDValue Op
, const APInt
&Demanded
,
3065 TargetLoweringOpt
&TLO
) const {
3069 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
3070 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
3071 /// generalized for targets with other types of implicit widening casts.
3072 bool ShrinkDemandedOp(SDValue Op
, unsigned BitWidth
, const APInt
&Demanded
,
3073 TargetLoweringOpt
&TLO
) const;
3075 /// Look at Op. At this point, we know that only the DemandedBits bits of the
3076 /// result of Op are ever used downstream. If we can use this information to
3077 /// simplify Op, create a new simplified DAG node and return true, returning
3078 /// the original and new nodes in Old and New. Otherwise, analyze the
3079 /// expression and return a mask of KnownOne and KnownZero bits for the
3080 /// expression (used to simplify the caller). The KnownZero/One bits may only
3081 /// be accurate for those bits in the Demanded masks.
3082 /// \p AssumeSingleUse When this parameter is true, this function will
3083 /// attempt to simplify \p Op even if there are multiple uses.
3084 /// Callers are responsible for correctly updating the DAG based on the
3085 /// results of this function, because simply replacing replacing TLO.Old
3086 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3087 /// has multiple uses.
3088 bool SimplifyDemandedBits(SDValue Op
, const APInt
&DemandedBits
,
3089 const APInt
&DemandedElts
, KnownBits
&Known
,
3090 TargetLoweringOpt
&TLO
, unsigned Depth
= 0,
3091 bool AssumeSingleUse
= false) const;
3093 /// Helper wrapper around SimplifyDemandedBits, demanding all elements.
3094 /// Adds Op back to the worklist upon success.
3095 bool SimplifyDemandedBits(SDValue Op
, const APInt
&DemandedBits
,
3096 KnownBits
&Known
, TargetLoweringOpt
&TLO
,
3098 bool AssumeSingleUse
= false) const;
3100 /// Helper wrapper around SimplifyDemandedBits.
3101 /// Adds Op back to the worklist upon success.
3102 bool SimplifyDemandedBits(SDValue Op
, const APInt
&DemandedMask
,
3103 DAGCombinerInfo
&DCI
) const;
3105 /// More limited version of SimplifyDemandedBits that can be used to "look
3106 /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3107 /// bitwise ops etc.
3108 SDValue
SimplifyMultipleUseDemandedBits(SDValue Op
, const APInt
&DemandedBits
,
3109 const APInt
&DemandedElts
,
3111 unsigned Depth
) const;
3113 /// Look at Vector Op. At this point, we know that only the DemandedElts
3114 /// elements of the result of Op are ever used downstream. If we can use
3115 /// this information to simplify Op, create a new simplified DAG node and
3116 /// return true, storing the original and new nodes in TLO.
3117 /// Otherwise, analyze the expression and return a mask of KnownUndef and
3118 /// KnownZero elements for the expression (used to simplify the caller).
3119 /// The KnownUndef/Zero elements may only be accurate for those bits
3120 /// in the DemandedMask.
3121 /// \p AssumeSingleUse When this parameter is true, this function will
3122 /// attempt to simplify \p Op even if there are multiple uses.
3123 /// Callers are responsible for correctly updating the DAG based on the
3124 /// results of this function, because simply replacing replacing TLO.Old
3125 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
3126 /// has multiple uses.
3127 bool SimplifyDemandedVectorElts(SDValue Op
, const APInt
&DemandedEltMask
,
3128 APInt
&KnownUndef
, APInt
&KnownZero
,
3129 TargetLoweringOpt
&TLO
, unsigned Depth
= 0,
3130 bool AssumeSingleUse
= false) const;
3132 /// Helper wrapper around SimplifyDemandedVectorElts.
3133 /// Adds Op back to the worklist upon success.
3134 bool SimplifyDemandedVectorElts(SDValue Op
, const APInt
&DemandedElts
,
3135 APInt
&KnownUndef
, APInt
&KnownZero
,
3136 DAGCombinerInfo
&DCI
) const;
3138 /// Determine which of the bits specified in Mask are known to be either zero
3139 /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3140 /// argument allows us to only collect the known bits that are shared by the
3141 /// requested vector elements.
3142 virtual void computeKnownBitsForTargetNode(const SDValue Op
,
3144 const APInt
&DemandedElts
,
3145 const SelectionDAG
&DAG
,
3146 unsigned Depth
= 0) const;
3147 /// Determine which of the bits specified in Mask are known to be either zero
3148 /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
3149 /// argument allows us to only collect the known bits that are shared by the
3150 /// requested vector elements. This is for GISel.
3151 virtual void computeKnownBitsForTargetInstr(Register R
, KnownBits
&Known
,
3152 const APInt
&DemandedElts
,
3153 const MachineRegisterInfo
&MRI
,
3154 unsigned Depth
= 0) const;
3156 /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
3157 /// Default implementation computes low bits based on alignment
3158 /// information. This should preserve known bits passed into it.
3159 virtual void computeKnownBitsForFrameIndex(const SDValue FIOp
,
3161 const APInt
&DemandedElts
,
3162 const SelectionDAG
&DAG
,
3163 unsigned Depth
= 0) const;
3165 /// This method can be implemented by targets that want to expose additional
3166 /// information about sign bits to the DAG Combiner. The DemandedElts
3167 /// argument allows us to only collect the minimum sign bits that are shared
3168 /// by the requested vector elements.
3169 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op
,
3170 const APInt
&DemandedElts
,
3171 const SelectionDAG
&DAG
,
3172 unsigned Depth
= 0) const;
3174 /// Attempt to simplify any target nodes based on the demanded vector
3175 /// elements, returning true on success. Otherwise, analyze the expression and
3176 /// return a mask of KnownUndef and KnownZero elements for the expression
3177 /// (used to simplify the caller). The KnownUndef/Zero elements may only be
3178 /// accurate for those bits in the DemandedMask.
3179 virtual bool SimplifyDemandedVectorEltsForTargetNode(
3180 SDValue Op
, const APInt
&DemandedElts
, APInt
&KnownUndef
,
3181 APInt
&KnownZero
, TargetLoweringOpt
&TLO
, unsigned Depth
= 0) const;
3183 /// Attempt to simplify any target nodes based on the demanded bits/elts,
3184 /// returning true on success. Otherwise, analyze the
3185 /// expression and return a mask of KnownOne and KnownZero bits for the
3186 /// expression (used to simplify the caller). The KnownZero/One bits may only
3187 /// be accurate for those bits in the Demanded masks.
3188 virtual bool SimplifyDemandedBitsForTargetNode(SDValue Op
,
3189 const APInt
&DemandedBits
,
3190 const APInt
&DemandedElts
,
3192 TargetLoweringOpt
&TLO
,
3193 unsigned Depth
= 0) const;
3195 /// More limited version of SimplifyDemandedBits that can be used to "look
3196 /// through" ops that don't contribute to the DemandedBits/DemandedElts -
3197 /// bitwise ops etc.
3198 virtual SDValue
SimplifyMultipleUseDemandedBitsForTargetNode(
3199 SDValue Op
, const APInt
&DemandedBits
, const APInt
&DemandedElts
,
3200 SelectionDAG
&DAG
, unsigned Depth
) const;
3202 /// Tries to build a legal vector shuffle using the provided parameters
3203 /// or equivalent variations. The Mask argument maybe be modified as the
3204 /// function tries different variations.
3205 /// Returns an empty SDValue if the operation fails.
3206 SDValue
buildLegalVectorShuffle(EVT VT
, const SDLoc
&DL
, SDValue N0
,
3207 SDValue N1
, MutableArrayRef
<int> Mask
,
3208 SelectionDAG
&DAG
) const;
3210 /// This method returns the constant pool value that will be loaded by LD.
3211 /// NOTE: You must check for implicit extensions of the constant by LD.
3212 virtual const Constant
*getTargetConstantFromLoad(LoadSDNode
*LD
) const;
3214 /// If \p SNaN is false, \returns true if \p Op is known to never be any
3215 /// NaN. If \p sNaN is true, returns if \p Op is known to never be a signaling
3217 virtual bool isKnownNeverNaNForTargetNode(SDValue Op
,
3218 const SelectionDAG
&DAG
,
3220 unsigned Depth
= 0) const;
3221 struct DAGCombinerInfo
{
3222 void *DC
; // The DAG Combiner object.
3224 bool CalledByLegalizer
;
3229 DAGCombinerInfo(SelectionDAG
&dag
, CombineLevel level
, bool cl
, void *dc
)
3230 : DC(dc
), Level(level
), CalledByLegalizer(cl
), DAG(dag
) {}
3232 bool isBeforeLegalize() const { return Level
== BeforeLegalizeTypes
; }
3233 bool isBeforeLegalizeOps() const { return Level
< AfterLegalizeVectorOps
; }
3234 bool isAfterLegalizeDAG() const {
3235 return Level
== AfterLegalizeDAG
;
3237 CombineLevel
getDAGCombineLevel() { return Level
; }
3238 bool isCalledByLegalizer() const { return CalledByLegalizer
; }
3240 void AddToWorklist(SDNode
*N
);
3241 SDValue
CombineTo(SDNode
*N
, ArrayRef
<SDValue
> To
, bool AddTo
= true);
3242 SDValue
CombineTo(SDNode
*N
, SDValue Res
, bool AddTo
= true);
3243 SDValue
CombineTo(SDNode
*N
, SDValue Res0
, SDValue Res1
, bool AddTo
= true);
3245 void CommitTargetLoweringOpt(const TargetLoweringOpt
&TLO
);
3248 /// Return if the N is a constant or constant vector equal to the true value
3249 /// from getBooleanContents().
3250 bool isConstTrueVal(const SDNode
*N
) const;
3252 /// Return if the N is a constant or constant vector equal to the false value
3253 /// from getBooleanContents().
3254 bool isConstFalseVal(const SDNode
*N
) const;
3256 /// Return if \p N is a True value when extended to \p VT.
3257 bool isExtendedTrueVal(const ConstantSDNode
*N
, EVT VT
, bool SExt
) const;
3259 /// Try to simplify a setcc built with the specified operands and cc. If it is
3260 /// unable to simplify it, return a null SDValue.
3261 SDValue
SimplifySetCC(EVT VT
, SDValue N0
, SDValue N1
, ISD::CondCode Cond
,
3262 bool foldBooleans
, DAGCombinerInfo
&DCI
,
3263 const SDLoc
&dl
) const;
3265 // For targets which wrap address, unwrap for analysis.
3266 virtual SDValue
unwrapAddress(SDValue N
) const { return N
; }
3268 /// Returns true (and the GlobalValue and the offset) if the node is a
3269 /// GlobalAddress + offset.
3271 isGAPlusOffset(SDNode
*N
, const GlobalValue
* &GA
, int64_t &Offset
) const;
3273 /// This method will be invoked for all target nodes and for any
3274 /// target-independent nodes that the target has registered with invoke it
3277 /// The semantics are as follows:
3279 /// SDValue.Val == 0 - No change was made
3280 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
3281 /// otherwise - N should be replaced by the returned Operand.
3283 /// In addition, methods provided by DAGCombinerInfo may be used to perform
3284 /// more complex transformations.
3286 virtual SDValue
PerformDAGCombine(SDNode
*N
, DAGCombinerInfo
&DCI
) const;
3288 /// Return true if it is profitable to move this shift by a constant amount
3289 /// though its operand, adjusting any immediate operands as necessary to
3290 /// preserve semantics. This transformation may not be desirable if it
3291 /// disrupts a particularly auspicious target-specific tree (e.g. bitfield
3292 /// extraction in AArch64). By default, it returns true.
3294 /// @param N the shift node
3295 /// @param Level the current DAGCombine legalization level.
3296 virtual bool isDesirableToCommuteWithShift(const SDNode
*N
,
3297 CombineLevel Level
) const {
3301 // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
3302 // to a shuffle and a truncate.
3303 // Example of such a combine:
3304 // v4i32 build_vector((extract_elt V, 1),
3305 // (extract_elt V, 3),
3306 // (extract_elt V, 5),
3307 // (extract_elt V, 7))
3309 // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
3310 virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
3311 ArrayRef
<int> ShuffleMask
, EVT SrcVT
, EVT TruncVT
) const {
3315 /// Return true if the target has native support for the specified value type
3316 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
3317 /// i16 is legal, but undesirable since i16 instruction encodings are longer
3318 /// and some i16 instructions are slow.
3319 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT
) const {
3320 // By default, assume all legal types are desirable.
3321 return isTypeLegal(VT
);
3324 /// Return true if it is profitable for dag combiner to transform a floating
3325 /// point op of specified opcode to a equivalent op of an integer
3326 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
3327 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
3332 /// This method query the target whether it is beneficial for dag combiner to
3333 /// promote the specified node. If true, it should return the desired
3334 /// promotion type by reference.
3335 virtual bool IsDesirableToPromoteOp(SDValue
/*Op*/, EVT
&/*PVT*/) const {
3339 /// Return true if the target supports swifterror attribute. It optimizes
3340 /// loads and stores to reading and writing a specific register.
3341 virtual bool supportSwiftError() const {
3345 /// Return true if the target supports that a subset of CSRs for the given
3346 /// machine function is handled explicitly via copies.
3347 virtual bool supportSplitCSR(MachineFunction
*MF
) const {
3351 /// Perform necessary initialization to handle a subset of CSRs explicitly
3352 /// via copies. This function is called at the beginning of instruction
3354 virtual void initializeSplitCSR(MachineBasicBlock
*Entry
) const {
3355 llvm_unreachable("Not Implemented");
3358 /// Insert explicit copies in entry and exit blocks. We copy a subset of
3359 /// CSRs to virtual registers in the entry block, and copy them back to
3360 /// physical registers in the exit blocks. This function is called at the end
3361 /// of instruction selection.
3362 virtual void insertCopiesSplitCSR(
3363 MachineBasicBlock
*Entry
,
3364 const SmallVectorImpl
<MachineBasicBlock
*> &Exits
) const {
3365 llvm_unreachable("Not Implemented");
3368 /// Return 1 if we can compute the negated form of the specified expression
3369 /// for the same cost as the expression itself, or 2 if we can compute the
3370 /// negated form more cheaply than the expression itself. Else return 0.
3371 virtual char isNegatibleForFree(SDValue Op
, SelectionDAG
&DAG
,
3372 bool LegalOperations
, bool ForCodeSize
,
3373 unsigned Depth
= 0) const;
3375 /// If isNegatibleForFree returns true, return the newly negated expression.
3376 virtual SDValue
getNegatedExpression(SDValue Op
, SelectionDAG
&DAG
,
3377 bool LegalOperations
, bool ForCodeSize
,
3378 unsigned Depth
= 0) const;
3380 //===--------------------------------------------------------------------===//
3381 // Lowering methods - These methods must be implemented by targets so that
3382 // the SelectionDAGBuilder code knows how to lower these.
3385 /// This hook must be implemented to lower the incoming (formal) arguments,
3386 /// described by the Ins array, into the specified DAG. The implementation
3387 /// should fill in the InVals array with legal-type argument values, and
3388 /// return the resulting token chain value.
3389 virtual SDValue
LowerFormalArguments(
3390 SDValue
/*Chain*/, CallingConv::ID
/*CallConv*/, bool /*isVarArg*/,
3391 const SmallVectorImpl
<ISD::InputArg
> & /*Ins*/, const SDLoc
& /*dl*/,
3392 SelectionDAG
& /*DAG*/, SmallVectorImpl
<SDValue
> & /*InVals*/) const {
3393 llvm_unreachable("Not Implemented");
3396 /// This structure contains all information that is necessary for lowering
3397 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
3398 /// needs to lower a call, and targets will see this struct in their LowerCall
3400 struct CallLoweringInfo
{
3402 Type
*RetTy
= nullptr;
3407 bool DoesNotReturn
: 1;
3408 bool IsReturnValueUsed
: 1;
3409 bool IsConvergent
: 1;
3410 bool IsPatchPoint
: 1;
3412 // IsTailCall should be modified by implementations of
3413 // TargetLowering::LowerCall that perform tail call conversions.
3414 bool IsTailCall
= false;
3416 // Is Call lowering done post SelectionDAG type legalization.
3417 bool IsPostTypeLegalization
= false;
3419 unsigned NumFixedArgs
= -1;
3420 CallingConv::ID CallConv
= CallingConv::C
;
3425 ImmutableCallSite CS
;
3426 SmallVector
<ISD::OutputArg
, 32> Outs
;
3427 SmallVector
<SDValue
, 32> OutVals
;
3428 SmallVector
<ISD::InputArg
, 32> Ins
;
3429 SmallVector
<SDValue
, 4> InVals
;
3431 CallLoweringInfo(SelectionDAG
&DAG
)
3432 : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
3433 DoesNotReturn(false), IsReturnValueUsed(true), IsConvergent(false),
3434 IsPatchPoint(false), DAG(DAG
) {}
3436 CallLoweringInfo
&setDebugLoc(const SDLoc
&dl
) {
3441 CallLoweringInfo
&setChain(SDValue InChain
) {
3446 // setCallee with target/module-specific attributes
3447 CallLoweringInfo
&setLibCallee(CallingConv::ID CC
, Type
*ResultType
,
3448 SDValue Target
, ArgListTy
&&ArgsList
) {
3452 NumFixedArgs
= ArgsList
.size();
3453 Args
= std::move(ArgsList
);
3455 DAG
.getTargetLoweringInfo().markLibCallAttributes(
3456 &(DAG
.getMachineFunction()), CC
, Args
);
3460 CallLoweringInfo
&setCallee(CallingConv::ID CC
, Type
*ResultType
,
3461 SDValue Target
, ArgListTy
&&ArgsList
) {
3465 NumFixedArgs
= ArgsList
.size();
3466 Args
= std::move(ArgsList
);
3470 CallLoweringInfo
&setCallee(Type
*ResultType
, FunctionType
*FTy
,
3471 SDValue Target
, ArgListTy
&&ArgsList
,
3472 ImmutableCallSite Call
) {
3475 IsInReg
= Call
.hasRetAttr(Attribute::InReg
);
3477 Call
.doesNotReturn() ||
3478 (!Call
.isInvoke() &&
3479 isa
<UnreachableInst
>(Call
.getInstruction()->getNextNode()));
3480 IsVarArg
= FTy
->isVarArg();
3481 IsReturnValueUsed
= !Call
.getInstruction()->use_empty();
3482 RetSExt
= Call
.hasRetAttr(Attribute::SExt
);
3483 RetZExt
= Call
.hasRetAttr(Attribute::ZExt
);
3487 CallConv
= Call
.getCallingConv();
3488 NumFixedArgs
= FTy
->getNumParams();
3489 Args
= std::move(ArgsList
);
3496 CallLoweringInfo
&setInRegister(bool Value
= true) {
3501 CallLoweringInfo
&setNoReturn(bool Value
= true) {
3502 DoesNotReturn
= Value
;
3506 CallLoweringInfo
&setVarArg(bool Value
= true) {
3511 CallLoweringInfo
&setTailCall(bool Value
= true) {
3516 CallLoweringInfo
&setDiscardResult(bool Value
= true) {
3517 IsReturnValueUsed
= !Value
;
3521 CallLoweringInfo
&setConvergent(bool Value
= true) {
3522 IsConvergent
= Value
;
3526 CallLoweringInfo
&setSExtResult(bool Value
= true) {
3531 CallLoweringInfo
&setZExtResult(bool Value
= true) {
3536 CallLoweringInfo
&setIsPatchPoint(bool Value
= true) {
3537 IsPatchPoint
= Value
;
3541 CallLoweringInfo
&setIsPostTypeLegalization(bool Value
=true) {
3542 IsPostTypeLegalization
= Value
;
3546 ArgListTy
&getArgs() {
3551 /// This structure is used to pass arguments to makeLibCall function.
3552 struct MakeLibCallOptions
{
3553 // By passing type list before soften to makeLibCall, the target hook
3554 // shouldExtendTypeInLibCall can get the original type before soften.
3555 ArrayRef
<EVT
> OpsVTBeforeSoften
;
3556 EVT RetVTBeforeSoften
;
3558 bool DoesNotReturn
: 1;
3559 bool IsReturnValueUsed
: 1;
3560 bool IsPostTypeLegalization
: 1;
3563 MakeLibCallOptions()
3564 : IsSExt(false), DoesNotReturn(false), IsReturnValueUsed(true),
3565 IsPostTypeLegalization(false), IsSoften(false) {}
3567 MakeLibCallOptions
&setSExt(bool Value
= true) {
3572 MakeLibCallOptions
&setNoReturn(bool Value
= true) {
3573 DoesNotReturn
= Value
;
3577 MakeLibCallOptions
&setDiscardResult(bool Value
= true) {
3578 IsReturnValueUsed
= !Value
;
3582 MakeLibCallOptions
&setIsPostTypeLegalization(bool Value
= true) {
3583 IsPostTypeLegalization
= Value
;
3587 MakeLibCallOptions
&setTypeListBeforeSoften(ArrayRef
<EVT
> OpsVT
, EVT RetVT
,
3588 bool Value
= true) {
3589 OpsVTBeforeSoften
= OpsVT
;
3590 RetVTBeforeSoften
= RetVT
;
3596 /// This function lowers an abstract call to a function into an actual call.
3597 /// This returns a pair of operands. The first element is the return value
3598 /// for the function (if RetTy is not VoidTy). The second element is the
3599 /// outgoing token chain. It calls LowerCall to do the actual lowering.
3600 std::pair
<SDValue
, SDValue
> LowerCallTo(CallLoweringInfo
&CLI
) const;
3602 /// This hook must be implemented to lower calls into the specified
3603 /// DAG. The outgoing arguments to the call are described by the Outs array,
3604 /// and the values to be returned by the call are described by the Ins
3605 /// array. The implementation should fill in the InVals array with legal-type
3606 /// return values from the call, and return the resulting token chain value.
3608 LowerCall(CallLoweringInfo
&/*CLI*/,
3609 SmallVectorImpl
<SDValue
> &/*InVals*/) const {
3610 llvm_unreachable("Not Implemented");
3613 /// Target-specific cleanup for formal ByVal parameters.
3614 virtual void HandleByVal(CCState
*, unsigned &, unsigned) const {}
3616 /// This hook should be implemented to check whether the return values
3617 /// described by the Outs array can fit into the return registers. If false
3618 /// is returned, an sret-demotion is performed.
3619 virtual bool CanLowerReturn(CallingConv::ID
/*CallConv*/,
3620 MachineFunction
&/*MF*/, bool /*isVarArg*/,
3621 const SmallVectorImpl
<ISD::OutputArg
> &/*Outs*/,
3622 LLVMContext
&/*Context*/) const
3624 // Return true by default to get preexisting behavior.
3628 /// This hook must be implemented to lower outgoing return values, described
3629 /// by the Outs array, into the specified DAG. The implementation should
3630 /// return the resulting token chain value.
3631 virtual SDValue
LowerReturn(SDValue
/*Chain*/, CallingConv::ID
/*CallConv*/,
3633 const SmallVectorImpl
<ISD::OutputArg
> & /*Outs*/,
3634 const SmallVectorImpl
<SDValue
> & /*OutVals*/,
3635 const SDLoc
& /*dl*/,
3636 SelectionDAG
& /*DAG*/) const {
3637 llvm_unreachable("Not Implemented");
3640 /// Return true if result of the specified node is used by a return node
3641 /// only. It also compute and return the input chain for the tail call.
3643 /// This is used to determine whether it is possible to codegen a libcall as
3644 /// tail call at legalization time.
3645 virtual bool isUsedByReturnOnly(SDNode
*, SDValue
&/*Chain*/) const {
3649 /// Return true if the target may be able emit the call instruction as a tail
3650 /// call. This is used by optimization passes to determine if it's profitable
3651 /// to duplicate return instructions to enable tailcall optimization.
3652 virtual bool mayBeEmittedAsTailCall(const CallInst
*) const {
3656 /// Return the builtin name for the __builtin___clear_cache intrinsic
3657 /// Default is to invoke the clear cache library call
3658 virtual const char * getClearCacheBuiltinName() const {
3659 return "__clear_cache";
3662 /// Return the register ID of the name passed in. Used by named register
3663 /// global variables extension. There is no target-independent behaviour
3664 /// so the default action is to bail.
3665 virtual unsigned getRegisterByName(const char* RegName
, EVT VT
,
3666 SelectionDAG
&DAG
) const {
3667 report_fatal_error("Named registers not implemented for this target");
3670 /// Return the type that should be used to zero or sign extend a
3671 /// zeroext/signext integer return value. FIXME: Some C calling conventions
3672 /// require the return type to be promoted, but this is not true all the time,
3673 /// e.g. i1/i8/i16 on x86/x86_64. It is also not necessary for non-C calling
3674 /// conventions. The frontend should handle this and include all of the
3675 /// necessary information.
3676 virtual EVT
getTypeForExtReturn(LLVMContext
&Context
, EVT VT
,
3677 ISD::NodeType
/*ExtendKind*/) const {
3678 EVT MinVT
= getRegisterType(Context
, MVT::i32
);
3679 return VT
.bitsLT(MinVT
) ? MinVT
: VT
;
3682 /// For some targets, an LLVM struct type must be broken down into multiple
3683 /// simple types, but the calling convention specifies that the entire struct
3684 /// must be passed in a block of consecutive registers.
3686 functionArgumentNeedsConsecutiveRegisters(Type
*Ty
, CallingConv::ID CallConv
,
3687 bool isVarArg
) const {
3691 /// For most targets, an LLVM type must be broken down into multiple
3692 /// smaller types. Usually the halves are ordered according to the endianness
3693 /// but for some platform that would break. So this method will default to
3694 /// matching the endianness but can be overridden.
3696 shouldSplitFunctionArgumentsAsLittleEndian(const DataLayout
&DL
) const {
3697 return DL
.isLittleEndian();
3700 /// Returns a 0 terminated array of registers that can be safely used as
3701 /// scratch registers.
3702 virtual const MCPhysReg
*getScratchRegisters(CallingConv::ID CC
) const {
3706 /// This callback is used to prepare for a volatile or atomic load.
3707 /// It takes a chain node as input and returns the chain for the load itself.
3709 /// Having a callback like this is necessary for targets like SystemZ,
3710 /// which allows a CPU to reuse the result of a previous load indefinitely,
3711 /// even if a cache-coherent store is performed by another CPU. The default
3712 /// implementation does nothing.
3713 virtual SDValue
prepareVolatileOrAtomicLoad(SDValue Chain
, const SDLoc
&DL
,
3714 SelectionDAG
&DAG
) const {
3718 /// This callback is used to inspect load/store instructions and add
3719 /// target-specific MachineMemOperand flags to them. The default
3720 /// implementation does nothing.
3721 virtual MachineMemOperand::Flags
getMMOFlags(const Instruction
&I
) const {
3722 return MachineMemOperand::MONone
;
3725 /// Should SelectionDAG lower an atomic store of the given kind as a normal
3726 /// StoreSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to
3727 /// eventually migrate all targets to the using StoreSDNodes, but porting is
3728 /// being done target at a time.
3729 virtual bool lowerAtomicStoreAsStoreSDNode(const StoreInst
&SI
) const {
3730 assert(SI
.isAtomic() && "violated precondition");
3734 /// Should SelectionDAG lower an atomic load of the given kind as a normal
3735 /// LoadSDNode (as opposed to an AtomicSDNode)? NOTE: The intention is to
3736 /// eventually migrate all targets to the using LoadSDNodes, but porting is
3737 /// being done target at a time.
3738 virtual bool lowerAtomicLoadAsLoadSDNode(const LoadInst
&LI
) const {
3739 assert(LI
.isAtomic() && "violated precondition");
3744 /// This callback is invoked by the type legalizer to legalize nodes with an
3745 /// illegal operand type but legal result types. It replaces the
3746 /// LowerOperation callback in the type Legalizer. The reason we can not do
3747 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
3748 /// use this callback.
3750 /// TODO: Consider merging with ReplaceNodeResults.
3752 /// The target places new result values for the node in Results (their number
3753 /// and types must exactly match those of the original return values of
3754 /// the node), or leaves Results empty, which indicates that the node is not
3755 /// to be custom lowered after all.
3756 /// The default implementation calls LowerOperation.
3757 virtual void LowerOperationWrapper(SDNode
*N
,
3758 SmallVectorImpl
<SDValue
> &Results
,
3759 SelectionDAG
&DAG
) const;
3761 /// This callback is invoked for operations that are unsupported by the
3762 /// target, which are registered to use 'custom' lowering, and whose defined
3763 /// values are all legal. If the target has no operations that require custom
3764 /// lowering, it need not implement this. The default implementation of this
3766 virtual SDValue
LowerOperation(SDValue Op
, SelectionDAG
&DAG
) const;
3768 /// This callback is invoked when a node result type is illegal for the
3769 /// target, and the operation was registered to use 'custom' lowering for that
3770 /// result type. The target places new result values for the node in Results
3771 /// (their number and types must exactly match those of the original return
3772 /// values of the node), or leaves Results empty, which indicates that the
3773 /// node is not to be custom lowered after all.
3775 /// If the target has no operations that require custom lowering, it need not
3776 /// implement this. The default implementation aborts.
3777 virtual void ReplaceNodeResults(SDNode
* /*N*/,
3778 SmallVectorImpl
<SDValue
> &/*Results*/,
3779 SelectionDAG
&/*DAG*/) const {
3780 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
3783 /// This method returns the name of a target specific DAG node.
3784 virtual const char *getTargetNodeName(unsigned Opcode
) const;
3786 /// This method returns a target specific FastISel object, or null if the
3787 /// target does not support "fast" ISel.
3788 virtual FastISel
*createFastISel(FunctionLoweringInfo
&,
3789 const TargetLibraryInfo
*) const {
3793 bool verifyReturnAddressArgumentIsConstant(SDValue Op
,
3794 SelectionDAG
&DAG
) const;
3796 //===--------------------------------------------------------------------===//
3797 // Inline Asm Support hooks
3800 /// This hook allows the target to expand an inline asm call to be explicit
3801 /// llvm code if it wants to. This is useful for turning simple inline asms
3802 /// into LLVM intrinsics, which gives the compiler more information about the
3803 /// behavior of the code.
3804 virtual bool ExpandInlineAsm(CallInst
*) const {
3808 enum ConstraintType
{
3809 C_Register
, // Constraint represents specific register(s).
3810 C_RegisterClass
, // Constraint represents any of register(s) in class.
3811 C_Memory
, // Memory constraint.
3812 C_Immediate
, // Requires an immediate.
3813 C_Other
, // Something else.
3814 C_Unknown
// Unsupported constraint.
3817 enum ConstraintWeight
{
3819 CW_Invalid
= -1, // No match.
3820 CW_Okay
= 0, // Acceptable.
3821 CW_Good
= 1, // Good weight.
3822 CW_Better
= 2, // Better weight.
3823 CW_Best
= 3, // Best weight.
3825 // Well-known weights.
3826 CW_SpecificReg
= CW_Okay
, // Specific register operands.
3827 CW_Register
= CW_Good
, // Register operands.
3828 CW_Memory
= CW_Better
, // Memory operands.
3829 CW_Constant
= CW_Best
, // Constant operand.
3830 CW_Default
= CW_Okay
// Default or don't know type.
3833 /// This contains information for each constraint that we are lowering.
3834 struct AsmOperandInfo
: public InlineAsm::ConstraintInfo
{
3835 /// This contains the actual string for the code, like "m". TargetLowering
3836 /// picks the 'best' code from ConstraintInfo::Codes that most closely
3837 /// matches the operand.
3838 std::string ConstraintCode
;
3840 /// Information about the constraint code, e.g. Register, RegisterClass,
3841 /// Memory, Other, Unknown.
3842 TargetLowering::ConstraintType ConstraintType
= TargetLowering::C_Unknown
;
3844 /// If this is the result output operand or a clobber, this is null,
3845 /// otherwise it is the incoming operand to the CallInst. This gets
3846 /// modified as the asm is processed.
3847 Value
*CallOperandVal
= nullptr;
3849 /// The ValueType for the operand value.
3850 MVT ConstraintVT
= MVT::Other
;
3852 /// Copy constructor for copying from a ConstraintInfo.
3853 AsmOperandInfo(InlineAsm::ConstraintInfo Info
)
3854 : InlineAsm::ConstraintInfo(std::move(Info
)) {}
3856 /// Return true of this is an input operand that is a matching constraint
3858 bool isMatchingInputConstraint() const;
3860 /// If this is an input matching constraint, this method returns the output
3861 /// operand it matches.
3862 unsigned getMatchedOperand() const;
3865 using AsmOperandInfoVector
= std::vector
<AsmOperandInfo
>;
3867 /// Split up the constraint string from the inline assembly value into the
3868 /// specific constraints and their prefixes, and also tie in the associated
3869 /// operand values. If this returns an empty vector, and if the constraint
3870 /// string itself isn't empty, there was an error parsing.
3871 virtual AsmOperandInfoVector
ParseConstraints(const DataLayout
&DL
,
3872 const TargetRegisterInfo
*TRI
,
3873 ImmutableCallSite CS
) const;
3875 /// Examine constraint type and operand type and determine a weight value.
3876 /// The operand object must already have been set up with the operand type.
3877 virtual ConstraintWeight
getMultipleConstraintMatchWeight(
3878 AsmOperandInfo
&info
, int maIndex
) const;
3880 /// Examine constraint string and operand type and determine a weight value.
3881 /// The operand object must already have been set up with the operand type.
3882 virtual ConstraintWeight
getSingleConstraintMatchWeight(
3883 AsmOperandInfo
&info
, const char *constraint
) const;
3885 /// Determines the constraint code and constraint type to use for the specific
3886 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
3887 /// If the actual operand being passed in is available, it can be passed in as
3888 /// Op, otherwise an empty SDValue can be passed.
3889 virtual void ComputeConstraintToUse(AsmOperandInfo
&OpInfo
,
3891 SelectionDAG
*DAG
= nullptr) const;
3893 /// Given a constraint, return the type of constraint it is for this target.
3894 virtual ConstraintType
getConstraintType(StringRef Constraint
) const;
3896 /// Given a physical register constraint (e.g. {edx}), return the register
3897 /// number and the register class for the register.
3899 /// Given a register class constraint, like 'r', if this corresponds directly
3900 /// to an LLVM register class, return a register of 0 and the register class
3903 /// This should only be used for C_Register constraints. On error, this
3904 /// returns a register number of 0 and a null register class pointer.
3905 virtual std::pair
<unsigned, const TargetRegisterClass
*>
3906 getRegForInlineAsmConstraint(const TargetRegisterInfo
*TRI
,
3907 StringRef Constraint
, MVT VT
) const;
3909 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode
) const {
3910 if (ConstraintCode
== "i")
3911 return InlineAsm::Constraint_i
;
3912 else if (ConstraintCode
== "m")
3913 return InlineAsm::Constraint_m
;
3914 return InlineAsm::Constraint_Unknown
;
3917 /// Try to replace an X constraint, which matches anything, with another that
3918 /// has more specific requirements based on the type of the corresponding
3919 /// operand. This returns null if there is no replacement to make.
3920 virtual const char *LowerXConstraint(EVT ConstraintVT
) const;
3922 /// Lower the specified operand into the Ops vector. If it is invalid, don't
3923 /// add anything to Ops.
3924 virtual void LowerAsmOperandForConstraint(SDValue Op
, std::string
&Constraint
,
3925 std::vector
<SDValue
> &Ops
,
3926 SelectionDAG
&DAG
) const;
3928 // Lower custom output constraints. If invalid, return SDValue().
3929 virtual SDValue
LowerAsmOutputForConstraint(SDValue
&Chain
, SDValue
&Flag
,
3931 const AsmOperandInfo
&OpInfo
,
3932 SelectionDAG
&DAG
) const;
3934 //===--------------------------------------------------------------------===//
3935 // Div utility functions
3937 SDValue
BuildSDIV(SDNode
*N
, SelectionDAG
&DAG
, bool IsAfterLegalization
,
3938 SmallVectorImpl
<SDNode
*> &Created
) const;
3939 SDValue
BuildUDIV(SDNode
*N
, SelectionDAG
&DAG
, bool IsAfterLegalization
,
3940 SmallVectorImpl
<SDNode
*> &Created
) const;
3942 /// Targets may override this function to provide custom SDIV lowering for
3943 /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
3944 /// assumes SDIV is expensive and replaces it with a series of other integer
3946 virtual SDValue
BuildSDIVPow2(SDNode
*N
, const APInt
&Divisor
,
3948 SmallVectorImpl
<SDNode
*> &Created
) const;
3950 /// Indicate whether this target prefers to combine FDIVs with the same
3951 /// divisor. If the transform should never be done, return zero. If the
3952 /// transform should be done, return the minimum number of divisor uses
3953 /// that must exist.
3954 virtual unsigned combineRepeatedFPDivisors() const {
3958 /// Hooks for building estimates in place of slower divisions and square
3961 /// Return either a square root or its reciprocal estimate value for the input
3963 /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3964 /// 'Enabled' as set by a potential default override attribute.
3965 /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3966 /// refinement iterations required to generate a sufficient (though not
3967 /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3968 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
3969 /// algorithm implementation that uses either one or two constants.
3970 /// The boolean Reciprocal is used to select whether the estimate is for the
3971 /// square root of the input operand or the reciprocal of its square root.
3972 /// A target may choose to implement its own refinement within this function.
3973 /// If that's true, then return '0' as the number of RefinementSteps to avoid
3974 /// any further refinement of the estimate.
3975 /// An empty SDValue return means no estimate sequence can be created.
3976 virtual SDValue
getSqrtEstimate(SDValue Operand
, SelectionDAG
&DAG
,
3977 int Enabled
, int &RefinementSteps
,
3978 bool &UseOneConstNR
, bool Reciprocal
) const {
3982 /// Return a reciprocal estimate value for the input operand.
3983 /// \p Enabled is a ReciprocalEstimate enum with value either 'Unspecified' or
3984 /// 'Enabled' as set by a potential default override attribute.
3985 /// If \p RefinementSteps is 'Unspecified', the number of Newton-Raphson
3986 /// refinement iterations required to generate a sufficient (though not
3987 /// necessarily IEEE-754 compliant) estimate is returned in that parameter.
3988 /// A target may choose to implement its own refinement within this function.
3989 /// If that's true, then return '0' as the number of RefinementSteps to avoid
3990 /// any further refinement of the estimate.
3991 /// An empty SDValue return means no estimate sequence can be created.
3992 virtual SDValue
getRecipEstimate(SDValue Operand
, SelectionDAG
&DAG
,
3993 int Enabled
, int &RefinementSteps
) const {
3997 //===--------------------------------------------------------------------===//
3998 // Legalization utility functions
4001 /// Expand a MUL or [US]MUL_LOHI of n-bit values into two or four nodes,
4002 /// respectively, each computing an n/2-bit part of the result.
4003 /// \param Result A vector that will be filled with the parts of the result
4004 /// in little-endian order.
4005 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
4006 /// if you want to control how low bits are extracted from the LHS.
4007 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4008 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4009 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4010 /// \returns true if the node has been expanded, false if it has not
4011 bool expandMUL_LOHI(unsigned Opcode
, EVT VT
, SDLoc dl
, SDValue LHS
,
4012 SDValue RHS
, SmallVectorImpl
<SDValue
> &Result
, EVT HiLoVT
,
4013 SelectionDAG
&DAG
, MulExpansionKind Kind
,
4014 SDValue LL
= SDValue(), SDValue LH
= SDValue(),
4015 SDValue RL
= SDValue(), SDValue RH
= SDValue()) const;
4017 /// Expand a MUL into two nodes. One that computes the high bits of
4018 /// the result and one that computes the low bits.
4019 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
4020 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
4021 /// if you want to control how low bits are extracted from the LHS.
4022 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
4023 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
4024 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
4025 /// \returns true if the node has been expanded. false if it has not
4026 bool expandMUL(SDNode
*N
, SDValue
&Lo
, SDValue
&Hi
, EVT HiLoVT
,
4027 SelectionDAG
&DAG
, MulExpansionKind Kind
,
4028 SDValue LL
= SDValue(), SDValue LH
= SDValue(),
4029 SDValue RL
= SDValue(), SDValue RH
= SDValue()) const;
4031 /// Expand funnel shift.
4032 /// \param N Node to expand
4033 /// \param Result output after conversion
4034 /// \returns True, if the expansion was successful, false otherwise
4035 bool expandFunnelShift(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4037 /// Expand rotations.
4038 /// \param N Node to expand
4039 /// \param Result output after conversion
4040 /// \returns True, if the expansion was successful, false otherwise
4041 bool expandROT(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4043 /// Expand float(f32) to SINT(i64) conversion
4044 /// \param N Node to expand
4045 /// \param Result output after conversion
4046 /// \returns True, if the expansion was successful, false otherwise
4047 bool expandFP_TO_SINT(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4049 /// Expand float to UINT conversion
4050 /// \param N Node to expand
4051 /// \param Result output after conversion
4052 /// \returns True, if the expansion was successful, false otherwise
4053 bool expandFP_TO_UINT(SDNode
*N
, SDValue
&Result
, SDValue
&Chain
, SelectionDAG
&DAG
) const;
4055 /// Expand UINT(i64) to double(f64) conversion
4056 /// \param N Node to expand
4057 /// \param Result output after conversion
4058 /// \returns True, if the expansion was successful, false otherwise
4059 bool expandUINT_TO_FP(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4061 /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs.
4062 SDValue
expandFMINNUM_FMAXNUM(SDNode
*N
, SelectionDAG
&DAG
) const;
4064 /// Expand CTPOP nodes. Expands vector/scalar CTPOP nodes,
4065 /// vector nodes can only succeed if all operations are legal/custom.
4066 /// \param N Node to expand
4067 /// \param Result output after conversion
4068 /// \returns True, if the expansion was successful, false otherwise
4069 bool expandCTPOP(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4071 /// Expand CTLZ/CTLZ_ZERO_UNDEF nodes. Expands vector/scalar CTLZ nodes,
4072 /// vector nodes can only succeed if all operations are legal/custom.
4073 /// \param N Node to expand
4074 /// \param Result output after conversion
4075 /// \returns True, if the expansion was successful, false otherwise
4076 bool expandCTLZ(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4078 /// Expand CTTZ/CTTZ_ZERO_UNDEF nodes. Expands vector/scalar CTTZ nodes,
4079 /// vector nodes can only succeed if all operations are legal/custom.
4080 /// \param N Node to expand
4081 /// \param Result output after conversion
4082 /// \returns True, if the expansion was successful, false otherwise
4083 bool expandCTTZ(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4085 /// Expand ABS nodes. Expands vector/scalar ABS nodes,
4086 /// vector nodes can only succeed if all operations are legal/custom.
4087 /// (ABS x) -> (XOR (ADD x, (SRA x, type_size)), (SRA x, type_size))
4088 /// \param N Node to expand
4089 /// \param Result output after conversion
4090 /// \returns True, if the expansion was successful, false otherwise
4091 bool expandABS(SDNode
*N
, SDValue
&Result
, SelectionDAG
&DAG
) const;
4093 /// Turn load of vector type into a load of the individual elements.
4094 /// \param LD load to expand
4095 /// \returns MERGE_VALUEs of the scalar loads with their chains.
4096 SDValue
scalarizeVectorLoad(LoadSDNode
*LD
, SelectionDAG
&DAG
) const;
4098 // Turn a store of a vector type into stores of the individual elements.
4099 /// \param ST Store with a vector value type
4100 /// \returns MERGE_VALUs of the individual store chains.
4101 SDValue
scalarizeVectorStore(StoreSDNode
*ST
, SelectionDAG
&DAG
) const;
4103 /// Expands an unaligned load to 2 half-size loads for an integer, and
4104 /// possibly more for vectors.
4105 std::pair
<SDValue
, SDValue
> expandUnalignedLoad(LoadSDNode
*LD
,
4106 SelectionDAG
&DAG
) const;
4108 /// Expands an unaligned store to 2 half-size stores for integer values, and
4109 /// possibly more for vectors.
4110 SDValue
expandUnalignedStore(StoreSDNode
*ST
, SelectionDAG
&DAG
) const;
4112 /// Increments memory address \p Addr according to the type of the value
4113 /// \p DataVT that should be stored. If the data is stored in compressed
4114 /// form, the memory address should be incremented according to the number of
4115 /// the stored elements. This number is equal to the number of '1's bits
4117 /// \p DataVT is a vector type. \p Mask is a vector value.
4118 /// \p DataVT and \p Mask have the same number of vector elements.
4119 SDValue
IncrementMemoryAddress(SDValue Addr
, SDValue Mask
, const SDLoc
&DL
,
4120 EVT DataVT
, SelectionDAG
&DAG
,
4121 bool IsCompressedMemory
) const;
4123 /// Get a pointer to vector element \p Idx located in memory for a vector of
4124 /// type \p VecVT starting at a base address of \p VecPtr. If \p Idx is out of
4125 /// bounds the returned pointer is unspecified, but will be within the vector
4127 SDValue
getVectorElementPointer(SelectionDAG
&DAG
, SDValue VecPtr
, EVT VecVT
,
4128 SDValue Index
) const;
4130 /// Method for building the DAG expansion of ISD::[US][ADD|SUB]SAT. This
4131 /// method accepts integers as its arguments.
4132 SDValue
expandAddSubSat(SDNode
*Node
, SelectionDAG
&DAG
) const;
4134 /// Method for building the DAG expansion of ISD::[U|S]MULFIX[SAT]. This
4135 /// method accepts integers as its arguments.
4136 SDValue
expandFixedPointMul(SDNode
*Node
, SelectionDAG
&DAG
) const;
4138 /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion
4139 /// always suceeds and populates the Result and Overflow arguments.
4140 void expandUADDSUBO(SDNode
*Node
, SDValue
&Result
, SDValue
&Overflow
,
4141 SelectionDAG
&DAG
) const;
4143 /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion
4144 /// always suceeds and populates the Result and Overflow arguments.
4145 void expandSADDSUBO(SDNode
*Node
, SDValue
&Result
, SDValue
&Overflow
,
4146 SelectionDAG
&DAG
) const;
4148 /// Method for building the DAG expansion of ISD::[US]MULO. Returns whether
4149 /// expansion was successful and populates the Result and Overflow arguments.
4150 bool expandMULO(SDNode
*Node
, SDValue
&Result
, SDValue
&Overflow
,
4151 SelectionDAG
&DAG
) const;
4153 /// Expand a VECREDUCE_* into an explicit calculation. If Count is specified,
4154 /// only the first Count elements of the vector are used.
4155 SDValue
expandVecReduce(SDNode
*Node
, SelectionDAG
&DAG
) const;
4157 //===--------------------------------------------------------------------===//
4158 // Instruction Emitting Hooks
4161 /// This method should be implemented by targets that mark instructions with
4162 /// the 'usesCustomInserter' flag. These instructions are special in various
4163 /// ways, which require special support to insert. The specified MachineInstr
4164 /// is created but not inserted into any basic blocks, and this method is
4165 /// called to expand it into a sequence of instructions, potentially also
4166 /// creating new basic blocks and control flow.
4167 /// As long as the returned basic block is different (i.e., we created a new
4168 /// one), the custom inserter is free to modify the rest of \p MBB.
4169 virtual MachineBasicBlock
*
4170 EmitInstrWithCustomInserter(MachineInstr
&MI
, MachineBasicBlock
*MBB
) const;
4172 /// This method should be implemented by targets that mark instructions with
4173 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
4174 /// instruction selection by target hooks. e.g. To fill in optional defs for
4175 /// ARM 's' setting instructions.
4176 virtual void AdjustInstrPostInstrSelection(MachineInstr
&MI
,
4177 SDNode
*Node
) const;
4179 /// If this function returns true, SelectionDAGBuilder emits a
4180 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
4181 virtual bool useLoadStackGuardNode() const {
4185 virtual SDValue
emitStackGuardXorFP(SelectionDAG
&DAG
, SDValue Val
,
4186 const SDLoc
&DL
) const {
4187 llvm_unreachable("not implemented for this target");
4190 /// Lower TLS global address SDNode for target independent emulated TLS model.
4191 virtual SDValue
LowerToTLSEmulatedModel(const GlobalAddressSDNode
*GA
,
4192 SelectionDAG
&DAG
) const;
4194 /// Expands target specific indirect branch for the case of JumpTable
4196 virtual SDValue
expandIndirectJTBranch(const SDLoc
& dl
, SDValue Value
, SDValue Addr
,
4197 SelectionDAG
&DAG
) const {
4198 return DAG
.getNode(ISD::BRIND
, dl
, MVT::Other
, Value
, Addr
);
4201 // seteq(x, 0) -> truncate(srl(ctlz(zext(x)), log2(#bits)))
4202 // If we're comparing for equality to zero and isCtlzFast is true, expose the
4203 // fact that this can be implemented as a ctlz/srl pair, so that the dag
4204 // combiner can fold the new nodes.
4205 SDValue
lowerCmpEqZeroToCtlzSrl(SDValue Op
, SelectionDAG
&DAG
) const;
4208 SDValue
foldSetCCWithAnd(EVT VT
, SDValue N0
, SDValue N1
, ISD::CondCode Cond
,
4209 const SDLoc
&DL
, DAGCombinerInfo
&DCI
) const;
4210 SDValue
foldSetCCWithBinOp(EVT VT
, SDValue N0
, SDValue N1
, ISD::CondCode Cond
,
4211 const SDLoc
&DL
, DAGCombinerInfo
&DCI
) const;
4213 SDValue
optimizeSetCCOfSignedTruncationCheck(EVT SCCVT
, SDValue N0
,
4214 SDValue N1
, ISD::CondCode Cond
,
4215 DAGCombinerInfo
&DCI
,
4216 const SDLoc
&DL
) const;
4218 // (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0
4219 SDValue
optimizeSetCCByHoistingAndByConstFromLogicalShift(
4220 EVT SCCVT
, SDValue N0
, SDValue N1C
, ISD::CondCode Cond
,
4221 DAGCombinerInfo
&DCI
, const SDLoc
&DL
) const;
4223 SDValue
prepareUREMEqFold(EVT SETCCVT
, SDValue REMNode
,
4224 SDValue CompTargetNode
, ISD::CondCode Cond
,
4225 DAGCombinerInfo
&DCI
, const SDLoc
&DL
,
4226 SmallVectorImpl
<SDNode
*> &Created
) const;
4227 SDValue
buildUREMEqFold(EVT SETCCVT
, SDValue REMNode
, SDValue CompTargetNode
,
4228 ISD::CondCode Cond
, DAGCombinerInfo
&DCI
,
4229 const SDLoc
&DL
) const;
4231 SDValue
prepareSREMEqFold(EVT SETCCVT
, SDValue REMNode
,
4232 SDValue CompTargetNode
, ISD::CondCode Cond
,
4233 DAGCombinerInfo
&DCI
, const SDLoc
&DL
,
4234 SmallVectorImpl
<SDNode
*> &Created
) const;
4235 SDValue
buildSREMEqFold(EVT SETCCVT
, SDValue REMNode
, SDValue CompTargetNode
,
4236 ISD::CondCode Cond
, DAGCombinerInfo
&DCI
,
4237 const SDLoc
&DL
) const;
4240 /// Given an LLVM IR type and return type attributes, compute the return value
4241 /// EVTs and flags, and optionally also the offsets, if the return value is
4242 /// being lowered to memory.
4243 void GetReturnInfo(CallingConv::ID CC
, Type
*ReturnType
, AttributeList attr
,
4244 SmallVectorImpl
<ISD::OutputArg
> &Outs
,
4245 const TargetLowering
&TLI
, const DataLayout
&DL
);
4247 } // end namespace llvm
4249 #endif // LLVM_CODEGEN_TARGETLOWERING_H