1 //===- IntrinsicsAMDGPU.td - Defines AMDGPU intrinsics -----*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines all of the R600-specific intrinsics.
11 //===----------------------------------------------------------------------===//
13 class AMDGPUReadPreloadRegisterIntrinsic
14 : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>;
16 class AMDGPUReadPreloadRegisterIntrinsicNamed<string name>
17 : Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>, GCCBuiltin<name>;
19 // Used to tag image and resource intrinsics with information used to generate
21 class AMDGPURsrcIntrinsic<int rsrcarg, bit isimage = 0> {
22 int RsrcArg = rsrcarg;
23 bit IsImage = isimage;
26 let TargetPrefix = "r600" in {
28 multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz {
29 def _x : AMDGPUReadPreloadRegisterIntrinsic;
30 def _y : AMDGPUReadPreloadRegisterIntrinsic;
31 def _z : AMDGPUReadPreloadRegisterIntrinsic;
34 multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz_named<string prefix> {
35 def _x : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_x")>;
36 def _y : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_y")>;
37 def _z : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_z")>;
40 defm int_r600_read_global_size : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
41 <"__builtin_r600_read_global_size">;
42 defm int_r600_read_ngroups : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
43 <"__builtin_r600_read_ngroups">;
44 defm int_r600_read_tgid : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
45 <"__builtin_r600_read_tgid">;
47 defm int_r600_read_local_size : AMDGPUReadPreloadRegisterIntrinsic_xyz;
48 defm int_r600_read_tidig : AMDGPUReadPreloadRegisterIntrinsic_xyz;
50 def int_r600_group_barrier : GCCBuiltin<"__builtin_r600_group_barrier">,
51 Intrinsic<[], [], [IntrConvergent]>;
53 // AS 7 is PARAM_I_ADDRESS, used for kernel arguments
54 def int_r600_implicitarg_ptr :
55 GCCBuiltin<"__builtin_r600_implicitarg_ptr">,
56 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 7>], [],
57 [IntrNoMem, IntrSpeculatable]>;
59 def int_r600_rat_store_typed :
60 // 1st parameter: Data
61 // 2nd parameter: Index
62 // 3rd parameter: Constant RAT ID
63 Intrinsic<[], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], []>,
64 GCCBuiltin<"__builtin_r600_rat_store_typed">;
66 def int_r600_recipsqrt_ieee : Intrinsic<
67 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
70 def int_r600_recipsqrt_clamped : Intrinsic<
71 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
74 def int_r600_cube : Intrinsic<
75 [llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem, IntrSpeculatable]
78 def int_r600_store_stream_output : Intrinsic<
79 [], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []
82 class TextureIntrinsicFloatInput : Intrinsic<[llvm_v4f32_ty], [
83 llvm_v4f32_ty, // Coord
84 llvm_i32_ty, // offset_x
85 llvm_i32_ty, // offset_y,
86 llvm_i32_ty, // offset_z,
87 llvm_i32_ty, // resource_id
88 llvm_i32_ty, // samplerid
89 llvm_i32_ty, // coord_type_x
90 llvm_i32_ty, // coord_type_y
91 llvm_i32_ty, // coord_type_z
92 llvm_i32_ty], // coord_type_w
96 class TextureIntrinsicInt32Input : Intrinsic<[llvm_v4i32_ty], [
97 llvm_v4i32_ty, // Coord
98 llvm_i32_ty, // offset_x
99 llvm_i32_ty, // offset_y,
100 llvm_i32_ty, // offset_z,
101 llvm_i32_ty, // resource_id
102 llvm_i32_ty, // samplerid
103 llvm_i32_ty, // coord_type_x
104 llvm_i32_ty, // coord_type_y
105 llvm_i32_ty, // coord_type_z
106 llvm_i32_ty], // coord_type_w
110 def int_r600_store_swizzle :
111 Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []
114 def int_r600_tex : TextureIntrinsicFloatInput;
115 def int_r600_texc : TextureIntrinsicFloatInput;
116 def int_r600_txl : TextureIntrinsicFloatInput;
117 def int_r600_txlc : TextureIntrinsicFloatInput;
118 def int_r600_txb : TextureIntrinsicFloatInput;
119 def int_r600_txbc : TextureIntrinsicFloatInput;
120 def int_r600_txf : TextureIntrinsicInt32Input;
121 def int_r600_txq : TextureIntrinsicInt32Input;
122 def int_r600_ddx : TextureIntrinsicFloatInput;
123 def int_r600_ddy : TextureIntrinsicFloatInput;
125 def int_r600_dot4 : Intrinsic<[llvm_float_ty],
126 [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem, IntrSpeculatable]
129 def int_r600_kill : Intrinsic<[], [llvm_float_ty], []>;
131 } // End TargetPrefix = "r600"
133 let TargetPrefix = "amdgcn" in {
135 //===----------------------------------------------------------------------===//
136 // ABI Special Intrinsics
137 //===----------------------------------------------------------------------===//
139 defm int_amdgcn_workitem_id : AMDGPUReadPreloadRegisterIntrinsic_xyz;
140 defm int_amdgcn_workgroup_id : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
141 <"__builtin_amdgcn_workgroup_id">;
143 def int_amdgcn_dispatch_ptr :
144 GCCBuiltin<"__builtin_amdgcn_dispatch_ptr">,
145 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [],
146 [IntrNoMem, IntrSpeculatable]>;
148 def int_amdgcn_queue_ptr :
149 GCCBuiltin<"__builtin_amdgcn_queue_ptr">,
150 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [],
151 [IntrNoMem, IntrSpeculatable]>;
153 def int_amdgcn_kernarg_segment_ptr :
154 GCCBuiltin<"__builtin_amdgcn_kernarg_segment_ptr">,
155 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [],
156 [IntrNoMem, IntrSpeculatable]>;
158 def int_amdgcn_implicitarg_ptr :
159 GCCBuiltin<"__builtin_amdgcn_implicitarg_ptr">,
160 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [],
161 [IntrNoMem, IntrSpeculatable]>;
163 def int_amdgcn_groupstaticsize :
164 GCCBuiltin<"__builtin_amdgcn_groupstaticsize">,
165 Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>;
167 def int_amdgcn_dispatch_id :
168 GCCBuiltin<"__builtin_amdgcn_dispatch_id">,
169 Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable]>;
171 def int_amdgcn_implicit_buffer_ptr :
172 GCCBuiltin<"__builtin_amdgcn_implicit_buffer_ptr">,
173 Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [],
174 [IntrNoMem, IntrSpeculatable]>;
176 // Set EXEC to the 64-bit value given.
177 // This is always moved to the beginning of the basic block.
178 // FIXME: Should be mangled for wave size.
179 def int_amdgcn_init_exec : Intrinsic<[],
180 [llvm_i64_ty], // 64-bit literal constant
181 [IntrConvergent, ImmArg<0>]>;
183 // Set EXEC according to a thread count packed in an SGPR input:
184 // thread_count = (input >> bitoffset) & 0x7f;
185 // This is always moved to the beginning of the basic block.
186 def int_amdgcn_init_exec_from_input : Intrinsic<[],
187 [llvm_i32_ty, // 32-bit SGPR input
188 llvm_i32_ty], // bit offset of the thread count
189 [IntrConvergent, ImmArg<1>]>;
191 def int_amdgcn_wavefrontsize :
192 GCCBuiltin<"__builtin_amdgcn_wavefrontsize">,
193 Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>;
196 //===----------------------------------------------------------------------===//
197 // Instruction Intrinsics
198 //===----------------------------------------------------------------------===//
200 // The first parameter is s_sendmsg immediate (i16),
201 // the second one is copied to m0
202 def int_amdgcn_s_sendmsg : GCCBuiltin<"__builtin_amdgcn_s_sendmsg">,
203 Intrinsic <[], [llvm_i32_ty, llvm_i32_ty],
204 [ImmArg<0>, IntrNoMem, IntrHasSideEffects]>;
205 def int_amdgcn_s_sendmsghalt : GCCBuiltin<"__builtin_amdgcn_s_sendmsghalt">,
206 Intrinsic <[], [llvm_i32_ty, llvm_i32_ty],
207 [ImmArg<0>, IntrNoMem, IntrHasSideEffects]>;
209 def int_amdgcn_s_barrier : GCCBuiltin<"__builtin_amdgcn_s_barrier">,
210 Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects, IntrConvergent]>;
212 def int_amdgcn_wave_barrier : GCCBuiltin<"__builtin_amdgcn_wave_barrier">,
213 Intrinsic<[], [], [IntrConvergent]>;
215 def int_amdgcn_s_waitcnt : GCCBuiltin<"__builtin_amdgcn_s_waitcnt">,
216 Intrinsic<[], [llvm_i32_ty], [ImmArg<0>]>;
218 def int_amdgcn_div_scale : Intrinsic<
219 // 1st parameter: Numerator
220 // 2nd parameter: Denominator
221 // 3rd parameter: Constant to select select between first and
222 // second. (0 = first, 1 = second).
223 [llvm_anyfloat_ty, llvm_i1_ty],
224 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
225 [IntrNoMem, IntrSpeculatable, ImmArg<2>]
228 def int_amdgcn_div_fmas : Intrinsic<[llvm_anyfloat_ty],
229 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
230 [IntrNoMem, IntrSpeculatable]
233 def int_amdgcn_div_fixup : Intrinsic<[llvm_anyfloat_ty],
234 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
235 [IntrNoMem, IntrSpeculatable]
238 def int_amdgcn_trig_preop : Intrinsic<
239 [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty],
240 [IntrNoMem, IntrSpeculatable]
243 def int_amdgcn_sin : Intrinsic<
244 [llvm_anyfloat_ty], [LLVMMatchType<0>],
245 [IntrNoMem, IntrSpeculatable]
248 def int_amdgcn_cos : Intrinsic<
249 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
252 def int_amdgcn_log_clamp : Intrinsic<
253 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
256 def int_amdgcn_fmul_legacy : GCCBuiltin<"__builtin_amdgcn_fmul_legacy">,
257 Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty],
258 [IntrNoMem, IntrSpeculatable]
261 def int_amdgcn_rcp : Intrinsic<
262 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
265 def int_amdgcn_rcp_legacy : GCCBuiltin<"__builtin_amdgcn_rcp_legacy">,
266 Intrinsic<[llvm_float_ty], [llvm_float_ty],
267 [IntrNoMem, IntrSpeculatable]
270 def int_amdgcn_rsq : Intrinsic<
271 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
274 def int_amdgcn_rsq_legacy : GCCBuiltin<"__builtin_amdgcn_rsq_legacy">,
276 [llvm_float_ty], [llvm_float_ty], [IntrNoMem, IntrSpeculatable]
279 def int_amdgcn_rsq_clamp : Intrinsic<
280 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]>;
282 def int_amdgcn_ldexp : Intrinsic<
283 [llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty],
284 [IntrNoMem, IntrSpeculatable]
287 def int_amdgcn_frexp_mant : Intrinsic<
288 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
291 def int_amdgcn_frexp_exp : Intrinsic<
292 [llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem, IntrSpeculatable]
295 // v_fract is buggy on SI/CI. It mishandles infinities, may return 1.0
296 // and always uses rtz, so is not suitable for implementing the OpenCL
297 // fract function. It should be ok on VI.
298 def int_amdgcn_fract : Intrinsic<
299 [llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
302 def int_amdgcn_cvt_pkrtz : GCCBuiltin<"__builtin_amdgcn_cvt_pkrtz">,
303 Intrinsic<[llvm_v2f16_ty], [llvm_float_ty, llvm_float_ty],
304 [IntrNoMem, IntrSpeculatable]
307 def int_amdgcn_cvt_pknorm_i16 :
308 GCCBuiltin<"__builtin_amdgcn_cvt_pknorm_i16">,
309 Intrinsic<[llvm_v2i16_ty], [llvm_float_ty, llvm_float_ty],
310 [IntrNoMem, IntrSpeculatable]
313 def int_amdgcn_cvt_pknorm_u16 :
314 GCCBuiltin<"__builtin_amdgcn_cvt_pknorm_u16">,
315 Intrinsic<[llvm_v2i16_ty], [llvm_float_ty, llvm_float_ty],
316 [IntrNoMem, IntrSpeculatable]
319 def int_amdgcn_cvt_pk_i16 :
320 GCCBuiltin<"__builtin_amdgcn_cvt_pk_i16">,
322 [llvm_v2i16_ty], [llvm_i32_ty, llvm_i32_ty],
323 [IntrNoMem, IntrSpeculatable]
326 def int_amdgcn_cvt_pk_u16 : GCCBuiltin<"__builtin_amdgcn_cvt_pk_u16">,
327 Intrinsic<[llvm_v2i16_ty], [llvm_i32_ty, llvm_i32_ty],
328 [IntrNoMem, IntrSpeculatable]
331 def int_amdgcn_class : Intrinsic<
332 [llvm_i1_ty], [llvm_anyfloat_ty, llvm_i32_ty],
333 [IntrNoMem, IntrSpeculatable]
336 def int_amdgcn_fmed3 : GCCBuiltin<"__builtin_amdgcn_fmed3">,
337 Intrinsic<[llvm_anyfloat_ty],
338 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
339 [IntrNoMem, IntrSpeculatable]
342 def int_amdgcn_cubeid : GCCBuiltin<"__builtin_amdgcn_cubeid">,
343 Intrinsic<[llvm_float_ty],
344 [llvm_float_ty, llvm_float_ty, llvm_float_ty],
345 [IntrNoMem, IntrSpeculatable]
348 def int_amdgcn_cubema : GCCBuiltin<"__builtin_amdgcn_cubema">,
349 Intrinsic<[llvm_float_ty],
350 [llvm_float_ty, llvm_float_ty, llvm_float_ty],
351 [IntrNoMem, IntrSpeculatable]
354 def int_amdgcn_cubesc : GCCBuiltin<"__builtin_amdgcn_cubesc">,
355 Intrinsic<[llvm_float_ty],
356 [llvm_float_ty, llvm_float_ty, llvm_float_ty],
357 [IntrNoMem, IntrSpeculatable]
360 def int_amdgcn_cubetc : GCCBuiltin<"__builtin_amdgcn_cubetc">,
361 Intrinsic<[llvm_float_ty],
362 [llvm_float_ty, llvm_float_ty, llvm_float_ty],
363 [IntrNoMem, IntrSpeculatable]
366 // v_ffbh_i32, as opposed to v_ffbh_u32. For v_ffbh_u32, llvm.ctlz
368 def int_amdgcn_sffbh :
369 Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>],
370 [IntrNoMem, IntrSpeculatable]
373 // v_mad_f32|f16/v_mac_f32|f16, selected regardless of denorm support.
374 def int_amdgcn_fmad_ftz :
375 Intrinsic<[llvm_anyfloat_ty],
376 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
377 [IntrNoMem, IntrSpeculatable]
380 // Fields should mirror atomicrmw
381 class AMDGPUAtomicIncIntrin : Intrinsic<[llvm_anyint_ty],
384 llvm_i32_ty, // ordering
385 llvm_i32_ty, // scope
386 llvm_i1_ty], // isVolatile
387 [IntrArgMemOnly, NoCapture<0>, ImmArg<2>, ImmArg<3>, ImmArg<4>], "",
391 def int_amdgcn_atomic_inc : AMDGPUAtomicIncIntrin;
392 def int_amdgcn_atomic_dec : AMDGPUAtomicIncIntrin;
394 class AMDGPULDSF32Intrin<string clang_builtin> :
395 GCCBuiltin<clang_builtin>,
396 Intrinsic<[llvm_float_ty],
397 [LLVMQualPointerType<llvm_float_ty, 3>,
399 llvm_i32_ty, // ordering
400 llvm_i32_ty, // scope
401 llvm_i1_ty], // isVolatile
402 [IntrArgMemOnly, NoCapture<0>, ImmArg<2>, ImmArg<3>, ImmArg<4>]
405 // FIXME: The m0 argument should be moved after the normal arguments
406 class AMDGPUDSOrderedIntrinsic : Intrinsic<
408 // M0 = {hi16:address, lo16:waveID}. Allow passing M0 as a pointer, so that
409 // the bit packing can be optimized at the IR level.
410 [LLVMQualPointerType<llvm_i32_ty, 2>, // IntToPtr(M0)
411 llvm_i32_ty, // value to add or swap
412 llvm_i32_ty, // ordering
413 llvm_i32_ty, // scope
414 llvm_i1_ty, // isVolatile
415 llvm_i32_ty, // ordered count index (OA index), also added to the address
416 // gfx10: bits 24-27 indicate the number of active threads/dwords
417 llvm_i1_ty, // wave release, usually set to 1
418 llvm_i1_ty], // wave done, set to 1 for the last ordered instruction
420 ImmArg<2>, ImmArg<3>, ImmArg<4>,
421 ImmArg<5>, ImmArg<6>, ImmArg<7>
425 class AMDGPUDSAppendConsumedIntrinsic : Intrinsic<
427 [llvm_anyptr_ty, // LDS or GDS ptr
428 llvm_i1_ty], // isVolatile
429 [IntrConvergent, IntrArgMemOnly, NoCapture<0>, ImmArg<1>],
434 def int_amdgcn_ds_ordered_add : AMDGPUDSOrderedIntrinsic;
435 def int_amdgcn_ds_ordered_swap : AMDGPUDSOrderedIntrinsic;
437 // The pointer argument is assumed to be dynamically uniform if a VGPR.
438 def int_amdgcn_ds_append : AMDGPUDSAppendConsumedIntrinsic;
439 def int_amdgcn_ds_consume : AMDGPUDSAppendConsumedIntrinsic;
441 def int_amdgcn_ds_fadd : AMDGPULDSF32Intrin<"__builtin_amdgcn_ds_faddf">;
442 def int_amdgcn_ds_fmin : AMDGPULDSF32Intrin<"__builtin_amdgcn_ds_fminf">;
443 def int_amdgcn_ds_fmax : AMDGPULDSF32Intrin<"__builtin_amdgcn_ds_fmaxf">;
445 } // TargetPrefix = "amdgcn"
447 // New-style image intrinsics
449 //////////////////////////////////////////////////////////////////////////
450 // Dimension-aware image intrinsics framework
451 //////////////////////////////////////////////////////////////////////////
453 // Helper class to represent (type, name) combinations of arguments. The
454 // argument names are explanatory and used as DAG operand names for codegen
456 class AMDGPUArg<LLVMType ty, string name> {
461 // Return [AMDGPUArg<basety, names[0]>, AMDGPUArg<LLVMMatchType<0>, names[1]>, ...]
462 class makeArgList<list<string> names, LLVMType basety> {
463 list<AMDGPUArg> ret =
464 !listconcat([AMDGPUArg<basety, names[0]>],
465 !foreach(name, !tail(names), AMDGPUArg<LLVMMatchType<0>, name>));
468 // Return arglist, with LLVMMatchType's references shifted by 'shift'.
469 class arglistmatchshift<list<AMDGPUArg> arglist, int shift> {
470 list<AMDGPUArg> ret =
471 !foreach(arg, arglist,
472 !if(!isa<LLVMMatchType>(arg.Type),
473 AMDGPUArg<LLVMMatchType<!add(!cast<LLVMMatchType>(arg.Type).Number, shift)>,
478 // Return the concatenation of the given arglists. LLVMMatchType's are adjusted
479 // accordingly, and shifted by an additional 'shift'.
480 class arglistconcat<list<list<AMDGPUArg>> arglists, int shift = 0> {
481 list<AMDGPUArg> ret =
482 !foldl([]<AMDGPUArg>, arglists, lhs, rhs,
485 arglistmatchshift<rhs,
486 !add(shift, !foldl(0, lhs, a, b,
487 !add(a, b.Type.isAny)))>.ret));
490 // Represent texture/image types / dimensionality.
491 class AMDGPUDimProps<bits<3> enc, string name, string asmsuffix,
492 list<string> coord_names, list<string> slice_names> {
493 AMDGPUDimProps Dim = !cast<AMDGPUDimProps>(NAME);
494 string Name = name; // e.g. "2darraymsaa"
495 string AsmSuffix = asmsuffix; // e.g. 2D_MSAA_ARRAY (used in assembly strings)
496 bits<3> Encoding = enc;
497 bit DA = 0; // DA bit in MIMG encoding
499 list<AMDGPUArg> CoordSliceArgs =
500 makeArgList<!listconcat(coord_names, slice_names), llvm_anyfloat_ty>.ret;
501 list<AMDGPUArg> CoordSliceIntArgs =
502 makeArgList<!listconcat(coord_names, slice_names), llvm_anyint_ty>.ret;
503 list<AMDGPUArg> GradientArgs =
504 makeArgList<!listconcat(!foreach(name, coord_names, "d" # name # "dh"),
505 !foreach(name, coord_names, "d" # name # "dv")),
506 llvm_anyfloat_ty>.ret;
508 bits<8> NumCoords = !size(CoordSliceArgs);
509 bits<8> NumGradients = !size(GradientArgs);
512 def AMDGPUDim1D : AMDGPUDimProps<0x0, "1d", "1D", ["s"], []>;
513 def AMDGPUDim2D : AMDGPUDimProps<0x1, "2d", "2D", ["s", "t"], []>;
514 def AMDGPUDim3D : AMDGPUDimProps<0x2, "3d", "3D", ["s", "t", "r"], []>;
516 def AMDGPUDimCube : AMDGPUDimProps<0x3, "cube", "CUBE", ["s", "t"], ["face"]>;
517 def AMDGPUDim1DArray : AMDGPUDimProps<0x4, "1darray", "1D_ARRAY", ["s"], ["slice"]>;
518 def AMDGPUDim2DArray : AMDGPUDimProps<0x5, "2darray", "2D_ARRAY", ["s", "t"], ["slice"]>;
520 def AMDGPUDim2DMsaa : AMDGPUDimProps<0x6, "2dmsaa", "2D_MSAA", ["s", "t"], ["fragid"]>;
522 def AMDGPUDim2DArrayMsaa : AMDGPUDimProps<0x7, "2darraymsaa", "2D_MSAA_ARRAY", ["s", "t"], ["slice", "fragid"]>;
526 list<AMDGPUDimProps> NoMsaa = [AMDGPUDim1D, AMDGPUDim2D, AMDGPUDim3D,
527 AMDGPUDimCube, AMDGPUDim1DArray,
529 list<AMDGPUDimProps> Msaa = [AMDGPUDim2DMsaa, AMDGPUDim2DArrayMsaa];
530 list<AMDGPUDimProps> All = !listconcat(NoMsaa, Msaa);
533 // Represent sample variants, i.e. _C, _O, _B, ... and combinations thereof.
534 class AMDGPUSampleVariant<string ucmod, string lcmod, list<AMDGPUArg> extra_addr> {
535 string UpperCaseMod = ucmod;
536 string LowerCaseMod = lcmod;
538 // {offset} {bias} {z-compare}
539 list<AMDGPUArg> ExtraAddrArgs = extra_addr;
542 // Name of the {lod} or {clamp} argument that is appended to the coordinates,
544 string LodOrClamp = "";
547 // AMDGPUSampleVariants: all variants supported by IMAGE_SAMPLE
548 // AMDGPUSampleVariantsNoGradients: variants supported by IMAGE_GATHER4
549 defset list<AMDGPUSampleVariant> AMDGPUSampleVariants = {
550 multiclass AMDGPUSampleHelper_Offset<string ucmod, string lcmod,
551 list<AMDGPUArg> extra_addr> {
552 def NAME#lcmod : AMDGPUSampleVariant<ucmod, lcmod, extra_addr>;
553 def NAME#lcmod#_o : AMDGPUSampleVariant<
554 ucmod#"_O", lcmod#"_o", !listconcat([AMDGPUArg<llvm_i32_ty, "offset">], extra_addr)>;
557 multiclass AMDGPUSampleHelper_Compare<string ucmod, string lcmod,
558 list<AMDGPUArg> extra_addr> {
559 defm NAME : AMDGPUSampleHelper_Offset<ucmod, lcmod, extra_addr>;
560 defm NAME : AMDGPUSampleHelper_Offset<
561 "_C"#ucmod, "_c"#lcmod, !listconcat(extra_addr, [AMDGPUArg<llvm_float_ty, "zcompare">])>;
564 multiclass AMDGPUSampleHelper_Clamp<string ucmod, string lcmod,
565 list<AMDGPUArg> extra_addr> {
566 defm NAME : AMDGPUSampleHelper_Compare<ucmod, lcmod, extra_addr>;
567 let LodOrClamp = "clamp" in
568 defm NAME : AMDGPUSampleHelper_Compare<ucmod#"_CL", lcmod#"_cl", extra_addr>;
571 defset list<AMDGPUSampleVariant> AMDGPUSampleVariantsNoGradients = {
572 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"", "", []>;
573 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<
574 "_B", "_b", [AMDGPUArg<llvm_anyfloat_ty, "bias">]>;
575 let LodOrClamp = "lod" in
576 defm AMDGPUSample : AMDGPUSampleHelper_Compare<"_L", "_l", []>;
577 defm AMDGPUSample : AMDGPUSampleHelper_Compare<"_LZ", "_lz", []>;
580 let Gradients = 1 in {
581 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"_D", "_d", []>;
582 defm AMDGPUSample : AMDGPUSampleHelper_Clamp<"_CD", "_cd", []>;
586 // Helper class to capture the profile of a dimension-aware image intrinsic.
587 // This information is used to generate the intrinsic's type and to inform
588 // codegen pattern matching.
589 class AMDGPUDimProfile<string opmod,
590 AMDGPUDimProps dim> {
591 AMDGPUDimProps Dim = dim;
592 string OpMod = opmod; // the corresponding instruction is named IMAGE_OpMod
594 // These are entended to be overwritten by subclasses
597 list<LLVMType> RetTypes = [];
598 list<AMDGPUArg> DataArgs = [];
599 list<AMDGPUArg> ExtraAddrArgs = [];
601 string LodClampMip = "";
603 int NumRetAndDataAnyTypes =
604 !foldl(0, !listconcat(RetTypes, !foreach(arg, DataArgs, arg.Type)), a, b,
607 list<AMDGPUArg> AddrArgs =
608 arglistconcat<[ExtraAddrArgs,
609 !if(Gradients, dim.GradientArgs, []),
610 !listconcat(!if(IsSample, dim.CoordSliceArgs, dim.CoordSliceIntArgs),
611 !if(!eq(LodClampMip, ""),
613 [AMDGPUArg<LLVMMatchType<0>, LodClampMip>]))],
614 NumRetAndDataAnyTypes>.ret;
615 list<LLVMType> AddrTypes = !foreach(arg, AddrArgs, arg.Type);
616 list<AMDGPUArg> AddrDefaultArgs =
617 !foreach(arg, AddrArgs,
618 AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)),
619 !if(IsSample, llvm_float_ty, llvm_i32_ty), arg.Type),
621 list<AMDGPUArg> AddrA16Args =
622 !foreach(arg, AddrArgs,
623 AMDGPUArg<!if(!or(arg.Type.isAny, !isa<LLVMMatchType>(arg.Type)),
624 !if(IsSample, llvm_half_ty, llvm_i16_ty), arg.Type),
628 class AMDGPUDimProfileCopy<AMDGPUDimProfile base> : AMDGPUDimProfile<base.OpMod, base.Dim> {
629 let IsSample = base.IsSample;
630 let IsAtomic = base.IsAtomic;
631 let RetTypes = base.RetTypes;
632 let DataArgs = base.DataArgs;
633 let ExtraAddrArgs = base.ExtraAddrArgs;
634 let Gradients = base.Gradients;
635 let LodClampMip = base.LodClampMip;
638 class AMDGPUDimSampleProfile<string opmod,
640 AMDGPUSampleVariant sample> : AMDGPUDimProfile<opmod, dim> {
642 let RetTypes = [llvm_any_ty];
643 let ExtraAddrArgs = sample.ExtraAddrArgs;
644 let Gradients = sample.Gradients;
645 let LodClampMip = sample.LodOrClamp;
648 class AMDGPUDimNoSampleProfile<string opmod,
650 list<LLVMType> retty,
651 list<AMDGPUArg> dataargs,
652 bit Mip = 0> : AMDGPUDimProfile<opmod, dim> {
653 let RetTypes = retty;
654 let DataArgs = dataargs;
655 let LodClampMip = !if(Mip, "mip", "");
658 class AMDGPUDimAtomicProfile<string opmod,
660 list<AMDGPUArg> dataargs> : AMDGPUDimProfile<opmod, dim> {
661 let RetTypes = [llvm_anyint_ty];
662 let DataArgs = dataargs;
666 class AMDGPUDimGetResInfoProfile<AMDGPUDimProps dim> : AMDGPUDimProfile<"GET_RESINFO", dim> {
667 let RetTypes = [llvm_anyfloat_ty];
669 let AddrArgs = [AMDGPUArg<llvm_anyint_ty, "mip">];
670 let LodClampMip = "mip";
673 // Helper class for figuring out image intrinsic argument indexes.
674 class AMDGPUImageDimIntrinsicEval<AMDGPUDimProfile P_> {
675 int NumDataArgs = !size(P_.DataArgs);
676 int NumDmaskArgs = !if(P_.IsAtomic, 0, 1);
677 int NumVAddrArgs = !size(P_.AddrArgs);
679 int NumSampArgs = !if(P_.IsSample, 2, 0);
680 int DmaskArgIndex = NumDataArgs;
681 int UnormArgIndex = !add(NumDataArgs, NumDmaskArgs, NumVAddrArgs, NumRSrcArgs, 1);
682 int TexFailCtrlArgIndex = !add(NumDataArgs, NumDmaskArgs, NumVAddrArgs, NumRSrcArgs, NumSampArgs);
683 int CachePolicyArgIndex = !add(TexFailCtrlArgIndex, 1);
686 // All dimension-aware intrinsics are derived from this class.
687 class AMDGPUImageDimIntrinsic<AMDGPUDimProfile P_,
688 list<IntrinsicProperty> props,
689 list<SDNodeProperty> sdnodeprops> : Intrinsic<
690 P_.RetTypes, // vdata(VGPR) -- for load/atomic-with-return
692 !foreach(arg, P_.DataArgs, arg.Type), // vdata(VGPR) -- for store/atomic
693 !if(P_.IsAtomic, [], [llvm_i32_ty]), // dmask(imm)
694 P_.AddrTypes, // vaddr(VGPR)
695 [llvm_v8i32_ty], // rsrc(SGPR)
696 !if(P_.IsSample, [llvm_v4i32_ty, // samp(SGPR)
697 llvm_i1_ty], []), // unorm(imm)
698 [llvm_i32_ty, // texfailctrl(imm; bit 0 = tfe, bit 1 = lwe)
699 llvm_i32_ty]), // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc)
701 !if(P_.IsAtomic, [], [ImmArg<AMDGPUImageDimIntrinsicEval<P_>.DmaskArgIndex>]),
702 !if(P_.IsSample, [ImmArg<AMDGPUImageDimIntrinsicEval<P_>.UnormArgIndex>], []),
703 [ImmArg<AMDGPUImageDimIntrinsicEval<P_>.TexFailCtrlArgIndex>,
704 ImmArg<AMDGPUImageDimIntrinsicEval<P_>.CachePolicyArgIndex>]),
706 AMDGPURsrcIntrinsic<!add(!size(P_.DataArgs), !size(P_.AddrTypes),
707 !if(P_.IsAtomic, 0, 1)), 1> {
708 AMDGPUDimProfile P = P_;
710 AMDGPUImageDimIntrinsic Intr = !cast<AMDGPUImageDimIntrinsic>(NAME);
712 let TargetPrefix = "amdgcn";
715 // Marker class for intrinsics with a DMask that determines the returned
717 class AMDGPUImageDMaskIntrinsic;
719 defset list<AMDGPUImageDimIntrinsic> AMDGPUImageDimIntrinsics = {
721 //////////////////////////////////////////////////////////////////////////
722 // Load and store intrinsics
723 //////////////////////////////////////////////////////////////////////////
724 multiclass AMDGPUImageDimIntrinsicsNoMsaa<string opmod,
725 list<LLVMType> retty,
726 list<AMDGPUArg> dataargs,
727 list<IntrinsicProperty> props,
728 list<SDNodeProperty> sdnodeprops,
730 foreach dim = AMDGPUDims.NoMsaa in {
731 def !strconcat(NAME, "_", dim.Name)
732 : AMDGPUImageDimIntrinsic<
733 AMDGPUDimNoSampleProfile<opmod, dim, retty, dataargs, Mip>,
738 multiclass AMDGPUImageDimIntrinsicsAll<string opmod,
739 list<LLVMType> retty,
740 list<AMDGPUArg> dataargs,
741 list<IntrinsicProperty> props,
742 list<SDNodeProperty> sdnodeprops,
744 foreach dim = AMDGPUDims.All in {
745 def !strconcat(NAME, "_", dim.Name)
746 : AMDGPUImageDimIntrinsic<
747 AMDGPUDimNoSampleProfile<opmod, dim, retty, dataargs, Mip>,
752 defm int_amdgcn_image_load
753 : AMDGPUImageDimIntrinsicsAll<"LOAD", [llvm_any_ty], [], [IntrReadMem],
755 AMDGPUImageDMaskIntrinsic;
756 defm int_amdgcn_image_load_mip
757 : AMDGPUImageDimIntrinsicsNoMsaa<"LOAD_MIP", [llvm_any_ty], [],
758 [IntrReadMem], [SDNPMemOperand], 1>,
759 AMDGPUImageDMaskIntrinsic;
761 defm int_amdgcn_image_store : AMDGPUImageDimIntrinsicsAll<
762 "STORE", [], [AMDGPUArg<llvm_anyfloat_ty, "vdata">],
763 [IntrWriteMem], [SDNPMemOperand]>;
764 defm int_amdgcn_image_store_mip : AMDGPUImageDimIntrinsicsNoMsaa<
765 "STORE_MIP", [], [AMDGPUArg<llvm_anyfloat_ty, "vdata">],
766 [IntrWriteMem], [SDNPMemOperand], 1>;
768 //////////////////////////////////////////////////////////////////////////
769 // sample and getlod intrinsics
770 //////////////////////////////////////////////////////////////////////////
771 multiclass AMDGPUImageDimSampleDims<string opmod,
772 AMDGPUSampleVariant sample,
774 foreach dim = AMDGPUDims.NoMsaa in {
775 def !strconcat(NAME, "_", dim.Name) : AMDGPUImageDimIntrinsic<
776 AMDGPUDimSampleProfile<opmod, dim, sample>,
777 !if(NoMem, [IntrNoMem], [IntrReadMem]),
778 !if(NoMem, [], [SDNPMemOperand])>;
782 foreach sample = AMDGPUSampleVariants in {
783 defm int_amdgcn_image_sample # sample.LowerCaseMod
784 : AMDGPUImageDimSampleDims<"SAMPLE" # sample.UpperCaseMod, sample>,
785 AMDGPUImageDMaskIntrinsic;
788 defm int_amdgcn_image_getlod
789 : AMDGPUImageDimSampleDims<"GET_LOD", AMDGPUSample, 1>,
790 AMDGPUImageDMaskIntrinsic;
792 //////////////////////////////////////////////////////////////////////////
793 // getresinfo intrinsics
794 //////////////////////////////////////////////////////////////////////////
795 foreach dim = AMDGPUDims.All in {
796 def !strconcat("int_amdgcn_image_getresinfo_", dim.Name)
797 : AMDGPUImageDimIntrinsic<AMDGPUDimGetResInfoProfile<dim>, [IntrNoMem], []>,
798 AMDGPUImageDMaskIntrinsic;
801 //////////////////////////////////////////////////////////////////////////
802 // gather4 intrinsics
803 //////////////////////////////////////////////////////////////////////////
804 foreach sample = AMDGPUSampleVariantsNoGradients in {
805 foreach dim = [AMDGPUDim2D, AMDGPUDimCube, AMDGPUDim2DArray] in {
806 def int_amdgcn_image_gather4 # sample.LowerCaseMod # _ # dim.Name:
807 AMDGPUImageDimIntrinsic<
808 AMDGPUDimSampleProfile<"GATHER4" # sample.UpperCaseMod, dim, sample>,
809 [IntrReadMem], [SDNPMemOperand]>;
814 //////////////////////////////////////////////////////////////////////////
816 //////////////////////////////////////////////////////////////////////////
817 defset list<AMDGPUImageDimIntrinsic> AMDGPUImageDimAtomicIntrinsics = {
818 multiclass AMDGPUImageDimAtomicX<string opmod, list<AMDGPUArg> dataargs> {
819 foreach dim = AMDGPUDims.All in {
820 def !strconcat(NAME, "_", dim.Name)
821 : AMDGPUImageDimIntrinsic<
822 AMDGPUDimAtomicProfile<opmod, dim, dataargs>,
823 [], [SDNPMemOperand]>;
827 multiclass AMDGPUImageDimAtomic<string opmod> {
828 defm "" : AMDGPUImageDimAtomicX<opmod, [AMDGPUArg<LLVMMatchType<0>, "vdata">]>;
831 defm int_amdgcn_image_atomic_swap : AMDGPUImageDimAtomic<"ATOMIC_SWAP">;
832 defm int_amdgcn_image_atomic_add : AMDGPUImageDimAtomic<"ATOMIC_ADD">;
833 defm int_amdgcn_image_atomic_sub : AMDGPUImageDimAtomic<"ATOMIC_SUB">;
834 defm int_amdgcn_image_atomic_smin : AMDGPUImageDimAtomic<"ATOMIC_SMIN">;
835 defm int_amdgcn_image_atomic_umin : AMDGPUImageDimAtomic<"ATOMIC_UMIN">;
836 defm int_amdgcn_image_atomic_smax : AMDGPUImageDimAtomic<"ATOMIC_SMAX">;
837 defm int_amdgcn_image_atomic_umax : AMDGPUImageDimAtomic<"ATOMIC_UMAX">;
838 defm int_amdgcn_image_atomic_and : AMDGPUImageDimAtomic<"ATOMIC_AND">;
839 defm int_amdgcn_image_atomic_or : AMDGPUImageDimAtomic<"ATOMIC_OR">;
840 defm int_amdgcn_image_atomic_xor : AMDGPUImageDimAtomic<"ATOMIC_XOR">;
841 defm int_amdgcn_image_atomic_inc : AMDGPUImageDimAtomic<"ATOMIC_INC">;
842 defm int_amdgcn_image_atomic_dec : AMDGPUImageDimAtomic<"ATOMIC_DEC">;
844 defm int_amdgcn_image_atomic_cmpswap :
845 AMDGPUImageDimAtomicX<"ATOMIC_CMPSWAP", [AMDGPUArg<LLVMMatchType<0>, "src">,
846 AMDGPUArg<LLVMMatchType<0>, "cmp">]>;
849 //////////////////////////////////////////////////////////////////////////
851 //////////////////////////////////////////////////////////////////////////
853 let TargetPrefix = "amdgcn" in {
855 defset list<AMDGPURsrcIntrinsic> AMDGPUBufferIntrinsics = {
857 class AMDGPUBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic <
859 [llvm_v4i32_ty, // rsrc(SGPR)
860 llvm_i32_ty, // vindex(VGPR)
861 llvm_i32_ty, // offset(SGPR/VGPR/imm)
862 llvm_i1_ty, // glc(imm)
863 llvm_i1_ty], // slc(imm)
864 [IntrReadMem, ImmArg<3>, ImmArg<4>], "", [SDNPMemOperand]>,
865 AMDGPURsrcIntrinsic<0>;
866 def int_amdgcn_buffer_load_format : AMDGPUBufferLoad<llvm_anyfloat_ty>;
867 def int_amdgcn_buffer_load : AMDGPUBufferLoad;
869 def int_amdgcn_s_buffer_load : Intrinsic <
871 [llvm_v4i32_ty, // rsrc(SGPR)
872 llvm_i32_ty, // byte offset(SGPR/imm)
873 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 2 = dlc)
874 [IntrNoMem, ImmArg<2>]>,
875 AMDGPURsrcIntrinsic<0>;
877 class AMDGPUBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic <
879 [data_ty, // vdata(VGPR)
880 llvm_v4i32_ty, // rsrc(SGPR)
881 llvm_i32_ty, // vindex(VGPR)
882 llvm_i32_ty, // offset(SGPR/VGPR/imm)
883 llvm_i1_ty, // glc(imm)
884 llvm_i1_ty], // slc(imm)
885 [IntrWriteMem, ImmArg<4>, ImmArg<5>], "", [SDNPMemOperand]>,
886 AMDGPURsrcIntrinsic<1>;
887 def int_amdgcn_buffer_store_format : AMDGPUBufferStore<llvm_anyfloat_ty>;
888 def int_amdgcn_buffer_store : AMDGPUBufferStore;
890 // New buffer intrinsics with separate raw and struct variants. The raw
891 // variant never has an index. The struct variant always has an index, even if
892 // it is const 0. A struct intrinsic with constant 0 index is different to the
893 // corresponding raw intrinsic on gfx9+ because the behavior of bound checking
894 // and swizzling changes depending on whether idxen is set in the instruction.
895 // These new instrinsics also keep the offset and soffset arguments separate as
896 // they behave differently in bounds checking and swizzling.
897 class AMDGPURawBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic <
899 [llvm_v4i32_ty, // rsrc(SGPR)
900 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
901 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
902 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
903 [IntrReadMem, ImmArg<3>], "", [SDNPMemOperand]>,
904 AMDGPURsrcIntrinsic<0>;
905 def int_amdgcn_raw_buffer_load_format : AMDGPURawBufferLoad<llvm_anyfloat_ty>;
906 def int_amdgcn_raw_buffer_load : AMDGPURawBufferLoad;
908 class AMDGPUStructBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic <
910 [llvm_v4i32_ty, // rsrc(SGPR)
911 llvm_i32_ty, // vindex(VGPR)
912 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
913 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
914 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
915 [IntrReadMem, ImmArg<4>], "", [SDNPMemOperand]>,
916 AMDGPURsrcIntrinsic<0>;
917 def int_amdgcn_struct_buffer_load_format : AMDGPUStructBufferLoad<llvm_anyfloat_ty>;
918 def int_amdgcn_struct_buffer_load : AMDGPUStructBufferLoad;
920 class AMDGPURawBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic <
922 [data_ty, // vdata(VGPR)
923 llvm_v4i32_ty, // rsrc(SGPR)
924 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
925 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
926 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
927 [IntrWriteMem, ImmArg<4>], "", [SDNPMemOperand]>,
928 AMDGPURsrcIntrinsic<1>;
929 def int_amdgcn_raw_buffer_store_format : AMDGPURawBufferStore<llvm_anyfloat_ty>;
930 def int_amdgcn_raw_buffer_store : AMDGPURawBufferStore;
932 class AMDGPUStructBufferStore<LLVMType data_ty = llvm_any_ty> : Intrinsic <
934 [data_ty, // vdata(VGPR)
935 llvm_v4i32_ty, // rsrc(SGPR)
936 llvm_i32_ty, // vindex(VGPR)
937 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
938 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
939 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
940 [IntrWriteMem, ImmArg<5>], "", [SDNPMemOperand]>,
941 AMDGPURsrcIntrinsic<1>;
942 def int_amdgcn_struct_buffer_store_format : AMDGPUStructBufferStore<llvm_anyfloat_ty>;
943 def int_amdgcn_struct_buffer_store : AMDGPUStructBufferStore;
945 class AMDGPURawBufferAtomic<LLVMType data_ty = llvm_any_ty> : Intrinsic <
947 [LLVMMatchType<0>, // vdata(VGPR)
948 llvm_v4i32_ty, // rsrc(SGPR)
949 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
950 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
951 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc)
952 [ImmArg<4>], "", [SDNPMemOperand]>,
953 AMDGPURsrcIntrinsic<1, 0>;
954 def int_amdgcn_raw_buffer_atomic_swap : AMDGPURawBufferAtomic;
955 def int_amdgcn_raw_buffer_atomic_add : AMDGPURawBufferAtomic;
956 def int_amdgcn_raw_buffer_atomic_sub : AMDGPURawBufferAtomic;
957 def int_amdgcn_raw_buffer_atomic_smin : AMDGPURawBufferAtomic;
958 def int_amdgcn_raw_buffer_atomic_umin : AMDGPURawBufferAtomic;
959 def int_amdgcn_raw_buffer_atomic_smax : AMDGPURawBufferAtomic;
960 def int_amdgcn_raw_buffer_atomic_umax : AMDGPURawBufferAtomic;
961 def int_amdgcn_raw_buffer_atomic_and : AMDGPURawBufferAtomic;
962 def int_amdgcn_raw_buffer_atomic_or : AMDGPURawBufferAtomic;
963 def int_amdgcn_raw_buffer_atomic_xor : AMDGPURawBufferAtomic;
964 def int_amdgcn_raw_buffer_atomic_inc : AMDGPURawBufferAtomic;
965 def int_amdgcn_raw_buffer_atomic_dec : AMDGPURawBufferAtomic;
966 def int_amdgcn_raw_buffer_atomic_cmpswap : Intrinsic<
968 [LLVMMatchType<0>, // src(VGPR)
969 LLVMMatchType<0>, // cmp(VGPR)
970 llvm_v4i32_ty, // rsrc(SGPR)
971 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
972 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
973 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc)
974 [ImmArg<5>], "", [SDNPMemOperand]>,
975 AMDGPURsrcIntrinsic<2, 0>;
977 class AMDGPUStructBufferAtomic<LLVMType data_ty = llvm_any_ty> : Intrinsic <
979 [LLVMMatchType<0>, // vdata(VGPR)
980 llvm_v4i32_ty, // rsrc(SGPR)
981 llvm_i32_ty, // vindex(VGPR)
982 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
983 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
984 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc)
985 [ImmArg<5>], "", [SDNPMemOperand]>,
986 AMDGPURsrcIntrinsic<1, 0>;
987 def int_amdgcn_struct_buffer_atomic_swap : AMDGPUStructBufferAtomic;
988 def int_amdgcn_struct_buffer_atomic_add : AMDGPUStructBufferAtomic;
989 def int_amdgcn_struct_buffer_atomic_sub : AMDGPUStructBufferAtomic;
990 def int_amdgcn_struct_buffer_atomic_smin : AMDGPUStructBufferAtomic;
991 def int_amdgcn_struct_buffer_atomic_umin : AMDGPUStructBufferAtomic;
992 def int_amdgcn_struct_buffer_atomic_smax : AMDGPUStructBufferAtomic;
993 def int_amdgcn_struct_buffer_atomic_umax : AMDGPUStructBufferAtomic;
994 def int_amdgcn_struct_buffer_atomic_and : AMDGPUStructBufferAtomic;
995 def int_amdgcn_struct_buffer_atomic_or : AMDGPUStructBufferAtomic;
996 def int_amdgcn_struct_buffer_atomic_xor : AMDGPUStructBufferAtomic;
997 def int_amdgcn_struct_buffer_atomic_inc : AMDGPUStructBufferAtomic;
998 def int_amdgcn_struct_buffer_atomic_dec : AMDGPUStructBufferAtomic;
999 def int_amdgcn_struct_buffer_atomic_cmpswap : Intrinsic<
1001 [LLVMMatchType<0>, // src(VGPR)
1002 LLVMMatchType<0>, // cmp(VGPR)
1003 llvm_v4i32_ty, // rsrc(SGPR)
1004 llvm_i32_ty, // vindex(VGPR)
1005 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
1006 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1007 llvm_i32_ty], // cachepolicy(imm; bit 1 = slc)
1008 [ImmArg<6>], "", [SDNPMemOperand]>,
1009 AMDGPURsrcIntrinsic<2, 0>;
1011 // Obsolescent tbuffer intrinsics.
1012 def int_amdgcn_tbuffer_load : Intrinsic <
1013 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1014 [llvm_v4i32_ty, // rsrc(SGPR)
1015 llvm_i32_ty, // vindex(VGPR)
1016 llvm_i32_ty, // voffset(VGPR)
1017 llvm_i32_ty, // soffset(SGPR)
1018 llvm_i32_ty, // offset(imm)
1019 llvm_i32_ty, // dfmt(imm)
1020 llvm_i32_ty, // nfmt(imm)
1021 llvm_i1_ty, // glc(imm)
1022 llvm_i1_ty], // slc(imm)
1023 [IntrReadMem, ImmArg<4>, ImmArg<5>, ImmArg<6>,
1024 ImmArg<7>, ImmArg<8>], "", [SDNPMemOperand]>,
1025 AMDGPURsrcIntrinsic<0>;
1027 def int_amdgcn_tbuffer_store : Intrinsic <
1029 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1030 llvm_v4i32_ty, // rsrc(SGPR)
1031 llvm_i32_ty, // vindex(VGPR)
1032 llvm_i32_ty, // voffset(VGPR)
1033 llvm_i32_ty, // soffset(SGPR)
1034 llvm_i32_ty, // offset(imm)
1035 llvm_i32_ty, // dfmt(imm)
1036 llvm_i32_ty, // nfmt(imm)
1037 llvm_i1_ty, // glc(imm)
1038 llvm_i1_ty], // slc(imm)
1039 [IntrWriteMem, ImmArg<5>, ImmArg<6>, ImmArg<7>,
1040 ImmArg<8>, ImmArg<9>], "", [SDNPMemOperand]>,
1041 AMDGPURsrcIntrinsic<1>;
1043 // New tbuffer intrinsics, with:
1044 // - raw and struct variants
1045 // - joint format field
1046 // - joint cachepolicy field
1047 def int_amdgcn_raw_tbuffer_load : Intrinsic <
1048 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1049 [llvm_v4i32_ty, // rsrc(SGPR)
1050 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
1051 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1052 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
1053 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
1054 [IntrReadMem, ImmArg<3>, ImmArg<4>], "", [SDNPMemOperand]>,
1055 AMDGPURsrcIntrinsic<0>;
1057 def int_amdgcn_raw_tbuffer_store : Intrinsic <
1059 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1060 llvm_v4i32_ty, // rsrc(SGPR)
1061 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
1062 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1063 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
1064 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
1065 [IntrWriteMem, ImmArg<4>, ImmArg<5>], "", [SDNPMemOperand]>,
1066 AMDGPURsrcIntrinsic<1>;
1068 def int_amdgcn_struct_tbuffer_load : Intrinsic <
1069 [llvm_any_ty], // overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1070 [llvm_v4i32_ty, // rsrc(SGPR)
1071 llvm_i32_ty, // vindex(VGPR)
1072 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
1073 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1074 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
1075 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
1076 [IntrReadMem, ImmArg<4>, ImmArg<5>], "", [SDNPMemOperand]>,
1077 AMDGPURsrcIntrinsic<0>;
1079 def int_amdgcn_struct_tbuffer_store : Intrinsic <
1081 [llvm_any_ty, // vdata(VGPR), overloaded for types f32/i32, v2f32/v2i32, v4f32/v4i32
1082 llvm_v4i32_ty, // rsrc(SGPR)
1083 llvm_i32_ty, // vindex(VGPR)
1084 llvm_i32_ty, // offset(VGPR/imm, included in bounds checking and swizzling)
1085 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1086 llvm_i32_ty, // format(imm; bits 3..0 = dfmt, bits 6..4 = nfmt)
1087 llvm_i32_ty], // cachepolicy(imm; bit 0 = glc, bit 1 = slc, bit 2 = dlc on gfx10+)
1088 [IntrWriteMem, ImmArg<5>, ImmArg<6>], "", [SDNPMemOperand]>,
1089 AMDGPURsrcIntrinsic<1>;
1091 class AMDGPUBufferAtomic : Intrinsic <
1093 [LLVMMatchType<0>, // vdata(VGPR)
1094 llvm_v4i32_ty, // rsrc(SGPR)
1095 llvm_i32_ty, // vindex(VGPR)
1096 llvm_i32_ty, // offset(SGPR/VGPR/imm)
1097 llvm_i1_ty], // slc(imm)
1098 [ImmArg<4>], "", [SDNPMemOperand]>,
1099 AMDGPURsrcIntrinsic<1, 0>;
1100 def int_amdgcn_buffer_atomic_swap : AMDGPUBufferAtomic;
1101 def int_amdgcn_buffer_atomic_add : AMDGPUBufferAtomic;
1102 def int_amdgcn_buffer_atomic_sub : AMDGPUBufferAtomic;
1103 def int_amdgcn_buffer_atomic_smin : AMDGPUBufferAtomic;
1104 def int_amdgcn_buffer_atomic_umin : AMDGPUBufferAtomic;
1105 def int_amdgcn_buffer_atomic_smax : AMDGPUBufferAtomic;
1106 def int_amdgcn_buffer_atomic_umax : AMDGPUBufferAtomic;
1107 def int_amdgcn_buffer_atomic_and : AMDGPUBufferAtomic;
1108 def int_amdgcn_buffer_atomic_or : AMDGPUBufferAtomic;
1109 def int_amdgcn_buffer_atomic_xor : AMDGPUBufferAtomic;
1110 def int_amdgcn_buffer_atomic_cmpswap : Intrinsic<
1112 [llvm_i32_ty, // src(VGPR)
1113 llvm_i32_ty, // cmp(VGPR)
1114 llvm_v4i32_ty, // rsrc(SGPR)
1115 llvm_i32_ty, // vindex(VGPR)
1116 llvm_i32_ty, // offset(SGPR/VGPR/imm)
1117 llvm_i1_ty], // slc(imm)
1118 [ImmArg<5>], "", [SDNPMemOperand]>,
1119 AMDGPURsrcIntrinsic<2, 0>;
1121 } // defset AMDGPUBufferIntrinsics
1123 // Uses that do not set the done bit should set IntrWriteMem on the
1125 def int_amdgcn_exp : Intrinsic <[], [
1126 llvm_i32_ty, // tgt,
1128 llvm_any_ty, // src0 (f32 or i32)
1129 LLVMMatchType<0>, // src1
1130 LLVMMatchType<0>, // src2
1131 LLVMMatchType<0>, // src3
1135 [ImmArg<0>, ImmArg<1>, ImmArg<6>, ImmArg<7>, IntrInaccessibleMemOnly]
1138 // exp with compr bit set.
1139 def int_amdgcn_exp_compr : Intrinsic <[], [
1140 llvm_i32_ty, // tgt,
1142 llvm_anyvector_ty, // src0 (v2f16 or v2i16)
1143 LLVMMatchType<0>, // src1
1146 [ImmArg<0>, ImmArg<1>, ImmArg<4>, ImmArg<5>, IntrInaccessibleMemOnly]
1149 def int_amdgcn_buffer_wbinvl1_sc :
1150 GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_sc">,
1151 Intrinsic<[], [], []>;
1153 def int_amdgcn_buffer_wbinvl1 :
1154 GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1">,
1155 Intrinsic<[], [], []>;
1157 def int_amdgcn_s_dcache_inv :
1158 GCCBuiltin<"__builtin_amdgcn_s_dcache_inv">,
1159 Intrinsic<[], [], []>;
1161 def int_amdgcn_s_memtime :
1162 GCCBuiltin<"__builtin_amdgcn_s_memtime">,
1163 Intrinsic<[llvm_i64_ty], []>;
1165 def int_amdgcn_s_sleep :
1166 GCCBuiltin<"__builtin_amdgcn_s_sleep">,
1167 Intrinsic<[], [llvm_i32_ty], [ImmArg<0>]> {
1170 def int_amdgcn_s_incperflevel :
1171 GCCBuiltin<"__builtin_amdgcn_s_incperflevel">,
1172 Intrinsic<[], [llvm_i32_ty], [ImmArg<0>]> {
1175 def int_amdgcn_s_decperflevel :
1176 GCCBuiltin<"__builtin_amdgcn_s_decperflevel">,
1177 Intrinsic<[], [llvm_i32_ty], [ImmArg<0>]> {
1180 def int_amdgcn_s_getreg :
1181 GCCBuiltin<"__builtin_amdgcn_s_getreg">,
1182 Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
1183 [IntrInaccessibleMemOnly, IntrReadMem, IntrSpeculatable, ImmArg<0>]
1186 // int_amdgcn_s_getpc is provided to allow a specific style of position
1187 // independent code to determine the high part of its address when it is
1188 // known (through convention) that the code and any data of interest does
1189 // not cross a 4Gb address boundary. Use for any other purpose may not
1190 // produce the desired results as optimizations may cause code movement,
1191 // especially as we explicitly use IntrNoMem to allow optimizations.
1192 def int_amdgcn_s_getpc :
1193 GCCBuiltin<"__builtin_amdgcn_s_getpc">,
1194 Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable]>;
1196 // __builtin_amdgcn_interp_mov <param>, <attr_chan>, <attr>, <m0>
1197 // param values: 0 = P10, 1 = P20, 2 = P0
1198 def int_amdgcn_interp_mov :
1199 GCCBuiltin<"__builtin_amdgcn_interp_mov">,
1200 Intrinsic<[llvm_float_ty],
1201 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1202 [IntrNoMem, IntrSpeculatable, ImmArg<1>, ImmArg<2>]>;
1204 // __builtin_amdgcn_interp_p1 <i>, <attr_chan>, <attr>, <m0>
1205 // This intrinsic reads from lds, but the memory values are constant,
1206 // so it behaves like IntrNoMem.
1207 def int_amdgcn_interp_p1 :
1208 GCCBuiltin<"__builtin_amdgcn_interp_p1">,
1209 Intrinsic<[llvm_float_ty],
1210 [llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1211 [IntrNoMem, IntrSpeculatable, ImmArg<1>, ImmArg<2>]>;
1213 // __builtin_amdgcn_interp_p2 <p1>, <j>, <attr_chan>, <attr>, <m0>
1214 def int_amdgcn_interp_p2 :
1215 GCCBuiltin<"__builtin_amdgcn_interp_p2">,
1216 Intrinsic<[llvm_float_ty],
1217 [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1218 [IntrNoMem, IntrSpeculatable, ImmArg<2>, ImmArg<3>]>;
1219 // See int_amdgcn_v_interp_p1 for why this is IntrNoMem.
1221 // __builtin_amdgcn_interp_p1_f16 <i>, <attr_chan>, <attr>, <high>, <m0>
1222 def int_amdgcn_interp_p1_f16 :
1223 GCCBuiltin<"__builtin_amdgcn_interp_p1_f16">,
1224 Intrinsic<[llvm_float_ty],
1225 [llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i32_ty],
1226 [IntrNoMem, IntrSpeculatable, ImmArg<1>, ImmArg<2>, ImmArg<3>]>;
1228 // __builtin_amdgcn_interp_p2_f16 <p1>, <j>, <attr_chan>, <attr>, <high>, <m0>
1229 def int_amdgcn_interp_p2_f16 :
1230 GCCBuiltin<"__builtin_amdgcn_interp_p2_f16">,
1231 Intrinsic<[llvm_half_ty],
1232 [llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i32_ty],
1233 [IntrNoMem, IntrSpeculatable, ImmArg<2>, ImmArg<3>, ImmArg<4>]>;
1235 // Pixel shaders only: whether the current pixel is live (i.e. not a helper
1236 // invocation for derivative computation).
1237 def int_amdgcn_ps_live : Intrinsic <
1242 def int_amdgcn_mbcnt_lo :
1243 GCCBuiltin<"__builtin_amdgcn_mbcnt_lo">,
1244 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
1246 def int_amdgcn_mbcnt_hi :
1247 GCCBuiltin<"__builtin_amdgcn_mbcnt_hi">,
1248 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
1250 // llvm.amdgcn.ds.swizzle src offset
1251 def int_amdgcn_ds_swizzle :
1252 GCCBuiltin<"__builtin_amdgcn_ds_swizzle">,
1253 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
1254 [IntrNoMem, IntrConvergent, ImmArg<1>]>;
1256 def int_amdgcn_ubfe : Intrinsic<[llvm_anyint_ty],
1257 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
1258 [IntrNoMem, IntrSpeculatable]
1261 def int_amdgcn_sbfe : Intrinsic<[llvm_anyint_ty],
1262 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty],
1263 [IntrNoMem, IntrSpeculatable]
1266 def int_amdgcn_lerp :
1267 GCCBuiltin<"__builtin_amdgcn_lerp">,
1268 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1269 [IntrNoMem, IntrSpeculatable]
1272 def int_amdgcn_sad_u8 :
1273 GCCBuiltin<"__builtin_amdgcn_sad_u8">,
1274 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1275 [IntrNoMem, IntrSpeculatable]
1278 def int_amdgcn_msad_u8 :
1279 GCCBuiltin<"__builtin_amdgcn_msad_u8">,
1280 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1281 [IntrNoMem, IntrSpeculatable]
1284 def int_amdgcn_sad_hi_u8 :
1285 GCCBuiltin<"__builtin_amdgcn_sad_hi_u8">,
1286 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1287 [IntrNoMem, IntrSpeculatable]
1290 def int_amdgcn_sad_u16 :
1291 GCCBuiltin<"__builtin_amdgcn_sad_u16">,
1292 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1293 [IntrNoMem, IntrSpeculatable]
1296 def int_amdgcn_qsad_pk_u16_u8 :
1297 GCCBuiltin<"__builtin_amdgcn_qsad_pk_u16_u8">,
1298 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty],
1299 [IntrNoMem, IntrSpeculatable]
1302 def int_amdgcn_mqsad_pk_u16_u8 :
1303 GCCBuiltin<"__builtin_amdgcn_mqsad_pk_u16_u8">,
1304 Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty],
1305 [IntrNoMem, IntrSpeculatable]
1308 def int_amdgcn_mqsad_u32_u8 :
1309 GCCBuiltin<"__builtin_amdgcn_mqsad_u32_u8">,
1310 Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_i32_ty, llvm_v4i32_ty],
1311 [IntrNoMem, IntrSpeculatable]
1314 def int_amdgcn_cvt_pk_u8_f32 :
1315 GCCBuiltin<"__builtin_amdgcn_cvt_pk_u8_f32">,
1316 Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty, llvm_i32_ty],
1317 [IntrNoMem, IntrSpeculatable]
1320 def int_amdgcn_icmp :
1321 Intrinsic<[llvm_anyint_ty], [llvm_anyint_ty, LLVMMatchType<1>, llvm_i32_ty],
1322 [IntrNoMem, IntrConvergent, ImmArg<2>]>;
1324 def int_amdgcn_fcmp :
1325 Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, LLVMMatchType<1>, llvm_i32_ty],
1326 [IntrNoMem, IntrConvergent, ImmArg<2>]>;
1328 def int_amdgcn_readfirstlane :
1329 GCCBuiltin<"__builtin_amdgcn_readfirstlane">,
1330 Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
1332 // The lane argument must be uniform across the currently active threads of the
1333 // current wave. Otherwise, the result is undefined.
1334 def int_amdgcn_readlane :
1335 GCCBuiltin<"__builtin_amdgcn_readlane">,
1336 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
1338 // The value to write and lane select arguments must be uniform across the
1339 // currently active threads of the current wave. Otherwise, the result is
1341 def int_amdgcn_writelane :
1342 GCCBuiltin<"__builtin_amdgcn_writelane">,
1343 Intrinsic<[llvm_i32_ty], [
1344 llvm_i32_ty, // uniform value to write: returned by the selected lane
1345 llvm_i32_ty, // uniform lane select
1346 llvm_i32_ty // returned by all lanes other than the selected one
1348 [IntrNoMem, IntrConvergent]
1351 def int_amdgcn_alignbit :
1352 GCCBuiltin<"__builtin_amdgcn_alignbit">, Intrinsic<[llvm_i32_ty],
1353 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1354 [IntrNoMem, IntrSpeculatable]
1357 def int_amdgcn_alignbyte : GCCBuiltin<"__builtin_amdgcn_alignbyte">,
1358 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1359 [IntrNoMem, IntrSpeculatable]
1362 def int_amdgcn_mul_i24 : Intrinsic<[llvm_i32_ty],
1363 [llvm_i32_ty, llvm_i32_ty],
1364 [IntrNoMem, IntrSpeculatable]
1367 def int_amdgcn_mul_u24 : Intrinsic<[llvm_i32_ty],
1368 [llvm_i32_ty, llvm_i32_ty],
1369 [IntrNoMem, IntrSpeculatable]
1372 // llvm.amdgcn.ds.gws.init(i32 bar_val, i32 resource_id)
1374 // bar_val is the total number of waves that will wait on this
1375 // barrier, minus 1.
1376 def int_amdgcn_ds_gws_init :
1377 GCCBuiltin<"__builtin_amdgcn_ds_gws_init">,
1379 [llvm_i32_ty, llvm_i32_ty],
1380 [IntrConvergent, IntrWriteMem, IntrInaccessibleMemOnly], "",
1384 // llvm.amdgcn.ds.gws.barrier(i32 vsrc0, i32 resource_id)
1385 // bar_val is the total number of waves that will wait on this
1386 // barrier, minus 1.
1387 def int_amdgcn_ds_gws_barrier :
1388 GCCBuiltin<"__builtin_amdgcn_ds_gws_barrier">,
1390 [llvm_i32_ty, llvm_i32_ty],
1391 [IntrConvergent, IntrInaccessibleMemOnly], "",
1395 // llvm.amdgcn.ds.gws.sema.v(i32 resource_id)
1396 def int_amdgcn_ds_gws_sema_v :
1397 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_v">,
1400 [IntrConvergent, IntrInaccessibleMemOnly], "",
1404 // llvm.amdgcn.ds.gws.sema.br(i32 vsrc, i32 resource_id)
1405 def int_amdgcn_ds_gws_sema_br :
1406 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_br">,
1408 [llvm_i32_ty, llvm_i32_ty],
1409 [IntrConvergent, IntrInaccessibleMemOnly], "",
1413 // llvm.amdgcn.ds.gws.sema.p(i32 resource_id)
1414 def int_amdgcn_ds_gws_sema_p :
1415 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_p">,
1418 [IntrConvergent, IntrInaccessibleMemOnly], "",
1422 // llvm.amdgcn.ds.gws.sema.release.all(i32 resource_id)
1423 def int_amdgcn_ds_gws_sema_release_all :
1424 GCCBuiltin<"__builtin_amdgcn_ds_gws_sema_release_all">,
1427 [IntrConvergent, IntrInaccessibleMemOnly], "",
1432 // Copies the source value to the destination value, with the guarantee that
1433 // the source value is computed as if the entire program were executed in WQM.
1434 def int_amdgcn_wqm : Intrinsic<[llvm_any_ty],
1435 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
1438 // Copies the source value to the destination value, such that the source
1439 // is computed as if the entire program were executed in WQM if any other
1440 // program code executes in WQM.
1441 def int_amdgcn_softwqm : Intrinsic<[llvm_any_ty],
1442 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable]
1445 // Return true if at least one thread within the pixel quad passes true into
1447 def int_amdgcn_wqm_vote : Intrinsic<[llvm_i1_ty],
1448 [llvm_i1_ty], [IntrNoMem, IntrConvergent]
1451 // If false, set EXEC=0 for the current thread until the end of program.
1452 def int_amdgcn_kill : Intrinsic<[], [llvm_i1_ty], []>;
1454 // Copies the active channels of the source value to the destination value,
1455 // with the guarantee that the source value is computed as if the entire
1456 // program were executed in Whole Wavefront Mode, i.e. with all channels
1457 // enabled, with a few exceptions: - Phi nodes with require WWM return an
1459 def int_amdgcn_wwm : Intrinsic<[llvm_any_ty],
1460 [LLVMMatchType<0>], [IntrNoMem, IntrSpeculatable, IntrConvergent]
1463 // Given a value, copies it while setting all the inactive lanes to a given
1464 // value. Note that OpenGL helper lanes are considered active, so if the
1465 // program ever uses WQM, then the instruction and the first source will be
1467 def int_amdgcn_set_inactive :
1468 Intrinsic<[llvm_anyint_ty],
1469 [LLVMMatchType<0>, // value to be copied
1470 LLVMMatchType<0>], // value for the inactive lanes to take
1471 [IntrNoMem, IntrConvergent]>;
1473 // Return if the given flat pointer points to a local memory address.
1474 def int_amdgcn_is_shared : GCCBuiltin<"__builtin_amdgcn_is_shared">,
1475 Intrinsic<[llvm_i1_ty], [llvm_ptr_ty],
1476 [IntrNoMem, IntrSpeculatable, NoCapture<0>]
1479 // Return if the given flat pointer points to a prvate memory address.
1480 def int_amdgcn_is_private : GCCBuiltin<"__builtin_amdgcn_is_private">,
1481 Intrinsic<[llvm_i1_ty], [llvm_ptr_ty],
1482 [IntrNoMem, IntrSpeculatable, NoCapture<0>]
1485 //===----------------------------------------------------------------------===//
1487 //===----------------------------------------------------------------------===//
1489 def int_amdgcn_s_dcache_inv_vol :
1490 GCCBuiltin<"__builtin_amdgcn_s_dcache_inv_vol">,
1491 Intrinsic<[], [], []>;
1493 def int_amdgcn_buffer_wbinvl1_vol :
1494 GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_vol">,
1495 Intrinsic<[], [], []>;
1497 //===----------------------------------------------------------------------===//
1499 //===----------------------------------------------------------------------===//
1501 // llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1502 def int_amdgcn_mov_dpp :
1503 Intrinsic<[llvm_anyint_ty],
1504 [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
1505 llvm_i1_ty], [IntrNoMem, IntrConvergent, ImmArg<1>,
1506 ImmArg<2>, ImmArg<3>, ImmArg<4>]>;
1508 // llvm.amdgcn.update.dpp.i32 <old> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1509 // Should be equivalent to:
1510 // v_mov_b32 <dest> <old>
1511 // v_mov_b32 <dest> <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
1512 def int_amdgcn_update_dpp :
1513 Intrinsic<[llvm_anyint_ty],
1514 [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty,
1515 llvm_i32_ty, llvm_i32_ty, llvm_i1_ty],
1516 [IntrNoMem, IntrConvergent,
1517 ImmArg<2>, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1519 def int_amdgcn_s_dcache_wb :
1520 GCCBuiltin<"__builtin_amdgcn_s_dcache_wb">,
1521 Intrinsic<[], [], []>;
1523 def int_amdgcn_s_dcache_wb_vol :
1524 GCCBuiltin<"__builtin_amdgcn_s_dcache_wb_vol">,
1525 Intrinsic<[], [], []>;
1527 def int_amdgcn_s_memrealtime :
1528 GCCBuiltin<"__builtin_amdgcn_s_memrealtime">,
1529 Intrinsic<[llvm_i64_ty]>;
1531 // llvm.amdgcn.ds.permute <index> <src>
1532 def int_amdgcn_ds_permute :
1533 GCCBuiltin<"__builtin_amdgcn_ds_permute">,
1534 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
1536 // llvm.amdgcn.ds.bpermute <index> <src>
1537 def int_amdgcn_ds_bpermute :
1538 GCCBuiltin<"__builtin_amdgcn_ds_bpermute">,
1539 Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
1541 //===----------------------------------------------------------------------===//
1543 //===----------------------------------------------------------------------===//
1545 // llvm.amdgcn.permlane16 <old> <src0> <src1> <src2> <fi> <bound_control>
1546 def int_amdgcn_permlane16 : GCCBuiltin<"__builtin_amdgcn_permlane16">,
1547 Intrinsic<[llvm_i32_ty],
1548 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty],
1549 [IntrNoMem, IntrConvergent, ImmArg<4>, ImmArg<5>]>;
1551 // llvm.amdgcn.permlanex16 <old> <src0> <src1> <src2> <fi> <bound_control>
1552 def int_amdgcn_permlanex16 : GCCBuiltin<"__builtin_amdgcn_permlanex16">,
1553 Intrinsic<[llvm_i32_ty],
1554 [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i1_ty, llvm_i1_ty],
1555 [IntrNoMem, IntrConvergent, ImmArg<4>, ImmArg<5>]>;
1557 // llvm.amdgcn.mov.dpp8.i32 <src> <sel>
1558 // <sel> is a 32-bit constant whose high 8 bits must be zero which selects
1559 // the lanes to read from.
1560 def int_amdgcn_mov_dpp8 :
1561 Intrinsic<[llvm_anyint_ty],
1562 [LLVMMatchType<0>, llvm_i32_ty],
1563 [IntrNoMem, IntrConvergent, ImmArg<1>]>;
1565 def int_amdgcn_s_get_waveid_in_workgroup :
1566 GCCBuiltin<"__builtin_amdgcn_s_get_waveid_in_workgroup">,
1567 Intrinsic<[llvm_i32_ty], [], [IntrReadMem, IntrInaccessibleMemOnly]>;
1569 //===----------------------------------------------------------------------===//
1570 // Deep learning intrinsics.
1571 //===----------------------------------------------------------------------===//
1573 // f32 %r = llvm.amdgcn.fdot2(v2f16 %a, v2f16 %b, f32 %c, i1 %clamp)
1574 // %r = %a[0] * %b[0] + %a[1] * %b[1] + %c
1575 def int_amdgcn_fdot2 :
1576 GCCBuiltin<"__builtin_amdgcn_fdot2">,
1578 [llvm_float_ty], // %r
1580 llvm_v2f16_ty, // %a
1581 llvm_v2f16_ty, // %b
1582 llvm_float_ty, // %c
1583 llvm_i1_ty // %clamp
1585 [IntrNoMem, IntrSpeculatable, ImmArg<3>]
1588 // i32 %r = llvm.amdgcn.sdot2(v2i16 %a, v2i16 %b, i32 %c, i1 %clamp)
1589 // %r = %a[0] * %b[0] + %a[1] * %b[1] + %c
1590 def int_amdgcn_sdot2 :
1591 GCCBuiltin<"__builtin_amdgcn_sdot2">,
1593 [llvm_i32_ty], // %r
1595 llvm_v2i16_ty, // %a
1596 llvm_v2i16_ty, // %b
1598 llvm_i1_ty // %clamp
1600 [IntrNoMem, IntrSpeculatable, ImmArg<3>]
1603 // u32 %r = llvm.amdgcn.udot2(v2u16 %a, v2u16 %b, u32 %c, i1 %clamp)
1604 // %r = %a[0] * %b[0] + %a[1] * %b[1] + %c
1605 def int_amdgcn_udot2 :
1606 GCCBuiltin<"__builtin_amdgcn_udot2">,
1608 [llvm_i32_ty], // %r
1610 llvm_v2i16_ty, // %a
1611 llvm_v2i16_ty, // %b
1613 llvm_i1_ty // %clamp
1615 [IntrNoMem, IntrSpeculatable, ImmArg<3>]
1618 // i32 %r = llvm.amdgcn.sdot4(v4i8 (as i32) %a, v4i8 (as i32) %b, i32 %c, i1 %clamp)
1619 // %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c
1620 def int_amdgcn_sdot4 :
1621 GCCBuiltin<"__builtin_amdgcn_sdot4">,
1623 [llvm_i32_ty], // %r
1628 llvm_i1_ty // %clamp
1630 [IntrNoMem, IntrSpeculatable, ImmArg<3>]
1633 // u32 %r = llvm.amdgcn.udot4(v4u8 (as u32) %a, v4u8 (as u32) %b, u32 %c, i1 %clamp)
1634 // %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] + %c
1635 def int_amdgcn_udot4 :
1636 GCCBuiltin<"__builtin_amdgcn_udot4">,
1638 [llvm_i32_ty], // %r
1643 llvm_i1_ty // %clamp
1645 [IntrNoMem, IntrSpeculatable, ImmArg<3>]
1648 // i32 %r = llvm.amdgcn.sdot8(v8i4 (as i32) %a, v8i4 (as i32) %b, i32 %c, i1 %clamp)
1649 // %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] +
1650 // %a[4] * %b[4] + %a[5] * %b[5] + %a[6] * %b[6] + %a[7] * %b[7] + %c
1651 def int_amdgcn_sdot8 :
1652 GCCBuiltin<"__builtin_amdgcn_sdot8">,
1654 [llvm_i32_ty], // %r
1659 llvm_i1_ty // %clamp
1661 [IntrNoMem, IntrSpeculatable, ImmArg<3>]
1664 // u32 %r = llvm.amdgcn.udot8(v8u4 (as u32) %a, v8u4 (as u32) %b, u32 %c, i1 %clamp)
1665 // %r = %a[0] * %b[0] + %a[1] * %b[1] + %a[2] * %b[2] + %a[3] * %b[3] +
1666 // %a[4] * %b[4] + %a[5] * %b[5] + %a[6] * %b[6] + %a[7] * %b[7] + %c
1667 def int_amdgcn_udot8 :
1668 GCCBuiltin<"__builtin_amdgcn_udot8">,
1670 [llvm_i32_ty], // %r
1675 llvm_i1_ty // %clamp
1677 [IntrNoMem, IntrSpeculatable, ImmArg<3>]
1680 //===----------------------------------------------------------------------===//
1681 // gfx908 intrinsics
1682 // ===----------------------------------------------------------------------===//
1684 class AMDGPUBufferAtomicNoRtn : Intrinsic <
1686 [llvm_anyfloat_ty, // vdata(VGPR)
1687 llvm_v4i32_ty, // rsrc(SGPR)
1688 llvm_i32_ty, // vindex(VGPR)
1689 llvm_i32_ty, // offset(SGPR/VGPR/imm)
1690 llvm_i1_ty], // slc(imm)
1691 [], "", [SDNPMemOperand]>,
1692 AMDGPURsrcIntrinsic<1, 0>;
1694 class AMDGPUGlobalAtomicNoRtn : Intrinsic <
1696 [llvm_anyptr_ty, // vaddr
1697 llvm_anyfloat_ty], // vdata(VGPR)
1698 [IntrArgMemOnly, NoCapture<0>], "", [SDNPMemOperand]>;
1700 def int_amdgcn_buffer_atomic_fadd : AMDGPUBufferAtomicNoRtn;
1701 def int_amdgcn_global_atomic_fadd : AMDGPUGlobalAtomicNoRtn;
1703 // llvm.amdgcn.mfma.f32.* vdst, srcA, srcB, srcC, cbsz, abid, blgp
1704 def int_amdgcn_mfma_f32_32x32x1f32 : Intrinsic<[llvm_v32f32_ty],
1705 [llvm_float_ty, llvm_float_ty, llvm_v32f32_ty,
1706 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1707 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1709 def int_amdgcn_mfma_f32_16x16x1f32 : Intrinsic<[llvm_v16f32_ty],
1710 [llvm_float_ty, llvm_float_ty, llvm_v16f32_ty,
1711 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1712 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1714 def int_amdgcn_mfma_f32_4x4x1f32 : Intrinsic<[llvm_v4f32_ty],
1715 [llvm_float_ty, llvm_float_ty, llvm_v4f32_ty,
1716 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1717 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1719 def int_amdgcn_mfma_f32_32x32x2f32 : Intrinsic<[llvm_v16f32_ty],
1720 [llvm_float_ty, llvm_float_ty, llvm_v16f32_ty,
1721 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1722 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1724 def int_amdgcn_mfma_f32_16x16x4f32 : Intrinsic<[llvm_v4f32_ty],
1725 [llvm_float_ty, llvm_float_ty, llvm_v4f32_ty,
1726 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1727 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1729 def int_amdgcn_mfma_f32_32x32x4f16 : Intrinsic<[llvm_v32f32_ty],
1730 [llvm_v4f16_ty, llvm_v4f16_ty, llvm_v32f32_ty,
1731 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1732 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1734 def int_amdgcn_mfma_f32_16x16x4f16 : Intrinsic<[llvm_v16f32_ty],
1735 [llvm_v4f16_ty, llvm_v4f16_ty, llvm_v16f32_ty,
1736 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1737 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1739 def int_amdgcn_mfma_f32_4x4x4f16 : Intrinsic<[llvm_v4f32_ty],
1740 [llvm_v4f16_ty, llvm_v4f16_ty, llvm_v4f32_ty,
1741 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1742 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1744 def int_amdgcn_mfma_f32_32x32x8f16 : Intrinsic<[llvm_v16f32_ty],
1745 [llvm_v4f16_ty, llvm_v4f16_ty, llvm_v16f32_ty,
1746 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1747 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1749 def int_amdgcn_mfma_f32_16x16x16f16 : Intrinsic<[llvm_v4f32_ty],
1750 [llvm_v4f16_ty, llvm_v4f16_ty, llvm_v4f32_ty,
1751 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1752 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1754 def int_amdgcn_mfma_i32_32x32x4i8 : Intrinsic<[llvm_v32i32_ty],
1755 [llvm_i32_ty, llvm_i32_ty, llvm_v32i32_ty,
1756 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1757 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1759 def int_amdgcn_mfma_i32_16x16x4i8 : Intrinsic<[llvm_v16i32_ty],
1760 [llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty,
1761 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1762 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1764 def int_amdgcn_mfma_i32_4x4x4i8 : Intrinsic<[llvm_v4i32_ty],
1765 [llvm_i32_ty, llvm_i32_ty, llvm_v4i32_ty,
1766 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1767 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1769 def int_amdgcn_mfma_i32_32x32x8i8 : Intrinsic<[llvm_v16i32_ty],
1770 [llvm_i32_ty, llvm_i32_ty, llvm_v16i32_ty,
1771 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1772 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1774 def int_amdgcn_mfma_i32_16x16x16i8 : Intrinsic<[llvm_v4i32_ty],
1775 [llvm_i32_ty, llvm_i32_ty, llvm_v4i32_ty,
1776 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1777 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1779 def int_amdgcn_mfma_f32_32x32x2bf16 : Intrinsic<[llvm_v32f32_ty],
1780 [llvm_v2i16_ty, llvm_v2i16_ty, llvm_v32f32_ty,
1781 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1782 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1784 def int_amdgcn_mfma_f32_16x16x2bf16 : Intrinsic<[llvm_v16f32_ty],
1785 [llvm_v2i16_ty, llvm_v2i16_ty, llvm_v16f32_ty,
1786 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1787 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1789 def int_amdgcn_mfma_f32_4x4x2bf16 : Intrinsic<[llvm_v4f32_ty],
1790 [llvm_v2i16_ty, llvm_v2i16_ty, llvm_v4f32_ty,
1791 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1792 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1794 def int_amdgcn_mfma_f32_32x32x4bf16 : Intrinsic<[llvm_v16f32_ty],
1795 [llvm_v2i16_ty, llvm_v2i16_ty, llvm_v16f32_ty,
1796 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1797 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1799 def int_amdgcn_mfma_f32_16x16x8bf16 : Intrinsic<[llvm_v4f32_ty],
1800 [llvm_v2i16_ty, llvm_v2i16_ty, llvm_v4f32_ty,
1801 llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
1802 [IntrConvergent, IntrNoMem, ImmArg<3>, ImmArg<4>, ImmArg<5>]>;
1804 //===----------------------------------------------------------------------===//
1805 // Special Intrinsics for backend internal use only. No frontend
1806 // should emit calls to these.
1807 // ===----------------------------------------------------------------------===//
1808 def int_amdgcn_if : Intrinsic<[llvm_i1_ty, llvm_anyint_ty],
1809 [llvm_i1_ty], [IntrConvergent]
1812 def int_amdgcn_else : Intrinsic<[llvm_i1_ty, llvm_anyint_ty],
1813 [llvm_anyint_ty], [IntrConvergent]
1816 def int_amdgcn_if_break : Intrinsic<[llvm_anyint_ty],
1817 [llvm_i1_ty, llvm_anyint_ty], [IntrNoMem, IntrConvergent]
1820 def int_amdgcn_loop : Intrinsic<[llvm_i1_ty],
1821 [llvm_anyint_ty], [IntrConvergent]
1824 def int_amdgcn_end_cf : Intrinsic<[], [llvm_anyint_ty], [IntrConvergent]>;
1826 // Represent unreachable in a divergent region.
1827 def int_amdgcn_unreachable : Intrinsic<[], [], [IntrConvergent]>;
1829 // Emit 2.5 ulp, no denormal division. Should only be inserted by
1830 // pass based on !fpmath metadata.
1831 def int_amdgcn_fdiv_fast : Intrinsic<
1832 [llvm_float_ty], [llvm_float_ty, llvm_float_ty],
1833 [IntrNoMem, IntrSpeculatable]