lib/Target/AArch64/AArch64RegisterBankInfo.h

   1 //===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file declares the targeting of the RegisterBankInfo class for AArch64.
  10 /// \todo This should be generated by TableGen.
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
  14 #define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
  15
  16 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  17
  18 #define GET_REGBANK_DECLARATIONS
  19 #include "AArch64GenRegisterBank.inc"
  20
  21 namespace llvm {
  22
  23 class TargetRegisterInfo;
  24
  25 class AArch64GenRegisterBankInfo : public RegisterBankInfo {
  26 protected:
  27   enum PartialMappingIdx {
  28     PMI_None = -1,
  29     PMI_FPR16 = 1,
  30     PMI_FPR32,
  31     PMI_FPR64,
  32     PMI_FPR128,
  33     PMI_FPR256,
  34     PMI_FPR512,
  35     PMI_GPR32,
  36     PMI_GPR64,
  37     PMI_FirstGPR = PMI_GPR32,
  38     PMI_LastGPR = PMI_GPR64,
  39     PMI_FirstFPR = PMI_FPR16,
  40     PMI_LastFPR = PMI_FPR512,
  41     PMI_Min = PMI_FirstFPR,
  42   };
  43
  44   static RegisterBankInfo::PartialMapping PartMappings[];
  45   static RegisterBankInfo::ValueMapping ValMappings[];
  46   static PartialMappingIdx BankIDToCopyMapIdx[];
  47
  48   enum ValueMappingIdx {
  49     InvalidIdx = 0,
  50     First3OpsIdx = 1,
  51     Last3OpsIdx = 22,
  52     DistanceBetweenRegBanks = 3,
  53     FirstCrossRegCpyIdx = 25,
  54     LastCrossRegCpyIdx = 39,
  55     DistanceBetweenCrossRegCpy = 2,
  56     FPExt16To32Idx = 41,
  57     FPExt16To64Idx = 43,
  58     FPExt32To64Idx = 45,
  59     FPExt64To128Idx = 47,
  60     Shift64Imm = 49
  61   };
  62
  63   static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx,
  64                               unsigned ValLength, const RegisterBank &RB);
  65   static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank,
  66                                 unsigned Size, unsigned Offset);
  67   static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias,
  68                                      PartialMappingIdx LastAlias,
  69                                      ArrayRef<PartialMappingIdx> Order);
  70
  71   static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
  72
  73   /// Get the pointer to the ValueMapping representing the RegisterBank
  74   /// at \p RBIdx with a size of \p Size.
  75   ///
  76   /// The returned mapping works for instructions with the same kind of
  77   /// operands for up to 3 operands.
  78   ///
  79   /// \pre \p RBIdx != PartialMappingIdx::None
  80   static const RegisterBankInfo::ValueMapping *
  81   getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
  82
  83   /// Get the pointer to the ValueMapping of the operands of a copy
  84   /// instruction from the \p SrcBankID register bank to the \p DstBankID
  85   /// register bank with a size of \p Size.
  86   static const RegisterBankInfo::ValueMapping *
  87   getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
  88
  89   /// Get the instruction mapping for G_FPEXT.
  90   ///
  91   /// \pre (DstSize, SrcSize) pair is one of the following:
  92   ///      (32, 16), (64, 16), (64, 32), (128, 64)
  93   ///
  94   /// \return An InstructionMapping with statically allocated OperandsMapping.
  95   static const RegisterBankInfo::ValueMapping *
  96   getFPExtMapping(unsigned DstSize, unsigned SrcSize);
  97
  98 #define GET_TARGET_REGBANK_CLASS
  99 #include "AArch64GenRegisterBank.inc"
 100 };
 101
 102 /// This class provides the information for the target register banks.
 103 class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo {
 104   /// See RegisterBankInfo::applyMapping.
 105   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
 106
 107   /// Get an instruction mapping where all the operands map to
 108   /// the same register bank and have similar size.
 109   ///
 110   /// \pre MI.getNumOperands() <= 3
 111   ///
 112   /// \return An InstructionMappings with a statically allocated
 113   /// OperandsMapping.
 114   const InstructionMapping &
 115   getSameKindOfOperandsMapping(const MachineInstr &MI) const;
 116
 117   /// Returns true if the output of \p MI must be stored on a FPR register.
 118   bool hasFPConstraints(const MachineInstr &MI, const MachineRegisterInfo &MRI,
 119                      const TargetRegisterInfo &TRI) const;
 120
 121   /// Returns true if the source registers of \p MI must all be FPRs.
 122   bool onlyUsesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
 123                   const TargetRegisterInfo &TRI) const;
 124
 125   /// Returns true if the destination register of \p MI must be a FPR.
 126   bool onlyDefinesFP(const MachineInstr &MI, const MachineRegisterInfo &MRI,
 127                      const TargetRegisterInfo &TRI) const;
 128
 129 public:
 130   AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
 131
 132   unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
 133                     unsigned Size) const override;
 134
 135   const RegisterBank &
 136   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
 137
 138   InstructionMappings
 139   getInstrAlternativeMappings(const MachineInstr &MI) const override;
 140
 141   const InstructionMapping &
 142   getInstrMapping(const MachineInstr &MI) const override;
 143 };
 144 } // End llvm namespace.
 145 #endif