lib/Target/ARM/ARMScheduleA57WriteRes.td

   1 //=- ARMScheduleA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Contains all of the Cortex-A57 specific SchedWriteRes types. The approach
  10 // below is to define a generic SchedWriteRes for every combination of
  11 // latency and microOps. The naming conventions is to use a prefix, one field
  12 // for latency, and one or more microOp count/type designators.
  13 //   Prefix: A57Write
  14 //   Latency: #cyc
  15 //   MicroOp Count/Types: #(B|I|M|L|S|X|W|V)
  16 //
  17 // e.g. A57Write_6cyc_1I_6S_4V means the total latency is 6 and there are
  18 //      11 micro-ops to be issued as follows: one to I pipe, six to S pipes and
  19 //      four to V pipes.
  20 //
  21 //===----------------------------------------------------------------------===//
  22
  23 //===----------------------------------------------------------------------===//
  24 // Define Generic 1 micro-op types
  25
  26 def A57Write_5cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 5;  }
  27 def A57Write_5cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 5;  }
  28 def A57Write_5cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 5;  }
  29 def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
  30 def A57Write_17cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 17;
  31                                                     let ResourceCycles = [17]; }
  32 def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
  33                                                     let ResourceCycles = [18]; }
  34 def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
  35                                                     let ResourceCycles = [19]; }
  36 def A57Write_20cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 20;
  37                                                     let ResourceCycles = [20]; }
  38 def A57Write_1cyc_1B  : SchedWriteRes<[A57UnitB]> { let Latency = 1;  }
  39 def A57Write_1cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 1;  }
  40 def A57Write_2cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 2;  }
  41 def A57Write_3cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 3;  }
  42 def A57Write_1cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 1;  }
  43 def A57Write_2cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 2;  }
  44 def A57Write_3cyc_1S  : SchedWriteRes<[A57UnitS]> { let Latency = 3;  }
  45 def A57Write_2cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 2;  }
  46 def A57Write_32cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 32;
  47                                                     let ResourceCycles = [32]; }
  48 def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
  49                                                     let ResourceCycles = [32]; }
  50 def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
  51                                                     let ResourceCycles = [35]; }
  52 def A57Write_3cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 3;  }
  53 def A57Write_3cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 3;  }
  54 def A57Write_3cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 3;  }
  55 def A57Write_3cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 3;  }
  56
  57 // A57Write_3cyc_1L - A57Write_20cyc_1L
  58 foreach Lat = 3-20 in {
  59   def A57Write_#Lat#cyc_1L : SchedWriteRes<[A57UnitL]> {
  60     let Latency = Lat;
  61   }
  62 }
  63
  64 // A57Write_4cyc_1S - A57Write_16cyc_1S
  65 foreach Lat = 4-16 in {
  66   def A57Write_#Lat#cyc_1S : SchedWriteRes<[A57UnitS]> {
  67     let Latency = Lat;
  68   }
  69 }
  70
  71 def A57Write_4cyc_1M  : SchedWriteRes<[A57UnitL]> { let Latency = 4;  }
  72 def A57Write_4cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 4;  }
  73 def A57Write_4cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 4;  }
  74 def A57Write_5cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 5;  }
  75 def A57Write_6cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 6;  }
  76 def A57Write_6cyc_1W  : SchedWriteRes<[A57UnitW]> { let Latency = 6;  }
  77 def A57Write_8cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 8;  }
  78 def A57Write_9cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 9;  }
  79 def A57Write_6cyc_1M  : SchedWriteRes<[A57UnitM]> { let Latency = 6;  }
  80 def A57Write_6cyc_1V  : SchedWriteRes<[A57UnitV]> { let Latency = 6;  }
  81
  82
  83 //===----------------------------------------------------------------------===//
  84 // Define Generic 2 micro-op types
  85
  86 def A57Write_64cyc_2X    : SchedWriteRes<[A57UnitX, A57UnitX]> {
  87   let Latency     = 64;
  88   let NumMicroOps = 2;
  89   let ResourceCycles = [32, 32];
  90 }
  91 def A57Write_6cyc_1I_1L  : SchedWriteRes<[A57UnitI,
  92                                           A57UnitL]> {
  93   let Latency     = 6;
  94   let NumMicroOps = 2;
  95 }
  96 def A57Write_6cyc_1V_1X  : SchedWriteRes<[A57UnitV,
  97                                           A57UnitX]> {
  98   let Latency     = 6;
  99   let NumMicroOps = 2;
 100 }
 101 def A57Write_7cyc_1V_1X  : SchedWriteRes<[A57UnitV,
 102                                           A57UnitX]> {
 103   let Latency     = 7;
 104   let NumMicroOps = 2;
 105 }
 106 def A57Write_8cyc_1L_1V  : SchedWriteRes<[A57UnitL,
 107                                           A57UnitV]> {
 108   let Latency     = 8;
 109   let NumMicroOps = 2;
 110 }
 111 def A57Write_9cyc_1L_1V  : SchedWriteRes<[A57UnitL,
 112                                           A57UnitV]> {
 113   let Latency     = 9;
 114   let NumMicroOps = 2;
 115 }
 116 def A57Write_9cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
 117   let Latency     = 9;
 118   let NumMicroOps = 2;
 119 }
 120 def A57Write_8cyc_2X     : SchedWriteRes<[A57UnitX, A57UnitX]> {
 121   let Latency     = 8;
 122   let NumMicroOps = 2;
 123 }
 124 def A57Write_6cyc_2L     : SchedWriteRes<[A57UnitL, A57UnitL]> {
 125   let Latency     = 6;
 126   let NumMicroOps = 2;
 127 }
 128 def A57Write_6cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
 129   let Latency     = 6;
 130   let NumMicroOps = 2;
 131 }
 132 def A57Write_6cyc_2W     : SchedWriteRes<[A57UnitW, A57UnitW]> {
 133   let Latency     = 6;
 134   let NumMicroOps = 2;
 135 }
 136 def A57Write_5cyc_1I_1L  : SchedWriteRes<[A57UnitI,
 137                                           A57UnitL]> {
 138   let Latency     = 5;
 139   let NumMicroOps = 2;
 140 }
 141 def A57Write_5cyc_1I_1M  : SchedWriteRes<[A57UnitI,
 142                                           A57UnitM]> {
 143   let Latency     = 5;
 144   let NumMicroOps = 2;
 145 }
 146 def A57Write_5cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
 147   let Latency     = 5;
 148   let NumMicroOps = 2;
 149 }
 150 def A57Write_5cyc_2X     : SchedWriteRes<[A57UnitX, A57UnitX]> {
 151   let Latency     = 5;
 152   let NumMicroOps = 2;
 153 }
 154 def A57Write_10cyc_1L_1V : SchedWriteRes<[A57UnitL,
 155                                           A57UnitV]> {
 156   let Latency     = 10;
 157   let NumMicroOps = 2;
 158 }
 159 def A57Write_10cyc_2V    : SchedWriteRes<[A57UnitV, A57UnitV]> {
 160   let Latency     = 10;
 161   let NumMicroOps = 2;
 162 }
 163 def A57Write_1cyc_1B_1I  : SchedWriteRes<[A57UnitB,
 164                                           A57UnitI]> {
 165   let Latency     = 1;
 166   let NumMicroOps = 2;
 167 }
 168 def A57Write_1cyc_1I_1S  : SchedWriteRes<[A57UnitI,
 169                                           A57UnitS]> {
 170   let Latency     = 1;
 171   let NumMicroOps = 2;
 172 }
 173 def A57Write_1cyc_1S_1I  : SchedWriteRes<[A57UnitS,
 174                                           A57UnitI]> {
 175   let Latency     = 1;
 176   let NumMicroOps = 2;
 177 }
 178 def A57Write_2cyc_1S_1I  : SchedWriteRes<[A57UnitS,
 179                                           A57UnitI]> {
 180   let Latency     = 2;
 181   let NumMicroOps = 2;
 182 }
 183 def A57Write_3cyc_1S_1I  : SchedWriteRes<[A57UnitS,
 184                                           A57UnitI]> {
 185   let Latency     = 3;
 186   let NumMicroOps = 2;
 187 }
 188 def A57Write_1cyc_1S_1M  : SchedWriteRes<[A57UnitS,
 189                                           A57UnitM]> {
 190   let Latency     = 1;
 191   let NumMicroOps = 2;
 192 }
 193 def A57Write_2cyc_1B_1I  : SchedWriteRes<[A57UnitB,
 194                                           A57UnitI]> {
 195   let Latency     = 2;
 196   let NumMicroOps = 2;
 197 }
 198 def A57Write_3cyc_1B_1I  : SchedWriteRes<[A57UnitB,
 199                                           A57UnitI]> {
 200   let Latency     = 3;
 201   let NumMicroOps = 2;
 202 }
 203 def A57Write_6cyc_1B_1L  : SchedWriteRes<[A57UnitB,
 204                                           A57UnitI]> {
 205   let Latency     = 6;
 206   let NumMicroOps = 2;
 207 }
 208 def A57Write_2cyc_1I_1M  : SchedWriteRes<[A57UnitI,
 209                                           A57UnitM]> {
 210   let Latency     = 2;
 211   let NumMicroOps = 2;
 212 }
 213 def A57Write_2cyc_2S     : SchedWriteRes<[A57UnitS, A57UnitS]> {
 214   let Latency     = 2;
 215   let NumMicroOps = 2;
 216 }
 217 def A57Write_2cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
 218   let Latency     = 2;
 219   let NumMicroOps = 2;
 220 }
 221 def A57Write_36cyc_2X    : SchedWriteRes<[A57UnitX, A57UnitX]> {
 222   let Latency     = 36;
 223   let NumMicroOps = 2;
 224   let ResourceCycles = [18, 18];
 225 }
 226 def A57Write_3cyc_1I_1M  : SchedWriteRes<[A57UnitI,
 227                                           A57UnitM]> {
 228   let Latency     = 3;
 229   let NumMicroOps = 2;
 230 }
 231 def A57Write_4cyc_1I_1M  : SchedWriteRes<[A57UnitI,
 232                                           A57UnitM]> {
 233   let Latency     = 4;
 234   let NumMicroOps = 2;
 235 }
 236
 237 // A57Write_3cyc_1L_1I - A57Write_20cyc_1L_1I
 238 foreach Lat = 3-20 in {
 239   def A57Write_#Lat#cyc_1L_1I : SchedWriteRes<[A57UnitL, A57UnitI]> {
 240     let Latency = Lat; let NumMicroOps = 2;
 241   }
 242 }
 243
 244 def A57Write_3cyc_1I_1S  : SchedWriteRes<[A57UnitI,
 245                                           A57UnitS]> {
 246   let Latency     = 3;
 247   let NumMicroOps = 2;
 248 }
 249 def A57Write_3cyc_1S_1V  : SchedWriteRes<[A57UnitS,
 250                                           A57UnitV]> {
 251   let Latency     = 3;
 252   let NumMicroOps = 2;
 253 }
 254 def A57Write_4cyc_1S_1V  : SchedWriteRes<[A57UnitS,
 255                                           A57UnitV]> {
 256   let Latency     = 4;
 257   let NumMicroOps = 2;
 258 }
 259 def A57Write_3cyc_2V     : SchedWriteRes<[A57UnitV, A57UnitV]> {
 260   let Latency     = 3;
 261   let NumMicroOps = 2;
 262 }
 263
 264 // A57Write_4cyc_1S_1I - A57Write_16cyc_1S_1I
 265 foreach Lat = 4-16 in {
 266   def A57Write_#Lat#cyc_1S_1I : SchedWriteRes<[A57UnitS, A57UnitI]> {
 267     let Latency = Lat; let NumMicroOps = 2;
 268   }
 269 }
 270
 271 def A57Write_4cyc_2X     : SchedWriteRes<[A57UnitX, A57UnitX]> {
 272   let Latency     = 4;
 273   let NumMicroOps = 2;
 274 }
 275
 276
 277 //===----------------------------------------------------------------------===//
 278 // Define Generic 3 micro-op types
 279
 280 def A57Write_10cyc_3V       : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV]> {
 281   let Latency     = 10;
 282   let NumMicroOps = 3;
 283 }
 284 def A57Write_2cyc_1I_2S     : SchedWriteRes<[A57UnitI,
 285                                              A57UnitS, A57UnitS]> {
 286   let Latency     = 2;
 287   let NumMicroOps = 3;
 288 }
 289 def A57Write_3cyc_1I_1S_1V  : SchedWriteRes<[A57UnitI,
 290                                              A57UnitS,
 291                                              A57UnitV]> {
 292   let Latency     = 3;
 293   let NumMicroOps = 3;
 294 }
 295 def A57Write_3cyc_1S_1V_1I  : SchedWriteRes<[A57UnitS,
 296                                              A57UnitV,
 297                                              A57UnitI]> {
 298   let Latency     = 3;
 299   let NumMicroOps = 3;
 300 }
 301 def A57Write_4cyc_1S_1V_1I  : SchedWriteRes<[A57UnitS,
 302                                              A57UnitV,
 303                                              A57UnitI]> {
 304   let Latency     = 4;
 305   let NumMicroOps = 3;
 306 }
 307 def A57Write_4cyc_1I_1L_1M  : SchedWriteRes<[A57UnitI, A57UnitL, A57UnitM]> {
 308   let Latency     = 4;
 309   let NumMicroOps = 3;
 310 }
 311 def A57Write_8cyc_1L_1V_1I  : SchedWriteRes<[A57UnitL,
 312                                              A57UnitV,
 313                                              A57UnitI]> {
 314   let Latency     = 8;
 315   let NumMicroOps = 3;
 316 }
 317 def A57Write_9cyc_1L_1V_1I  : SchedWriteRes<[A57UnitL,
 318                                              A57UnitV,
 319                                              A57UnitI]> {
 320   let Latency     = 9;
 321   let NumMicroOps = 3;
 322 }