1 ============================
2 AMDGPU Instructions Notation
3 ============================
8 .. _amdgpu_syn_instruction_notation:
13 This is an overview of notation used to describe the syntax of AMDGPU assembler instructions.
15 This notation mimics the :ref:`syntax of assembler instructions<amdgpu_syn_instructions>`
16 except that instead of real operands and modifiers it provides references to their description.
24 This is the notation used to describe AMDGPU instructions:
26 ``<``\ :ref:`opcode description<amdgpu_syn_opcode_notation>`\ ``> <``\ :ref:`operands description<amdgpu_syn_instruction_operands_notation>`\ ``> <``\ :ref:`modifiers description<amdgpu_syn_instruction_modifiers_notation>`\ ``>``
28 .. _amdgpu_syn_opcode_notation:
38 .. _amdgpu_syn_instruction_operands_notation:
43 An instruction may have zero or more *operands*. They are comma-separated in the description:
45 ``<``\ :ref:`description of operand 0<amdgpu_syn_instruction_operand_notation>`\ ``>, <``\ :ref:`description of operand 1<amdgpu_syn_instruction_operand_notation>`\ ``>, ...``
47 The order of *operands* is fixed. *Operands* cannot be omitted
48 except for special cases described below.
50 .. _amdgpu_syn_instruction_operand_notation:
55 An operand is described using the following notation:
57 *<name><tag0><tag1>...*
61 * *name* is a link to a description of the operand.
62 * *tags* are optional. They are used to indicate special operand properties:
64 .. _amdgpu_syn_instruction_operand_tags:
66 ============== =================================================================================
68 ============== =================================================================================
69 :opt An optional operand.
70 :m An operand which may be used with
71 :ref:`VOP3 operand modifiers<amdgpu_synid_vop3_operand_modifiers>` or
72 :ref:`SDWA operand modifiers<amdgpu_synid_sdwa_operand_modifiers>`.
73 :dst An input operand which may also serve as a destination
74 if :ref:`glc<amdgpu_synid_glc>` modifier is specified.
75 :fx This is an *f32* or *f16* operand depending on
76 :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` modifier.
77 :<type> Operand *type* differs from *type*
78 :ref:`implied by the opcode name<amdgpu_syn_instruction_type>`.
79 This tag specifies actual operand *type*.
80 ============== =================================================================================
86 src1:m // src1 operand may be used with operand modifiers
87 vdata:dst // vdata operand may be used as both source and destination
88 vdst:u32 // vdst operand has u32 type
90 .. _amdgpu_syn_instruction_modifiers_notation:
95 An instruction may have zero or more optional *modifiers*. They are space-separated in the description:
97 ``<``\ :ref:`description of modifier 0<amdgpu_syn_instruction_modifier_notation>`\ ``> <``\ :ref:`description of modifier 1<amdgpu_syn_instruction_modifier_notation>`\ ``> ...``
99 The order of *modifiers* is fixed.
101 .. _amdgpu_syn_instruction_modifier_notation:
106 A *modifier* is described using the following notation:
110 Where *name* is a link to a description of the *modifier*.