tools/llvm-exegesis/lib/MCInstrDescView.h

   1 //===-- MCInstrDescView.h ---------------------------------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// \file
  10 /// Provide views around LLVM structures to represents an instruction instance,
  11 /// as well as its implicit and explicit arguments in a uniform way.
  12 /// Arguments that are explicit and independant (non tied) also have a Variable
  13 /// associated to them so the instruction can be fully defined by reading its
  14 /// Variables.
  15 ///
  16 //===----------------------------------------------------------------------===//
  17
  18 #ifndef LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
  19 #define LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H
  20
  21 #include <random>
  22 #include <unordered_map>
  23
  24 #include "RegisterAliasing.h"
  25 #include "llvm/ADT/ArrayRef.h"
  26 #include "llvm/ADT/Optional.h"
  27 #include "llvm/MC/MCInst.h"
  28 #include "llvm/MC/MCInstrDesc.h"
  29 #include "llvm/MC/MCInstrInfo.h"
  30
  31 namespace llvm {
  32 namespace exegesis {
  33
  34 // A variable represents the value associated to an Operand or a set of Operands
  35 // if they are tied together.
  36 struct Variable {
  37   // Returns the index of this Variable inside Instruction's Variable.
  38   unsigned getIndex() const;
  39
  40   // Returns the index of the Operand linked to this Variable.
  41   unsigned getPrimaryOperandIndex() const;
  42
  43   // Returns whether this Variable has more than one Operand linked to it.
  44   bool hasTiedOperands() const;
  45
  46   // The indices of the operands tied to this Variable.
  47   llvm::SmallVector<unsigned, 2> TiedOperands;
  48
  49   // The index of this Variable in Instruction.Variables and its associated
  50   // Value in InstructionBuilder.VariableValues.
  51   int Index = -1;
  52 };
  53
  54 // MCOperandInfo can only represents Explicit operands. This object gives a
  55 // uniform view of Implicit and Explicit Operands.
  56 // - Index: can be used to refer to MCInstrDesc::operands for Explicit operands.
  57 // - Tracker: is set for Register Operands and is used to keep track of possible
  58 // registers and the registers reachable from them (aliasing registers).
  59 // - Info: a shortcut for MCInstrDesc::operands()[Index].
  60 // - TiedToIndex: the index of the Operand holding the value or -1.
  61 // - ImplicitReg: a pointer to the register value when Operand is Implicit,
  62 // nullptr otherwise.
  63 // - VariableIndex: the index of the Variable holding the value for this Operand
  64 // or -1 if this operand is implicit.
  65 struct Operand {
  66   bool isExplicit() const;
  67   bool isImplicit() const;
  68   bool isImplicitReg() const;
  69   bool isDef() const;
  70   bool isUse() const;
  71   bool isReg() const;
  72   bool isTied() const;
  73   bool isVariable() const;
  74   bool isMemory() const;
  75   bool isImmediate() const;
  76   unsigned getIndex() const;
  77   unsigned getTiedToIndex() const;
  78   unsigned getVariableIndex() const;
  79   unsigned getImplicitReg() const;
  80   const RegisterAliasingTracker &getRegisterAliasing() const;
  81   const llvm::MCOperandInfo &getExplicitOperandInfo() const;
  82
  83   // Please use the accessors above and not the following fields.
  84   int Index = -1;
  85   bool IsDef = false;
  86   const RegisterAliasingTracker *Tracker = nullptr; // Set for Register Op.
  87   const llvm::MCOperandInfo *Info = nullptr;        // Set for Explicit Op.
  88   int TiedToIndex = -1;                             // Set for Reg&Explicit Op.
  89   const llvm::MCPhysReg *ImplicitReg = nullptr;     // Set for Implicit Op.
  90   int VariableIndex = -1;                           // Set for Explicit Op.
  91 };
  92
  93 // A view over an MCInstrDesc offering a convenient interface to compute
  94 // Register aliasing.
  95 struct Instruction {
  96   Instruction(const llvm::MCInstrInfo &InstrInfo,
  97               const RegisterAliasingTrackerCache &RATC, unsigned Opcode);
  98
  99   // Returns the Operand linked to this Variable.
 100   // In case the Variable is tied, the primary (i.e. Def) Operand is returned.
 101   const Operand &getPrimaryOperand(const Variable &Var) const;
 102
 103   // Whether this instruction is self aliasing through its tied registers.
 104   // Repeating this instruction is guaranteed to executes sequentially.
 105   bool hasTiedRegisters() const;
 106
 107   // Whether this instruction is self aliasing through its implicit registers.
 108   // Repeating this instruction is guaranteed to executes sequentially.
 109   bool hasAliasingImplicitRegisters() const;
 110
 111   // Whether this instruction is self aliasing through some registers.
 112   // Repeating this instruction may execute sequentially by picking aliasing
 113   // Use and Def registers. It may also execute in parallel by picking non
 114   // aliasing Use and Def registers.
 115   bool hasAliasingRegisters(const BitVector &ForbiddenRegisters) const;
 116
 117   // Whether this instruction's registers alias with OtherInstr's registers.
 118   bool hasAliasingRegistersThrough(const Instruction &OtherInstr,
 119                                    const BitVector &ForbiddenRegisters) const;
 120
 121   // Returns whether this instruction has Memory Operands.
 122   // Repeating this instruction executes sequentially with an instruction that
 123   // reads or write the same memory region.
 124   bool hasMemoryOperands() const;
 125
 126   // Returns whether this instruction as at least one use or one def.
 127   // Repeating this instruction may execute sequentially by adding an
 128   // instruction that aliases one of these.
 129   bool hasOneUseOrOneDef() const;
 130
 131   // Convenient function to help with debugging.
 132   void dump(const llvm::MCRegisterInfo &RegInfo,
 133             const RegisterAliasingTrackerCache &RATC,
 134             llvm::raw_ostream &Stream) const;
 135
 136   const llvm::MCInstrDesc *Description; // Never nullptr.
 137   llvm::StringRef Name;                 // The name of this instruction.
 138   llvm::SmallVector<Operand, 8> Operands;
 139   llvm::SmallVector<Variable, 4> Variables;
 140   llvm::BitVector ImplDefRegs; // The set of aliased implicit def registers.
 141   llvm::BitVector ImplUseRegs; // The set of aliased implicit use registers.
 142   llvm::BitVector AllDefRegs;  // The set of all aliased def registers.
 143   llvm::BitVector AllUseRegs;  // The set of all aliased use registers.
 144 };
 145
 146 // Instructions are expensive to instantiate. This class provides a cache of
 147 // Instructions with lazy construction.
 148 struct InstructionsCache {
 149   InstructionsCache(const llvm::MCInstrInfo &InstrInfo,
 150                     const RegisterAliasingTrackerCache &RATC);
 151
 152   // Returns the Instruction object corresponding to this Opcode.
 153   const Instruction &getInstr(unsigned Opcode) const;
 154
 155 private:
 156   const llvm::MCInstrInfo &InstrInfo;
 157   const RegisterAliasingTrackerCache &RATC;
 158   mutable std::unordered_map<unsigned, std::unique_ptr<Instruction>>
 159       Instructions;
 160 };
 161
 162 // Represents the assignment of a Register to an Operand.
 163 struct RegisterOperandAssignment {
 164   RegisterOperandAssignment(const Operand *Operand, llvm::MCPhysReg Reg)
 165       : Op(Operand), Reg(Reg) {}
 166
 167   const Operand *Op; // Pointer to an Explicit Register Operand.
 168   llvm::MCPhysReg Reg;
 169
 170   bool operator==(const RegisterOperandAssignment &other) const;
 171 };
 172
 173 // Represents a set of Operands that would alias through the use of some
 174 // Registers.
 175 // There are two reasons why operands would alias:
 176 // - The registers assigned to each of the operands are the same or alias each
 177 //   other (e.g. AX/AL)
 178 // - The operands are tied.
 179 struct AliasingRegisterOperands {
 180   llvm::SmallVector<RegisterOperandAssignment, 1> Defs; // Unlikely size() > 1.
 181   llvm::SmallVector<RegisterOperandAssignment, 2> Uses;
 182
 183   // True is Defs and Use contain an Implicit Operand.
 184   bool hasImplicitAliasing() const;
 185
 186   bool operator==(const AliasingRegisterOperands &other) const;
 187 };
 188
 189 // Returns all possible configurations leading Def registers of DefInstruction
 190 // to alias with Use registers of UseInstruction.
 191 struct AliasingConfigurations {
 192   AliasingConfigurations(const Instruction &DefInstruction,
 193                          const Instruction &UseInstruction);
 194
 195   bool empty() const; // True if no aliasing configuration is found.
 196   bool hasImplicitAliasing() const;
 197
 198   llvm::SmallVector<AliasingRegisterOperands, 32> Configurations;
 199 };
 200
 201 // Writes MCInst to OS.
 202 // This is not assembly but the internal LLVM's name for instructions and
 203 // registers.
 204 void DumpMCInst(const llvm::MCRegisterInfo &MCRegisterInfo,
 205                 const llvm::MCInstrInfo &MCInstrInfo,
 206                 const llvm::MCInst &MCInst, llvm::raw_ostream &OS);
 207
 208 } // namespace exegesis
 209 } // namespace llvm
 210
 211 #endif // LLVM_TOOLS_LLVM_EXEGESIS_MCINSTRDESCVIEW_H