lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

   1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This implements routines for translating functions from LLVM IR into
  10 // Machine IR.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "llvm/CodeGen/FunctionLoweringInfo.h"
  15 #include "llvm/Analysis/LegacyDivergenceAnalysis.h"
  16 #include "llvm/CodeGen/Analysis.h"
  17 #include "llvm/CodeGen/MachineFrameInfo.h"
  18 #include "llvm/CodeGen/MachineFunction.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineRegisterInfo.h"
  21 #include "llvm/CodeGen/TargetFrameLowering.h"
  22 #include "llvm/CodeGen/TargetInstrInfo.h"
  23 #include "llvm/CodeGen/TargetLowering.h"
  24 #include "llvm/CodeGen/TargetRegisterInfo.h"
  25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  26 #include "llvm/CodeGen/WasmEHFuncInfo.h"
  27 #include "llvm/CodeGen/WinEHFuncInfo.h"
  28 #include "llvm/IR/DataLayout.h"
  29 #include "llvm/IR/DerivedTypes.h"
  30 #include "llvm/IR/Function.h"
  31 #include "llvm/IR/Instructions.h"
  32 #include "llvm/IR/IntrinsicInst.h"
  33 #include "llvm/IR/LLVMContext.h"
  34 #include "llvm/IR/Module.h"
  35 #include "llvm/Support/Debug.h"
  36 #include "llvm/Support/ErrorHandling.h"
  37 #include "llvm/Support/MathExtras.h"
  38 #include "llvm/Support/raw_ostream.h"
  39 #include "llvm/Target/TargetOptions.h"
  40 #include <algorithm>
  41 using namespace llvm;
  42
  43 #define DEBUG_TYPE "function-lowering-info"
  44
  45 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
  46 /// PHI nodes or outside of the basic block that defines it, or used by a
  47 /// switch or atomic instruction, which may expand to multiple basic blocks.
  48 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
  49   if (I->use_empty()) return false;
  50   if (isa<PHINode>(I)) return true;
  51   const BasicBlock *BB = I->getParent();
  52   for (const User *U : I->users())
  53     if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
  54       return true;
  55
  56   return false;
  57 }
  58
  59 static ISD::NodeType getPreferredExtendForValue(const Value *V) {
  60   // For the users of the source value being used for compare instruction, if
  61   // the number of signed predicate is greater than unsigned predicate, we
  62   // prefer to use SIGN_EXTEND.
  63   //
  64   // With this optimization, we would be able to reduce some redundant sign or
  65   // zero extension instruction, and eventually more machine CSE opportunities
  66   // can be exposed.
  67   ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
  68   unsigned NumOfSigned = 0, NumOfUnsigned = 0;
  69   for (const User *U : V->users()) {
  70     if (const auto *CI = dyn_cast<CmpInst>(U)) {
  71       NumOfSigned += CI->isSigned();
  72       NumOfUnsigned += CI->isUnsigned();
  73     }
  74   }
  75   if (NumOfSigned > NumOfUnsigned)
  76     ExtendKind = ISD::SIGN_EXTEND;
  77
  78   return ExtendKind;
  79 }
  80
  81 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
  82                                SelectionDAG *DAG) {
  83   Fn = &fn;
  84   MF = &mf;
  85   TLI = MF->getSubtarget().getTargetLowering();
  86   RegInfo = &MF->getRegInfo();
  87   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
  88   unsigned StackAlign = TFI->getStackAlignment();
  89   DA = DAG->getDivergenceAnalysis();
  90
  91   // Check whether the function can return without sret-demotion.
  92   SmallVector<ISD::OutputArg, 4> Outs;
  93   CallingConv::ID CC = Fn->getCallingConv();
  94
  95   GetReturnInfo(CC, Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
  96                 mf.getDataLayout());
  97   CanLowerReturn =
  98       TLI->CanLowerReturn(CC, *MF, Fn->isVarArg(), Outs, Fn->getContext());
  99
 100   // If this personality uses funclets, we need to do a bit more work.
 101   DenseMap<const AllocaInst *, TinyPtrVector<int *>> CatchObjects;
 102   EHPersonality Personality = classifyEHPersonality(
 103       Fn->hasPersonalityFn() ? Fn->getPersonalityFn() : nullptr);
 104   if (isFuncletEHPersonality(Personality)) {
 105     // Calculate state numbers if we haven't already.
 106     WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
 107     if (Personality == EHPersonality::MSVC_CXX)
 108       calculateWinCXXEHStateNumbers(&fn, EHInfo);
 109     else if (isAsynchronousEHPersonality(Personality))
 110       calculateSEHStateNumbers(&fn, EHInfo);
 111     else if (Personality == EHPersonality::CoreCLR)
 112       calculateClrEHStateNumbers(&fn, EHInfo);
 113
 114     // Map all BB references in the WinEH data to MBBs.
 115     for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
 116       for (WinEHHandlerType &H : TBME.HandlerArray) {
 117         if (const AllocaInst *AI = H.CatchObj.Alloca)
 118           CatchObjects.insert({AI, {}}).first->second.push_back(
 119               &H.CatchObj.FrameIndex);
 120         else
 121           H.CatchObj.FrameIndex = INT_MAX;
 122       }
 123     }
 124   }
 125   if (Personality == EHPersonality::Wasm_CXX) {
 126     WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
 127     calculateWasmEHInfo(&fn, EHInfo);
 128   }
 129
 130   // Initialize the mapping of values to registers.  This is only set up for
 131   // instruction values that are used outside of the block that defines
 132   // them.
 133   for (const BasicBlock &BB : *Fn) {
 134     for (const Instruction &I : BB) {
 135       if (const AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
 136         Type *Ty = AI->getAllocatedType();
 137         unsigned Align =
 138           std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(Ty),
 139                    AI->getAlignment());
 140
 141         // Static allocas can be folded into the initial stack frame
 142         // adjustment. For targets that don't realign the stack, don't
 143         // do this if there is an extra alignment requirement.
 144         if (AI->isStaticAlloca() &&
 145             (TFI->isStackRealignable() || (Align <= StackAlign))) {
 146           const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
 147           uint64_t TySize = MF->getDataLayout().getTypeAllocSize(Ty);
 148
 149           TySize *= CUI->getZExtValue();   // Get total allocated size.
 150           if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
 151           int FrameIndex = INT_MAX;
 152           auto Iter = CatchObjects.find(AI);
 153           if (Iter != CatchObjects.end() && TLI->needsFixedCatchObjects()) {
 154             FrameIndex = MF->getFrameInfo().CreateFixedObject(
 155                 TySize, 0, /*IsImmutable=*/false, /*isAliased=*/true);
 156             MF->getFrameInfo().setObjectAlignment(FrameIndex, Align);
 157           } else {
 158             FrameIndex =
 159                 MF->getFrameInfo().CreateStackObject(TySize, Align, false, AI);
 160           }
 161
 162           StaticAllocaMap[AI] = FrameIndex;
 163           // Update the catch handler information.
 164           if (Iter != CatchObjects.end()) {
 165             for (int *CatchObjPtr : Iter->second)
 166               *CatchObjPtr = FrameIndex;
 167           }
 168         } else {
 169           // FIXME: Overaligned static allocas should be grouped into
 170           // a single dynamic allocation instead of using a separate
 171           // stack allocation for each one.
 172           if (Align <= StackAlign)
 173             Align = 0;
 174           // Inform the Frame Information that we have variable-sized objects.
 175           MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, AI);
 176         }
 177       }
 178
 179       // Look for inline asm that clobbers the SP register.
 180       if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
 181         ImmutableCallSite CS(&I);
 182         if (isa<InlineAsm>(CS.getCalledValue())) {
 183           unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
 184           const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
 185           std::vector<TargetLowering::AsmOperandInfo> Ops =
 186               TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, CS);
 187           for (TargetLowering::AsmOperandInfo &Op : Ops) {
 188             if (Op.Type == InlineAsm::isClobber) {
 189               // Clobbers don't have SDValue operands, hence SDValue().
 190               TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
 191               std::pair<unsigned, const TargetRegisterClass *> PhysReg =
 192                   TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
 193                                                     Op.ConstraintVT);
 194               if (PhysReg.first == SP)
 195                 MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
 196             }
 197           }
 198         }
 199       }
 200
 201       // Look for calls to the @llvm.va_start intrinsic. We can omit some
 202       // prologue boilerplate for variadic functions that don't examine their
 203       // arguments.
 204       if (const auto *II = dyn_cast<IntrinsicInst>(&I)) {
 205         if (II->getIntrinsicID() == Intrinsic::vastart)
 206           MF->getFrameInfo().setHasVAStart(true);
 207       }
 208
 209       // If we have a musttail call in a variadic function, we need to ensure we
 210       // forward implicit register parameters.
 211       if (const auto *CI = dyn_cast<CallInst>(&I)) {
 212         if (CI->isMustTailCall() && Fn->isVarArg())
 213           MF->getFrameInfo().setHasMustTailInVarArgFunc(true);
 214       }
 215
 216       // Mark values used outside their block as exported, by allocating
 217       // a virtual register for them.
 218       if (isUsedOutsideOfDefiningBlock(&I))
 219         if (!isa<AllocaInst>(I) || !StaticAllocaMap.count(cast<AllocaInst>(&I)))
 220           InitializeRegForValue(&I);
 221
 222       // Decide the preferred extend type for a value.
 223       PreferredExtendType[&I] = getPreferredExtendForValue(&I);
 224     }
 225   }
 226
 227   // Create an initial MachineBasicBlock for each LLVM BasicBlock in F.  This
 228   // also creates the initial PHI MachineInstrs, though none of the input
 229   // operands are populated.
 230   for (const BasicBlock &BB : *Fn) {
 231     // Don't create MachineBasicBlocks for imaginary EH pad blocks. These blocks
 232     // are really data, and no instructions can live here.
 233     if (BB.isEHPad()) {
 234       const Instruction *PadInst = BB.getFirstNonPHI();
 235       // If this is a non-landingpad EH pad, mark this function as using
 236       // funclets.
 237       // FIXME: SEH catchpads do not create EH scope/funclets, so we could avoid
 238       // setting this in such cases in order to improve frame layout.
 239       if (!isa<LandingPadInst>(PadInst)) {
 240         MF->setHasEHScopes(true);
 241         MF->setHasEHFunclets(true);
 242         MF->getFrameInfo().setHasOpaqueSPAdjustment(true);
 243       }
 244       if (isa<CatchSwitchInst>(PadInst)) {
 245         assert(&*BB.begin() == PadInst &&
 246                "WinEHPrepare failed to remove PHIs from imaginary BBs");
 247         continue;
 248       }
 249       if (isa<FuncletPadInst>(PadInst))
 250         assert(&*BB.begin() == PadInst && "WinEHPrepare failed to demote PHIs");
 251     }
 252
 253     MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&BB);
 254     MBBMap[&BB] = MBB;
 255     MF->push_back(MBB);
 256
 257     // Transfer the address-taken flag. This is necessary because there could
 258     // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
 259     // the first one should be marked.
 260     if (BB.hasAddressTaken())
 261       MBB->setHasAddressTaken();
 262
 263     // Mark landing pad blocks.
 264     if (BB.isEHPad())
 265       MBB->setIsEHPad();
 266
 267     // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
 268     // appropriate.
 269     for (const PHINode &PN : BB.phis()) {
 270       if (PN.use_empty())
 271         continue;
 272
 273       // Skip empty types
 274       if (PN.getType()->isEmptyTy())
 275         continue;
 276
 277       DebugLoc DL = PN.getDebugLoc();
 278       unsigned PHIReg = ValueMap[&PN];
 279       assert(PHIReg && "PHI node does not have an assigned virtual register!");
 280
 281       SmallVector<EVT, 4> ValueVTs;
 282       ComputeValueVTs(*TLI, MF->getDataLayout(), PN.getType(), ValueVTs);
 283       for (EVT VT : ValueVTs) {
 284         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
 285         const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
 286         for (unsigned i = 0; i != NumRegisters; ++i)
 287           BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
 288         PHIReg += NumRegisters;
 289       }
 290     }
 291   }
 292
 293   if (isFuncletEHPersonality(Personality)) {
 294     WinEHFuncInfo &EHInfo = *MF->getWinEHFuncInfo();
 295
 296     // Map all BB references in the WinEH data to MBBs.
 297     for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap) {
 298       for (WinEHHandlerType &H : TBME.HandlerArray) {
 299         if (H.Handler)
 300           H.Handler = MBBMap[H.Handler.get<const BasicBlock *>()];
 301       }
 302     }
 303     for (CxxUnwindMapEntry &UME : EHInfo.CxxUnwindMap)
 304       if (UME.Cleanup)
 305         UME.Cleanup = MBBMap[UME.Cleanup.get<const BasicBlock *>()];
 306     for (SEHUnwindMapEntry &UME : EHInfo.SEHUnwindMap) {
 307       const auto *BB = UME.Handler.get<const BasicBlock *>();
 308       UME.Handler = MBBMap[BB];
 309     }
 310     for (ClrEHUnwindMapEntry &CME : EHInfo.ClrEHUnwindMap) {
 311       const auto *BB = CME.Handler.get<const BasicBlock *>();
 312       CME.Handler = MBBMap[BB];
 313     }
 314   }
 315
 316   else if (Personality == EHPersonality::Wasm_CXX) {
 317     WasmEHFuncInfo &EHInfo = *MF->getWasmEHFuncInfo();
 318     // Map all BB references in the WinEH data to MBBs.
 319     DenseMap<BBOrMBB, BBOrMBB> NewMap;
 320     for (auto &KV : EHInfo.EHPadUnwindMap) {
 321       const auto *Src = KV.first.get<const BasicBlock *>();
 322       const auto *Dst = KV.second.get<const BasicBlock *>();
 323       NewMap[MBBMap[Src]] = MBBMap[Dst];
 324     }
 325     EHInfo.EHPadUnwindMap = std::move(NewMap);
 326   }
 327 }
 328
 329 /// clear - Clear out all the function-specific state. This returns this
 330 /// FunctionLoweringInfo to an empty state, ready to be used for a
 331 /// different function.
 332 void FunctionLoweringInfo::clear() {
 333   MBBMap.clear();
 334   ValueMap.clear();
 335   VirtReg2Value.clear();
 336   StaticAllocaMap.clear();
 337   LiveOutRegInfo.clear();
 338   VisitedBBs.clear();
 339   ArgDbgValues.clear();
 340   DescribedArgs.clear();
 341   ByValArgFrameIndexMap.clear();
 342   RegFixups.clear();
 343   RegsWithFixups.clear();
 344   StatepointStackSlots.clear();
 345   StatepointSpillMaps.clear();
 346   PreferredExtendType.clear();
 347 }
 348
 349 /// CreateReg - Allocate a single virtual register for the given type.
 350 unsigned FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) {
 351   return RegInfo->createVirtualRegister(
 352       MF->getSubtarget().getTargetLowering()->getRegClassFor(VT, isDivergent));
 353 }
 354
 355 /// CreateRegs - Allocate the appropriate number of virtual registers of
 356 /// the correctly promoted or expanded types.  Assign these registers
 357 /// consecutive vreg numbers and return the first assigned number.
 358 ///
 359 /// In the case that the given value has struct or array type, this function
 360 /// will assign registers for each member or element.
 361 ///
 362 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty, bool isDivergent) {
 363   const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
 364
 365   SmallVector<EVT, 4> ValueVTs;
 366   ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
 367
 368   unsigned FirstReg = 0;
 369   for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
 370     EVT ValueVT = ValueVTs[Value];
 371     MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
 372
 373     unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
 374     for (unsigned i = 0; i != NumRegs; ++i) {
 375       unsigned R = CreateReg(RegisterVT, isDivergent);
 376       if (!FirstReg) FirstReg = R;
 377     }
 378   }
 379   return FirstReg;
 380 }
 381
 382 unsigned FunctionLoweringInfo::CreateRegs(const Value *V) {
 383   return CreateRegs(V->getType(), DA && !TLI->requiresUniformRegister(*MF, V) &&
 384                                       DA->isDivergent(V));
 385 }
 386
 387 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
 388 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
 389 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
 390 /// the larger bit width by zero extension. The bit width must be no smaller
 391 /// than the LiveOutInfo's existing bit width.
 392 const FunctionLoweringInfo::LiveOutInfo *
 393 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
 394   if (!LiveOutRegInfo.inBounds(Reg))
 395     return nullptr;
 396
 397   LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
 398   if (!LOI->IsValid)
 399     return nullptr;
 400
 401   if (BitWidth > LOI->Known.getBitWidth()) {
 402     LOI->NumSignBits = 1;
 403     LOI->Known = LOI->Known.zext(BitWidth, false /* => any extend */);
 404   }
 405
 406   return LOI;
 407 }
 408
 409 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
 410 /// register based on the LiveOutInfo of its operands.
 411 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
 412   Type *Ty = PN->getType();
 413   if (!Ty->isIntegerTy() || Ty->isVectorTy())
 414     return;
 415
 416   SmallVector<EVT, 1> ValueVTs;
 417   ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
 418   assert(ValueVTs.size() == 1 &&
 419          "PHIs with non-vector integer types should have a single VT.");
 420   EVT IntVT = ValueVTs[0];
 421
 422   if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
 423     return;
 424   IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
 425   unsigned BitWidth = IntVT.getSizeInBits();
 426
 427   unsigned DestReg = ValueMap[PN];
 428   if (!Register::isVirtualRegister(DestReg))
 429     return;
 430   LiveOutRegInfo.grow(DestReg);
 431   LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
 432
 433   Value *V = PN->getIncomingValue(0);
 434   if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
 435     DestLOI.NumSignBits = 1;
 436     DestLOI.Known = KnownBits(BitWidth);
 437     return;
 438   }
 439
 440   if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
 441     APInt Val = CI->getValue().zextOrTrunc(BitWidth);
 442     DestLOI.NumSignBits = Val.getNumSignBits();
 443     DestLOI.Known.Zero = ~Val;
 444     DestLOI.Known.One = Val;
 445   } else {
 446     assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
 447                                 "CopyToReg node was created.");
 448     unsigned SrcReg = ValueMap[V];
 449     if (!Register::isVirtualRegister(SrcReg)) {
 450       DestLOI.IsValid = false;
 451       return;
 452     }
 453     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
 454     if (!SrcLOI) {
 455       DestLOI.IsValid = false;
 456       return;
 457     }
 458     DestLOI = *SrcLOI;
 459   }
 460
 461   assert(DestLOI.Known.Zero.getBitWidth() == BitWidth &&
 462          DestLOI.Known.One.getBitWidth() == BitWidth &&
 463          "Masks should have the same bit width as the type.");
 464
 465   for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
 466     Value *V = PN->getIncomingValue(i);
 467     if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
 468       DestLOI.NumSignBits = 1;
 469       DestLOI.Known = KnownBits(BitWidth);
 470       return;
 471     }
 472
 473     if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
 474       APInt Val = CI->getValue().zextOrTrunc(BitWidth);
 475       DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
 476       DestLOI.Known.Zero &= ~Val;
 477       DestLOI.Known.One &= Val;
 478       continue;
 479     }
 480
 481     assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
 482                                 "its CopyToReg node was created.");
 483     unsigned SrcReg = ValueMap[V];
 484     if (!Register::isVirtualRegister(SrcReg)) {
 485       DestLOI.IsValid = false;
 486       return;
 487     }
 488     const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
 489     if (!SrcLOI) {
 490       DestLOI.IsValid = false;
 491       return;
 492     }
 493     DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
 494     DestLOI.Known.Zero &= SrcLOI->Known.Zero;
 495     DestLOI.Known.One &= SrcLOI->Known.One;
 496   }
 497 }
 498
 499 /// setArgumentFrameIndex - Record frame index for the byval
 500 /// argument. This overrides previous frame index entry for this argument,
 501 /// if any.
 502 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
 503                                                  int FI) {
 504   ByValArgFrameIndexMap[A] = FI;
 505 }
 506
 507 /// getArgumentFrameIndex - Get frame index for the byval argument.
 508 /// If the argument does not have any assigned frame index then 0 is
 509 /// returned.
 510 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
 511   auto I = ByValArgFrameIndexMap.find(A);
 512   if (I != ByValArgFrameIndexMap.end())
 513     return I->second;
 514   LLVM_DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
 515   return INT_MAX;
 516 }
 517
 518 unsigned FunctionLoweringInfo::getCatchPadExceptionPointerVReg(
 519     const Value *CPI, const TargetRegisterClass *RC) {
 520   MachineRegisterInfo &MRI = MF->getRegInfo();
 521   auto I = CatchPadExceptionPointers.insert({CPI, 0});
 522   unsigned &VReg = I.first->second;
 523   if (I.second)
 524     VReg = MRI.createVirtualRegister(RC);
 525   assert(VReg && "null vreg in exception pointer table!");
 526   return VReg;
 527 }
 528
 529 const Value *
 530 FunctionLoweringInfo::getValueFromVirtualReg(unsigned Vreg) {
 531   if (VirtReg2Value.empty()) {
 532     SmallVector<EVT, 4> ValueVTs;
 533     for (auto &P : ValueMap) {
 534       ValueVTs.clear();
 535       ComputeValueVTs(*TLI, Fn->getParent()->getDataLayout(),
 536                       P.first->getType(), ValueVTs);
 537       unsigned Reg = P.second;
 538       for (EVT VT : ValueVTs) {
 539         unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
 540         for (unsigned i = 0, e = NumRegisters; i != e; ++i)
 541           VirtReg2Value[Reg++] = P.first;
 542       }
 543     }
 544   }
 545   return VirtReg2Value.lookup(Vreg);
 546 }