lib/Target/AArch64/AArch64SchedExynosM1.td

   1 //=- AArch64SchedExynosM1.td - Samsung Exynos M1 Sched Defs --*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for the Samsung Exynos M1 to support
  10 // instruction scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // The Exynos-M1 is a traditional superscalar microprocessor with a
  16 // 4-wide in-order stage for decode and dispatch and a wider issue stage.
  17 // The execution units and loads and stores are out-of-order.
  18
  19 def ExynosM1Model : SchedMachineModel {
  20   let IssueWidth            =  4; // Up to 4 uops per cycle.
  21   let MicroOpBufferSize     = 96; // ROB size.
  22   let LoopMicroOpBufferSize = 24; // Based on the instruction queue size.
  23   let LoadLatency           =  4; // Optimistic load cases.
  24   let MispredictPenalty     = 14; // Minimum branch misprediction penalty.
  25   let CompleteModel         =  1; // Use the default model otherwise.
  26
  27   list<Predicate> UnsupportedFeatures = SVEUnsupported.F;
  28 }
  29
  30 //===----------------------------------------------------------------------===//
  31 // Define each kind of processor resource and number available on the Exynos-M1,
  32 // which has 9 pipelines, each with its own queue with out-of-order dispatch.
  33
  34 let SchedModel = ExynosM1Model in {
  35
  36 def M1UnitA  : ProcResource<2>; // Simple integer
  37 def M1UnitC  : ProcResource<1>; // Simple and complex integer
  38 def M1UnitD  : ProcResource<1>; // Integer division (inside C, serialized)
  39 def M1UnitB  : ProcResource<2>; // Branch
  40 def M1UnitL  : ProcResource<1>; // Load
  41 def M1UnitS  : ProcResource<1>; // Store
  42 def M1PipeF0 : ProcResource<1>; // FP #0
  43 let Super = M1PipeF0 in {
  44   def M1UnitFMAC   : ProcResource<1>; // FP multiplication
  45   def M1UnitNAL0   : ProcResource<1>; // Simple vector
  46   def M1UnitNMISC  : ProcResource<1>; // Miscellanea
  47   def M1UnitFCVT   : ProcResource<1>; // FP conversion
  48   def M1UnitNCRYPT : ProcResource<1>; // Cryptographic
  49 }
  50 def M1PipeF1 : ProcResource<1>; // FP #1
  51 let Super = M1PipeF1 in {
  52   def M1UnitFADD : ProcResource<1>; // Simple FP
  53   def M1UnitNAL1 : ProcResource<1>; // Simple vector
  54   def M1UnitFVAR : ProcResource<1>; // FP division & square root (serialized)
  55   def M1UnitFST  : ProcResource<1>; // FP store
  56 }
  57
  58 def M1UnitALU  : ProcResGroup<[M1UnitA,
  59                                M1UnitC]>;    // All integer
  60 def M1UnitNALU : ProcResGroup<[M1UnitNAL0,
  61                                M1UnitNAL1]>; // All simple vector
  62
  63 //===----------------------------------------------------------------------===//
  64 // Coarse scheduling model.
  65
  66 def M1WriteA1 : SchedWriteRes<[M1UnitALU]> { let Latency = 1; }
  67 def M1WriteA2 : SchedWriteRes<[M1UnitALU]> { let Latency = 2; }
  68 def M1WriteAA : SchedWriteRes<[M1UnitALU]> { let Latency = 2;
  69                                              let ResourceCycles = [2]; }
  70 def M1WriteAB : SchedWriteRes<[M1UnitALU,
  71                                M1UnitC]>   { let Latency = 1;
  72                                              let NumMicroOps = 2; }
  73 def M1WriteAC : SchedWriteRes<[M1UnitALU,
  74                                M1UnitALU,
  75                                M1UnitC]>   { let Latency = 2;
  76                                              let NumMicroOps = 3; }
  77 def M1WriteAD : SchedWriteRes<[M1UnitALU,
  78                                M1UnitC]>   { let Latency = 2;
  79                                              let NumMicroOps = 2; }
  80 def M1WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M1WriteA1]>,
  81                                    SchedVar<ExynosLogicPred, [M1WriteA1]>,
  82                                    SchedVar<NoSchedPred,     [M1WriteAA]>]>;
  83 def M1WriteC1 : SchedWriteRes<[M1UnitC]>   { let Latency = 1; }
  84 def M1WriteC2 : SchedWriteRes<[M1UnitC]>   { let Latency = 2; }
  85
  86 def M1WriteB1 : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
  87 def M1WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M1WriteAC]>,
  88                                    SchedVar<NoSchedPred,            [M1WriteAB]>]>;
  89
  90 def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
  91 def M1WriteL6 : SchedWriteRes<[M1UnitL]> { let Latency = 6; }
  92 def M1WriteLA : SchedWriteRes<[M1UnitL]> { let Latency = 6;
  93                                            let ResourceCycles = [2]; }
  94 def M1WriteLB : SchedWriteRes<[M1UnitL,
  95                                M1UnitA]> { let Latency = 4;
  96                                            let NumMicroOps = 2; }
  97 def M1WriteLC : SchedWriteRes<[M1UnitL,
  98                                M1UnitA]> { let Latency = 5;
  99                                            let NumMicroOps = 2; }
 100 def M1WriteLD : SchedWriteRes<[M1UnitL,
 101                                M1UnitA]> { let Latency = 6;
 102                                            let NumMicroOps = 2;
 103                                            let ResourceCycles = [2, 1]; }
 104 def M1WriteLH : SchedWriteRes<[]>        { let Latency = 5;
 105                                            let NumMicroOps = 0; }
 106 def M1WriteLX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteLC]>,
 107                                    SchedVar<NoSchedPred,   [M1WriteL5]>]>;
 108
 109 def M1WriteS1 : SchedWriteRes<[M1UnitS]>   { let Latency = 1; }
 110 def M1WriteS3 : SchedWriteRes<[M1UnitS]>   { let Latency = 3; }
 111 def M1WriteS4 : SchedWriteRes<[M1UnitS]>   { let Latency = 4; }
 112 def M1WriteSA : SchedWriteRes<[M1UnitS,
 113                                M1UnitFST,
 114                                M1UnitA]>   { let Latency = 3;
 115                                              let NumMicroOps = 2; }
 116 def M1WriteSB : SchedWriteRes<[M1UnitS,
 117                                M1UnitFST,
 118                                M1UnitS,
 119                                M1UnitFST,
 120                                M1UnitA]>   { let Latency = 3;
 121                                              let NumMicroOps = 3; }
 122 def M1WriteSC : SchedWriteRes<[M1UnitS,
 123                                M1UnitA]>   { let Latency = 2;
 124                                              let NumMicroOps = 2; }
 125 def M1WriteSX : SchedWriteVariant<[SchedVar<ScaledIdxPred, [M1WriteSC]>,
 126                                    SchedVar<NoSchedPred,   [M1WriteS1]>]>;
 127
 128 def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
 129                                       SchedVar<NoSchedPred,   [ReadDefault]>]>;
 130
 131 // Branch instructions.
 132 def : WriteRes<WriteBr,    []>        { let Latency = 0; }
 133 def : WriteRes<WriteBrReg, [M1UnitC]> { let Latency = 1; }
 134
 135 // Arithmetic and logical integer instructions.
 136 def : WriteRes<WriteI,     [M1UnitALU]> { let Latency = 1; }
 137 def : WriteRes<WriteISReg, [M1UnitALU]> { let Latency = 1; }
 138 def : WriteRes<WriteIEReg, [M1UnitALU]> { let Latency = 1; }
 139 def : WriteRes<WriteIS,    [M1UnitALU]> { let Latency = 1; }
 140
 141 // Move instructions.
 142 def : WriteRes<WriteImm, [M1UnitALU]> { let Latency = 1; }
 143
 144 // Divide and multiply instructions.
 145 def : WriteRes<WriteID32, [M1UnitC,
 146                            M1UnitD]> { let Latency = 13;
 147                                        let ResourceCycles = [1, 13]; }
 148 def : WriteRes<WriteID64, [M1UnitC,
 149                            M1UnitD]> { let Latency = 21;
 150                                        let ResourceCycles = [1, 21]; }
 151 // TODO: Long multiplication take 5 cycles and also the ALU.
 152 def : WriteRes<WriteIM32, [M1UnitC]> { let Latency = 3; }
 153 def : WriteRes<WriteIM64, [M1UnitC]> { let Latency = 4;
 154                                        let ResourceCycles = [2]; }
 155
 156 // Miscellaneous instructions.
 157 def : WriteRes<WriteExtr, [M1UnitALU,
 158                            M1UnitALU]> { let Latency = 2;
 159                                          let NumMicroOps = 2; }
 160
 161 // Addressing modes.
 162 def : WriteRes<WriteAdr, []> { let Latency = 1;
 163                                let NumMicroOps = 0; }
 164 def : SchedAlias<ReadAdrBase, M1ReadAdrBase>;
 165
 166 // Load instructions.
 167 def : WriteRes<WriteLD,    [M1UnitL]>   { let Latency = 4; }
 168 def : WriteRes<WriteLDHi,  []>          { let Latency = 4;
 169                                           let NumMicroOps = 0; }
 170 def : SchedAlias<WriteLDIdx, M1WriteLX>;
 171
 172 // Store instructions.
 173 def : WriteRes<WriteST,    [M1UnitS]> { let Latency = 1; }
 174 def : WriteRes<WriteSTP,   [M1UnitS]> { let Latency = 1; }
 175 def : WriteRes<WriteSTX,   [M1UnitS]> { let Latency = 1; }
 176 def : SchedAlias<WriteSTIdx, M1WriteSX>;
 177
 178 // FP data instructions.
 179 def : WriteRes<WriteF,    [M1UnitFADD]>  { let Latency = 3; }
 180 def : WriteRes<WriteFCmp, [M1UnitNMISC]> { let Latency = 4; }
 181 def : WriteRes<WriteFDiv, [M1UnitFVAR]>  { let Latency = 15;
 182                                            let ResourceCycles = [15]; }
 183 def : WriteRes<WriteFMul, [M1UnitFMAC]>  { let Latency = 4; }
 184
 185 // FP miscellaneous instructions.
 186 def : WriteRes<WriteFCvt,  [M1UnitFCVT]> { let Latency = 3; }
 187 def : WriteRes<WriteFImm,  [M1UnitNALU]> { let Latency = 1; }
 188 def : WriteRes<WriteFCopy, [M1UnitS]>    { let Latency = 4; }
 189
 190 // FP load instructions.
 191 def : WriteRes<WriteVLD,   [M1UnitL]> { let Latency = 5; }
 192
 193 // FP store instructions.
 194 def : WriteRes<WriteVST, [M1UnitS,
 195                           M1UnitFST]> { let Latency = 1;
 196                                         let NumMicroOps = 1; }
 197
 198 // ASIMD FP instructions.
 199 def : WriteRes<WriteV, [M1UnitFADD]> { let Latency = 3; }
 200
 201 // Other miscellaneous instructions.
 202 def : WriteRes<WriteAtomic,  []> { let Unsupported = 1; }
 203 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
 204 def : WriteRes<WriteHint,    []> { let Latency = 1; }
 205 def : WriteRes<WriteSys,     []> { let Latency = 1; }
 206
 207 //===----------------------------------------------------------------------===//
 208 // Fast forwarding.
 209
 210 // TODO: Add FP register forwarding rules.
 211 def : ReadAdvance<ReadI,       0>;
 212 def : ReadAdvance<ReadISReg,   0>;
 213 def : ReadAdvance<ReadIEReg,   0>;
 214 def : ReadAdvance<ReadIM,      0>;
 215 // TODO: The forwarding for WriteIM32 saves actually 2 cycles.
 216 def : ReadAdvance<ReadIMA,     3, [WriteIM32, WriteIM64]>;
 217 def : ReadAdvance<ReadID,      0>;
 218 def : ReadAdvance<ReadExtrHi,  0>;
 219 def : ReadAdvance<ReadAdrBase, 0>;
 220 def : ReadAdvance<ReadVLD,     0>;
 221
 222 //===----------------------------------------------------------------------===//
 223 // Finer scheduling model.
 224
 225 def M1WriteNEONA   : SchedWriteRes<[M1UnitNALU,
 226                                     M1UnitNALU,
 227                                     M1UnitFADD]>   { let Latency = 9;
 228                                                      let NumMicroOps = 3; }
 229 def M1WriteNEONB   : SchedWriteRes<[M1UnitNALU,
 230                                     M1UnitFST]>    { let Latency = 5;
 231                                                      let NumMicroOps = 2;}
 232 def M1WriteNEONC   : SchedWriteRes<[M1UnitNALU,
 233                                     M1UnitFST]>    { let Latency = 6;
 234                                                      let NumMicroOps = 2; }
 235 def M1WriteNEOND   : SchedWriteRes<[M1UnitNALU,
 236                                     M1UnitFST,
 237                                     M1UnitL]>      { let Latency = 10;
 238                                                      let NumMicroOps = 3; }
 239 def M1WriteNEONE   : SchedWriteRes<[M1UnitFCVT,
 240                                     M1UnitFST]>    { let Latency = 8;
 241                                                      let NumMicroOps = 2; }
 242 def M1WriteNEONF   : SchedWriteRes<[M1UnitFCVT,
 243                                     M1UnitFST,
 244                                     M1UnitL]>      { let Latency = 13;
 245                                                      let NumMicroOps = 3; }
 246 def M1WriteNEONG   : SchedWriteRes<[M1UnitNMISC,
 247                                     M1UnitFST]>    { let Latency = 6;
 248                                                      let NumMicroOps = 2; }
 249 def M1WriteNEONH   : SchedWriteRes<[M1UnitNALU,
 250                                     M1UnitFST]>    { let Latency = 3;
 251                                                      let NumMicroOps = 2; }
 252 def M1WriteNEONI   : SchedWriteRes<[M1UnitFST,
 253                                     M1UnitL]>      { let Latency = 9;
 254                                                      let NumMicroOps = 2; }
 255 def M1WriteNEONJ   : SchedWriteRes<[M1UnitNMISC,
 256                                     M1UnitFMAC]>   { let Latency = 6;
 257                                                      let NumMicroOps = 2; }
 258 def M1WriteNEONK   : SchedWriteRes<[M1UnitNMISC,
 259                                     M1UnitFMAC]>   { let Latency = 7;
 260                                                      let NumMicroOps = 2; }
 261 def M1WriteNEONL   : SchedWriteRes<[M1UnitNALU]>   { let Latency = 2;
 262                                                      let ResourceCycles = [2]; }
 263 def M1WriteFADD3   : SchedWriteRes<[M1UnitFADD]>   { let Latency = 3; }
 264 def M1WriteFCVT3   : SchedWriteRes<[M1UnitFCVT]>   { let Latency = 3; }
 265 def M1WriteFCVT4   : SchedWriteRes<[M1UnitFCVT]>   { let Latency = 4; }
 266 def M1WriteFMAC4   : SchedWriteRes<[M1UnitFMAC]>   { let Latency = 4; }
 267 def M1WriteFMAC5   : SchedWriteRes<[M1UnitFMAC]>   { let Latency = 5; }
 268 // TODO
 269 def M1WriteFVAR15  : SchedWriteRes<[M1UnitFVAR]>   { let Latency = 15;
 270                                                      let ResourceCycles = [15]; }
 271 def M1WriteFVAR23  : SchedWriteRes<[M1UnitFVAR]>   { let Latency = 23;
 272                                                      let ResourceCycles = [23]; }
 273 def M1WriteNALU1   : SchedWriteRes<[M1UnitNALU]>   { let Latency = 1; }
 274 def M1WriteNALU2   : SchedWriteRes<[M1UnitNALU]>   { let Latency = 2; }
 275 def M1WriteNAL11   : SchedWriteRes<[M1UnitNAL1]>   { let Latency = 1; }
 276 def M1WriteNAL12   : SchedWriteRes<[M1UnitNAL1]>   { let Latency = 2; }
 277 def M1WriteNAL13   : SchedWriteRes<[M1UnitNAL1]>   { let Latency = 3; }
 278 def M1WriteNCRYPT1 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 1; }
 279 def M1WriteNCRYPT5 : SchedWriteRes<[M1UnitNCRYPT]> { let Latency = 5; }
 280 def M1WriteNMISC1  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 1; }
 281 def M1WriteNMISC2  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 2; }
 282 def M1WriteNMISC3  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 3; }
 283 def M1WriteNMISC4  : SchedWriteRes<[M1UnitNMISC]>  { let Latency = 4; }
 284 def M1WriteTB      : SchedWriteRes<[M1UnitC,
 285                                     M1UnitALU]>    { let Latency = 2;
 286                                                      let NumMicroOps = 2; }
 287 def M1WriteVLDA    : SchedWriteRes<[M1UnitL,
 288                                     M1UnitL]>      { let Latency = 6;
 289                                                      let NumMicroOps = 2; }
 290 def M1WriteVLDB    : SchedWriteRes<[M1UnitL,
 291                                     M1UnitL,
 292                                     M1UnitL]>      { let Latency = 7;
 293                                                      let NumMicroOps = 3; }
 294 def M1WriteVLDC    : SchedWriteRes<[M1UnitL,
 295                                     M1UnitL,
 296                                     M1UnitL,
 297                                     M1UnitL]>      { let Latency = 8;
 298                                                      let NumMicroOps = 4; }
 299 def M1WriteVLDD    : SchedWriteRes<[M1UnitL,
 300                                     M1UnitNALU]>   { let Latency = 7;
 301                                                      let NumMicroOps = 2;
 302                                                      let ResourceCycles = [2, 1]; }
 303 def M1WriteVLDE    : SchedWriteRes<[M1UnitL,
 304                                     M1UnitNALU]>   { let Latency = 6;
 305                                                      let NumMicroOps = 2; }
 306 def M1WriteVLDF    : SchedWriteRes<[M1UnitL,
 307                                     M1UnitL]>      { let Latency = 10;
 308                                                      let NumMicroOps = 2;
 309                                                      let ResourceCycles = [1, 1]; }
 310 def M1WriteVLDG    : SchedWriteRes<[M1UnitL,
 311                                     M1UnitNALU,
 312                                     M1UnitNALU]>   { let Latency = 7;
 313                                                      let NumMicroOps = 3;
 314                                                      let ResourceCycles = [2, 1, 1]; }
 315 def M1WriteVLDH    : SchedWriteRes<[M1UnitL,
 316                                     M1UnitNALU,
 317                                     M1UnitNALU]>   { let Latency = 6;
 318                                                      let NumMicroOps = 3; }
 319 def M1WriteVLDI    : SchedWriteRes<[M1UnitL,
 320                                     M1UnitL,
 321                                     M1UnitL]>      { let Latency = 12;
 322                                                      let NumMicroOps = 3;
 323                                                      let ResourceCycles = [2, 2, 2]; }
 324 def M1WriteVLDJ    : SchedWriteRes<[M1UnitL,
 325                                     M1UnitNALU,
 326                                     M1UnitNALU,
 327                                     M1UnitNALU]>   { let Latency = 9;
 328                                                      let NumMicroOps = 4;
 329                                                      let ResourceCycles = [2, 1, 1, 1]; }
 330 def M1WriteVLDK    : SchedWriteRes<[M1UnitL,
 331                                     M1UnitNALU,
 332                                     M1UnitNALU,
 333                                     M1UnitNALU,
 334                                     M1UnitNALU]>   { let Latency = 9;
 335                                                      let NumMicroOps = 5;
 336                                                      let ResourceCycles = [2, 1, 1, 1, 1]; }
 337 def M1WriteVLDL    : SchedWriteRes<[M1UnitL,
 338                                     M1UnitNALU,
 339                                     M1UnitNALU,
 340                                     M1UnitL,
 341                                     M1UnitNALU]>   { let Latency = 7;
 342                                                      let NumMicroOps = 5;
 343                                                      let ResourceCycles = [1, 1, 1, 1, 1]; }
 344 def M1WriteVLDM    : SchedWriteRes<[M1UnitL,
 345                                     M1UnitNALU,
 346                                     M1UnitNALU,
 347                                     M1UnitL,
 348                                     M1UnitNALU,
 349                                     M1UnitNALU]>   { let Latency = 7;
 350                                                      let NumMicroOps = 6;
 351                                                      let ResourceCycles = [1, 1, 1, 1, 1, 1]; }
 352 def M1WriteVLDN    : SchedWriteRes<[M1UnitL,
 353                                     M1UnitL,
 354                                     M1UnitL,
 355                                     M1UnitL]>      { let Latency = 14;
 356                                                      let NumMicroOps = 4;
 357                                                      let ResourceCycles = [2, 1, 2, 1]; }
 358 def M1WriteVSTA    : WriteSequence<[WriteVST], 2>;
 359 def M1WriteVSTB    : WriteSequence<[WriteVST], 3>;
 360 def M1WriteVSTC    : WriteSequence<[WriteVST], 4>;
 361 def M1WriteVSTD    : SchedWriteRes<[M1UnitS,
 362                                     M1UnitFST,
 363                                     M1UnitFST]>    { let Latency = 7;
 364                                                      let NumMicroOps = 2;
 365                                                      let ResourceCycles = [7, 1, 1]; }
 366 def M1WriteVSTE    : SchedWriteRes<[M1UnitS,
 367                                     M1UnitFST,
 368                                     M1UnitS,
 369                                     M1UnitFST,
 370                                     M1UnitFST]>    { let Latency = 8;
 371                                                      let NumMicroOps = 3;
 372                                                      let ResourceCycles = [7, 1, 1, 1, 1]; }
 373 def M1WriteVSTF    : SchedWriteRes<[M1UnitNALU,
 374                                     M1UnitS,
 375                                     M1UnitFST,
 376                                     M1UnitS,
 377                                     M1UnitFST,
 378                                     M1UnitFST,
 379                                     M1UnitFST]>     { let Latency = 15;
 380                                                       let NumMicroOps = 5;
 381                                                       let ResourceCycles = [1, 7, 1, 7, 1, 1, 1]; }
 382 def M1WriteVSTG    : SchedWriteRes<[M1UnitNALU,
 383                                     M1UnitS,
 384                                     M1UnitFST,
 385                                     M1UnitS,
 386                                     M1UnitFST,
 387                                     M1UnitS,
 388                                     M1UnitFST,
 389                                     M1UnitFST,
 390                                     M1UnitFST]>     { let Latency = 16;
 391                                                       let NumMicroOps = 6;
 392                                                       let ResourceCycles = [1, 7, 1, 7, 1, 1, 1, 1, 1]; }
 393 def M1WriteVSTH    : SchedWriteRes<[M1UnitNALU,
 394                                     M1UnitS,
 395                                     M1UnitFST,
 396                                     M1UnitFST,
 397                                     M1UnitFST]>     { let Latency = 14;
 398                                                       let NumMicroOps = 4;
 399                                                       let ResourceCycles = [1, 7, 1, 7, 1]; }
 400 def M1WriteVSTI    : SchedWriteRes<[M1UnitNALU,
 401                                     M1UnitS,
 402                                     M1UnitFST,
 403                                     M1UnitS,
 404                                     M1UnitFST,
 405                                     M1UnitS,
 406                                     M1UnitFST,
 407                                     M1UnitS,
 408                                     M1UnitFST,
 409                                     M1UnitFST,
 410                                     M1UnitFST]>     { let Latency = 17;
 411                                                       let NumMicroOps = 7;
 412                                                       let ResourceCycles = [1, 7, 1, 7, 1, 1, 1, 1, 1, 1, 1]; }
 413
 414 // Special cases.
 415 def M1WriteAES  : SchedWriteRes<[M1UnitNCRYPT]>     { let Latency = 1; }
 416 def M1WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M1WriteNALU1]>,
 417                                      SchedVar<NoSchedPred,  [M1WriteA1]>]>;
 418
 419 // Fast forwarding.
 420 def M1ReadAES : SchedReadAdvance<1, [M1WriteAES]>;
 421
 422 // Branch instructions
 423 def : InstRW<[M1WriteB1], (instrs Bcc)>;
 424 def : InstRW<[M1WriteA1], (instrs BL)>;
 425 def : InstRW<[M1WriteBX], (instrs BLR)>;
 426 def : InstRW<[M1WriteC1], (instregex "^CBN?Z[WX]")>;
 427 def : InstRW<[M1WriteAD], (instregex "^TBN?Z[WX]")>;
 428
 429 // Arithmetic and logical integer instructions.
 430 def : InstRW<[M1WriteAX], (instregex ".+rx(64)?$")>;
 431 def : InstRW<[M1WriteAX], (instregex ".+rs$")>;
 432
 433 // Move instructions.
 434 def : InstRW<[M1WriteCOPY], (instrs COPY)>;
 435
 436 // Divide and multiply instructions.
 437
 438 // Miscellaneous instructions.
 439
 440 // Load instructions.
 441 def : InstRW<[M1WriteLB,
 442               WriteLDHi,
 443               WriteAdr],    (instregex "^LDP(SW|W|X)(post|pre)")>;
 444 def : InstRW<[M1WriteLC,
 445               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
 446 def : InstRW<[M1WriteL5,
 447               ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
 448 def : InstRW<[M1WriteLC,
 449               ReadAdrBase], (instrs PRFMroW)>;
 450 def : InstRW<[M1WriteL5,
 451               ReadAdrBase], (instrs PRFMroX)>;
 452
 453 // Store instructions.
 454 def : InstRW<[M1WriteSC,
 455               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>;
 456 def : InstRW<[WriteST,
 457               ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>;
 458
 459 // FP data instructions.
 460 def : InstRW<[M1WriteNALU1],  (instregex "^F(ABS|NEG)[DS]r")>;
 461 def : InstRW<[M1WriteFADD3],  (instregex "^F(ADD|SUB)[DS]rr")>;
 462 def : InstRW<[M1WriteNEONG],  (instregex "^FCCMPE?[DS]rr")>;
 463 def : InstRW<[M1WriteNMISC4], (instregex "^FCMPE?[DS]r")>;
 464 def : InstRW<[M1WriteFVAR15], (instrs FDIVSrr)>;
 465 def : InstRW<[M1WriteFVAR23], (instrs FDIVDrr)>;
 466 def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN).+rr")>;
 467 def : InstRW<[M1WriteFMAC4],  (instregex "^FN?MUL[DS]rr")>;
 468 def : InstRW<[M1WriteFMAC5],  (instregex "^FN?M(ADD|SUB)[DS]rrr")>;
 469 def : InstRW<[M1WriteFCVT3],  (instregex "^FRINT.+r")>;
 470 def : InstRW<[M1WriteNEONH],  (instregex "^FCSEL[DS]rrr")>;
 471 def : InstRW<[M1WriteFVAR15], (instrs FSQRTSr)>;
 472 def : InstRW<[M1WriteFVAR23], (instrs FSQRTDr)>;
 473
 474 // FP miscellaneous instructions.
 475 def : InstRW<[M1WriteFCVT3],  (instregex "^FCVT[DS][DS]r")>;
 476 def : InstRW<[M1WriteNEONF],  (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
 477 def : InstRW<[M1WriteNEONE],  (instregex "^[SU]CVTF[SU]")>;
 478 def : InstRW<[M1WriteNALU1],  (instregex "^FMOV[DS][ir]")>;
 479 def : InstRW<[M1WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev1")>;
 480 def : InstRW<[M1WriteNMISC1], (instregex "^FRECPXv1")>;
 481 def : InstRW<[M1WriteFMAC5],  (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
 482 def : InstRW<[M1WriteS4],     (instregex "^FMOV[WX][DS](High)?r")>;
 483 def : InstRW<[M1WriteNEONI],  (instregex "^FMOV[DS][WX](High)?r")>;
 484
 485 // FP load instructions.
 486 def : InstRW<[WriteVLD],    (instregex "^LDR[DSQ]l")>;
 487 def : InstRW<[WriteVLD],    (instregex "^LDUR[BDHSQ]i")>;
 488 def : InstRW<[WriteVLD,
 489               WriteAdr],    (instregex "^LDR[BDHSQ](post|pre)")>;
 490 def : InstRW<[WriteVLD],    (instregex "^LDR[BDHSQ]ui")>;
 491 def : InstRW<[M1WriteLD,
 492               ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
 493 def : InstRW<[WriteVLD,
 494               ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
 495 def : InstRW<[M1WriteLD,
 496               ReadAdrBase], (instregex "^LDRQro[WX]")>;
 497 def : InstRW<[WriteVLD,
 498               M1WriteLH],   (instregex "^LDN?P[DS]i")>;
 499 def : InstRW<[M1WriteLA,
 500               M1WriteLH],   (instregex "^LDN?PQi")>;
 501 def : InstRW<[M1WriteLC,
 502               M1WriteLH,
 503               WriteAdr],    (instregex "^LDP[DS](post|pre)")>;
 504 def : InstRW<[M1WriteLD,
 505               M1WriteLH,
 506               WriteAdr],    (instregex "^LDPQ(post|pre)")>;
 507
 508 // FP store instructions.
 509 def : InstRW<[WriteVST],    (instregex "^STUR[BDHSQ]i")>;
 510 def : InstRW<[WriteVST,
 511               WriteAdr],    (instregex "^STR[BDHSQ](post|pre)")>;
 512 def : InstRW<[WriteVST],    (instregex "^STR[BDHSQ]ui")>;
 513 def : InstRW<[M1WriteSA,
 514               ReadAdrBase], (instregex "^STR[BDHS]roW")>;
 515 def : InstRW<[WriteVST,
 516               ReadAdrBase], (instregex "^STR[BDHS]roX")>;
 517 def : InstRW<[M1WriteSA,
 518               ReadAdrBase], (instregex "^STRQro[WX]")>;
 519 def : InstRW<[WriteVST],    (instregex "^STN?P[DSQ]i")>;
 520 def : InstRW<[WriteVST,
 521               WriteAdr],    (instregex "^STP[DS](post|pre)")>;
 522 def : InstRW<[M1WriteSB,
 523               WriteAdr],    (instregex "^STPQ(post|pre)")>;
 524
 525 // ASIMD instructions.
 526 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]ABAL?v")>;
 527 def : InstRW<[M1WriteNMISC1], (instregex "^[SU]ABDL?v")>;
 528 def : InstRW<[M1WriteNMISC1], (instregex "^(SQ)?ABSv")>;
 529 def : InstRW<[M1WriteNMISC1], (instregex "^SQNEGv")>;
 530 def : InstRW<[M1WriteNALU1],  (instregex "^(ADD|NEG|SUB)v")>;
 531 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?H(ADD|SUB)v")>;
 532 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?AD[AD](L|LP|P|W)V?2?v")>;
 533 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]?SUB[LW]2?v")>;
 534 def : InstRW<[M1WriteNMISC3], (instregex "^R?(ADD|SUB)HN?2?v")>;
 535 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]+Q(ADD|SUB)v")>;
 536 def : InstRW<[M1WriteNMISC3], (instregex "^[SU]RHADDv")>;
 537 def : InstRW<[M1WriteNMISC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>;
 538 def : InstRW<[M1WriteNALU1],  (instregex "^CMTSTv")>;
 539 def : InstRW<[M1WriteNALU1],  (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>;
 540 def : InstRW<[M1WriteNMISC1], (instregex "^[SU](MIN|MAX)v")>;
 541 def : InstRW<[M1WriteNMISC2], (instregex "^[SU](MIN|MAX)Pv")>;
 542 def : InstRW<[M1WriteNMISC3], (instregex "^[SU](MIN|MAX)Vv")>;
 543 def : InstRW<[M1WriteNMISC4], (instregex "^(MUL|SQR?DMULH)v")>;
 544 def : InstRW<[M1WriteNMISC4], (instregex "^ML[AS]v")>;
 545 def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD|SQRD)ML[AS][HL]v")>;
 546 def : InstRW<[M1WriteNMISC4], (instregex "^(S|U|SQD)MULLv")>;
 547 def : InstRW<[M1WriteNAL13],  (instregex "^(S|SR|U|UR)SRAv")>;
 548 def : InstRW<[M1WriteNALU1],  (instregex "^SHL[dv]")>;
 549 def : InstRW<[M1WriteNALU1],  (instregex "^[SU]SH[LR][dv]")>;
 550 def : InstRW<[M1WriteNALU1],  (instregex "^S[RS]I[dv]")>;
 551 def : InstRW<[M1WriteNAL13],  (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>;
 552 def : InstRW<[M1WriteNAL13],  (instregex "^[SU]RSH[LR][dv]")>;
 553 def : InstRW<[M1WriteNAL13],  (instregex "^[SU]QR?SHLU?[bdhsv]")>;
 554
 555 // ASIMD FP instructions.
 556 def : InstRW<[M1WriteNALU1],  (instregex "^F(ABS|NEG)v")>;
 557 def : InstRW<[M1WriteNMISC3], (instregex "^F(ABD|ADD|SUB)v")>;
 558 def : InstRW<[M1WriteNEONA],  (instregex "^FADDP")>;
 559 def : InstRW<[M1WriteNMISC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>;
 560 def : InstRW<[M1WriteFCVT3],  (instregex "^[FVSU]CVTX?[AFLMNPZ][SU]?(_Int)?v")>;
 561 def : InstRW<[M1WriteFVAR15], (instregex "FDIVv.f32")>;
 562 def : InstRW<[M1WriteFVAR23], (instregex "FDIVv2f64")>;
 563 def : InstRW<[M1WriteFVAR15], (instregex "FSQRTv.f32")>;
 564 def : InstRW<[M1WriteFVAR23], (instregex "FSQRTv2f64")>;
 565 def : InstRW<[M1WriteNMISC1], (instregex "^F(MAX|MIN)(NM)?V?v")>;
 566 def : InstRW<[M1WriteNMISC2], (instregex "^F(MAX|MIN)(NM)?Pv")>;
 567 def : InstRW<[M1WriteNEONJ],  (instregex "^FMULX?v.i")>;
 568 def : InstRW<[M1WriteFMAC4],  (instregex "^FMULX?v.f")>;
 569 def : InstRW<[M1WriteNEONK],  (instregex "^FML[AS]v.i")>;
 570 def : InstRW<[M1WriteFMAC5],  (instregex "^FML[AS]v.f")>;
 571 def : InstRW<[M1WriteFCVT3],  (instregex "^FRINT[AIMNPXZ]v")>;
 572
 573 // ASIMD miscellaneous instructions.
 574 def : InstRW<[M1WriteNALU1],  (instregex "^RBITv")>;
 575 def : InstRW<[M1WriteNAL11],  (instregex "^(BIF|BIT|BSL)v")>;
 576 def : InstRW<[M1WriteNEONB],  (instregex "^DUPv.+gpr")>;
 577 def : InstRW<[M1WriteNALU1],  (instregex "^DUPv.+lane")>;
 578 def : InstRW<[M1WriteNALU1],  (instregex "^EXTv8")>;
 579 def : InstRW<[M1WriteNEONL],  (instregex "^EXTv16")>;
 580 def : InstRW<[M1WriteNAL13],  (instregex "^[SU]?Q?XTU?Nv")>;
 581 def : InstRW<[M1WriteNALU1],  (instregex "^CPY")>;
 582 def : InstRW<[M1WriteNALU1],  (instregex "^INSv.+lane")>;
 583 def : InstRW<[M1WriteNALU1],  (instregex "^MOVI[Dv]")>;
 584 def : InstRW<[M1WriteNALU1],  (instregex "^FMOVv")>;
 585 def : InstRW<[M1WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
 586 def : InstRW<[M1WriteFMAC5],  (instregex "^F(RECP|RSQRT)Sv")>;
 587 def : InstRW<[M1WriteNALU1],  (instregex "^REV(16|32|64)v")>;
 588 def : InstRW<[M1WriteNAL11],  (instregex "^TB[LX]v8i8One")>;
 589 def : InstRW<[WriteSequence<[M1WriteNAL11], 2>],
 590                               (instregex "^TB[LX]v8i8Two")>;
 591 def : InstRW<[WriteSequence<[M1WriteNAL11], 3>],
 592                               (instregex "^TB[LX]v8i8Three")>;
 593 def : InstRW<[WriteSequence<[M1WriteNAL11], 4>],
 594                               (instregex "^TB[LX]v8i8Four")>;
 595 def : InstRW<[M1WriteNAL12],  (instregex "^TB[LX]v16i8One")>;
 596 def : InstRW<[WriteSequence<[M1WriteNAL12], 2>],
 597                               (instregex "^TB[LX]v16i8Two")>;
 598 def : InstRW<[WriteSequence<[M1WriteNAL12], 3>],
 599                               (instregex "^TB[LX]v16i8Three")>;
 600 def : InstRW<[WriteSequence<[M1WriteNAL12], 4>],
 601                               (instregex "^TB[LX]v16i8Four")>;
 602 def : InstRW<[M1WriteNEOND],  (instregex "^[SU]MOVv")>;
 603 def : InstRW<[M1WriteNEONC],  (instregex "^INSv.+gpr")>;
 604 def : InstRW<[M1WriteNALU1],  (instregex "^(TRN|UZP)[12](v8i8|v4i16|v2i32)")>;
 605 def : InstRW<[M1WriteNALU2],  (instregex "^(TRN|UZP)[12](v16i8|v8i16|v4i32|v2i64)")>;
 606 def : InstRW<[M1WriteNALU1],  (instregex "^ZIP[12]v")>;
 607
 608 // ASIMD load instructions.
 609 def : InstRW<[M1WriteVLDD],   (instregex "LD1i(8|16|32)$")>;
 610 def : InstRW<[M1WriteVLDD,
 611               WriteAdr],      (instregex "LD1i(8|16|32)_POST$")>;
 612 def : InstRW<[M1WriteVLDE],   (instregex "LD1i(64)$")>;
 613 def : InstRW<[M1WriteVLDE,
 614               WriteAdr],      (instregex "LD1i(64)_POST$")>;
 615
 616 def : InstRW<[WriteVLD],      (instregex "LD1Rv(8b|4h|2s)$")>;
 617 def : InstRW<[WriteVLD,
 618               WriteAdr],      (instregex "LD1Rv(8b|4h|2s)_POST$")>;
 619 def : InstRW<[WriteVLD],      (instregex "LD1Rv(1d)$")>;
 620 def : InstRW<[WriteVLD,
 621               WriteAdr],      (instregex "LD1Rv(1d)_POST$")>;
 622 def : InstRW<[WriteVLD],      (instregex "LD1Rv(16b|8h|4s|2d)$")>;
 623 def : InstRW<[WriteVLD,
 624               WriteAdr],      (instregex "LD1Rv(16b|8h|4s|2d)_POST$")>;
 625
 626 def : InstRW<[WriteVLD],      (instregex "LD1Onev(8b|4h|2s|1d)$")>;
 627 def : InstRW<[WriteVLD,
 628               WriteAdr],      (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
 629 def : InstRW<[WriteVLD],      (instregex "LD1Onev(16b|8h|4s|2d)$")>;
 630 def : InstRW<[WriteVLD,
 631               WriteAdr],      (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
 632 def : InstRW<[M1WriteVLDA],   (instregex "LD1Twov(8b|4h|2s|1d)$")>;
 633 def : InstRW<[M1WriteVLDA,
 634               WriteAdr],      (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
 635 def : InstRW<[M1WriteVLDA],   (instregex "LD1Twov(16b|8h|4s|2d)$")>;
 636 def : InstRW<[M1WriteVLDA,
 637               WriteAdr],      (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
 638 def : InstRW<[M1WriteVLDB],   (instregex "LD1Threev(8b|4h|2s|1d)$")>;
 639 def : InstRW<[M1WriteVLDB,
 640               WriteAdr],      (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
 641 def : InstRW<[M1WriteVLDB],   (instregex "LD1Threev(16b|8h|4s|2d)$")>;
 642 def : InstRW<[M1WriteVLDB,
 643               WriteAdr],      (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
 644 def : InstRW<[M1WriteVLDC],   (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
 645 def : InstRW<[M1WriteVLDC,
 646               WriteAdr],      (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
 647 def : InstRW<[M1WriteVLDC],   (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
 648 def : InstRW<[M1WriteVLDC,
 649               WriteAdr],      (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
 650
 651 def : InstRW<[M1WriteVLDG],   (instregex "LD2i(8|16)$")>;
 652 def : InstRW<[M1WriteVLDG,
 653               WriteAdr],      (instregex "LD2i(8|16)_POST$")>;
 654 def : InstRW<[M1WriteVLDG],   (instregex "LD2i(32)$")>;
 655 def : InstRW<[M1WriteVLDG,
 656               WriteAdr],      (instregex "LD2i(32)_POST$")>;
 657 def : InstRW<[M1WriteVLDH],   (instregex "LD2i(64)$")>;
 658 def : InstRW<[M1WriteVLDH,
 659               WriteAdr],      (instregex "LD2i(64)_POST$")>;
 660
 661 def : InstRW<[M1WriteVLDA],   (instregex "LD2Rv(8b|4h|2s)$")>;
 662 def : InstRW<[M1WriteVLDA,
 663               WriteAdr],      (instregex "LD2Rv(8b|4h|2s)_POST$")>;
 664 def : InstRW<[M1WriteVLDA],   (instregex "LD2Rv(1d)$")>;
 665 def : InstRW<[M1WriteVLDA,
 666               WriteAdr],      (instregex "LD2Rv(1d)_POST$")>;
 667 def : InstRW<[M1WriteVLDA],   (instregex "LD2Rv(16b|8h|4s|2d)$")>;
 668 def : InstRW<[M1WriteVLDA,
 669               WriteAdr],      (instregex "LD2Rv(16b|8h|4s|2d)_POST$")>;
 670
 671 def : InstRW<[M1WriteVLDF],   (instregex "LD2Twov(8b|4h|2s)$")>;
 672 def : InstRW<[M1WriteVLDF,
 673               WriteAdr],      (instregex "LD2Twov(8b|4h|2s)_POST$")>;
 674 def : InstRW<[M1WriteVLDF],   (instregex "LD2Twov(16b|8h|4s)$")>;
 675 def : InstRW<[M1WriteVLDF,
 676               WriteAdr],      (instregex "LD2Twov(16b|8h|4s)_POST$")>;
 677 def : InstRW<[M1WriteVLDF],   (instregex "LD2Twov(2d)$")>;
 678 def : InstRW<[M1WriteVLDF,
 679               WriteAdr],      (instregex "LD2Twov(2d)_POST$")>;
 680
 681 def : InstRW<[M1WriteVLDJ],   (instregex "LD3i(8|16)$")>;
 682 def : InstRW<[M1WriteVLDJ,
 683               WriteAdr],      (instregex "LD3i(8|16)_POST$")>;
 684 def : InstRW<[M1WriteVLDJ],   (instregex "LD3i(32)$")>;
 685 def : InstRW<[M1WriteVLDJ,
 686               WriteAdr],      (instregex "LD3i(32)_POST$")>;
 687 def : InstRW<[M1WriteVLDL],   (instregex "LD3i(64)$")>;
 688 def : InstRW<[M1WriteVLDL,
 689               WriteAdr],      (instregex "LD3i(64)_POST$")>;
 690
 691 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(8b|4h|2s)$")>;
 692 def : InstRW<[M1WriteVLDB,
 693               WriteAdr],      (instregex "LD3Rv(8b|4h|2s)_POST$")>;
 694 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(1d)$")>;
 695 def : InstRW<[M1WriteVLDB,
 696               WriteAdr],      (instregex "LD3Rv(1d)_POST$")>;
 697 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(16b|8h|4s)$")>;
 698 def : InstRW<[M1WriteVLDB,
 699               WriteAdr],      (instregex "LD3Rv(16b|8h|4s)_POST$")>;
 700 def : InstRW<[M1WriteVLDB],   (instregex "LD3Rv(2d)$")>;
 701 def : InstRW<[M1WriteVLDB,
 702               WriteAdr],      (instregex "LD3Rv(2d)_POST$")>;
 703
 704 def : InstRW<[M1WriteVLDI],   (instregex "LD3Threev(8b|4h|2s)$")>;
 705 def : InstRW<[M1WriteVLDI,
 706               WriteAdr],      (instregex "LD3Threev(8b|4h|2s)_POST$")>;
 707 def : InstRW<[M1WriteVLDI],   (instregex "LD3Threev(16b|8h|4s)$")>;
 708 def : InstRW<[M1WriteVLDI,
 709               WriteAdr],      (instregex "LD3Threev(16b|8h|4s)_POST$")>;
 710 def : InstRW<[M1WriteVLDI],   (instregex "LD3Threev(2d)$")>;
 711 def : InstRW<[M1WriteVLDI,
 712               WriteAdr],      (instregex "LD3Threev(2d)_POST$")>;
 713
 714 def : InstRW<[M1WriteVLDK],   (instregex "LD4i(8|16)$")>;
 715 def : InstRW<[M1WriteVLDK,
 716               WriteAdr],      (instregex "LD4i(8|16)_POST$")>;
 717 def : InstRW<[M1WriteVLDK],   (instregex "LD4i(32)$")>;
 718 def : InstRW<[M1WriteVLDK,
 719               WriteAdr],      (instregex "LD4i(32)_POST$")>;
 720 def : InstRW<[M1WriteVLDM],   (instregex "LD4i(64)$")>;
 721 def : InstRW<[M1WriteVLDM,
 722               WriteAdr],      (instregex "LD4i(64)_POST$")>;
 723
 724 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(8b|4h|2s)$")>;
 725 def : InstRW<[M1WriteVLDC,
 726               WriteAdr],      (instregex "LD4Rv(8b|4h|2s)_POST$")>;
 727 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(1d)$")>;
 728 def : InstRW<[M1WriteVLDC,
 729               WriteAdr],      (instregex "LD4Rv(1d)_POST$")>;
 730 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(16b|8h|4s)$")>;
 731 def : InstRW<[M1WriteVLDC,
 732               WriteAdr],      (instregex "LD4Rv(16b|8h|4s)_POST$")>;
 733 def : InstRW<[M1WriteVLDC],   (instregex "LD4Rv(2d)$")>;
 734 def : InstRW<[M1WriteVLDC,
 735               WriteAdr],      (instregex "LD4Rv(2d)_POST$")>;
 736
 737 def : InstRW<[M1WriteVLDN],   (instregex "LD4Fourv(8b|4h|2s)$")>;
 738 def : InstRW<[M1WriteVLDN,
 739               WriteAdr],      (instregex "LD4Fourv(8b|4h|2s)_POST$")>;
 740 def : InstRW<[M1WriteVLDN],   (instregex "LD4Fourv(16b|8h|4s)$")>;
 741 def : InstRW<[M1WriteVLDN,
 742               WriteAdr],      (instregex "LD4Fourv(16b|8h|4s)_POST$")>;
 743 def : InstRW<[M1WriteVLDN],   (instregex "LD4Fourv(2d)$")>;
 744 def : InstRW<[M1WriteVLDN,
 745               WriteAdr],      (instregex "LD4Fourv(2d)_POST$")>;
 746
 747 // ASIMD store instructions.
 748 def : InstRW<[M1WriteVSTD],   (instregex "ST1i(8|16|32)$")>;
 749 def : InstRW<[M1WriteVSTD,
 750               WriteAdr],      (instregex "ST1i(8|16|32)_POST$")>;
 751 def : InstRW<[M1WriteVSTD],   (instregex "ST1i(64)$")>;
 752 def : InstRW<[M1WriteVSTD,
 753               WriteAdr],      (instregex "ST1i(64)_POST$")>;
 754
 755 def : InstRW<[WriteVST],      (instregex "ST1Onev(8b|4h|2s|1d)$")>;
 756 def : InstRW<[WriteVST,
 757               WriteAdr],      (instregex "ST1Onev(8b|4h|2s|1d)_POST$")>;
 758 def : InstRW<[WriteVST],      (instregex "ST1Onev(16b|8h|4s|2d)$")>;
 759 def : InstRW<[WriteVST,
 760               WriteAdr],      (instregex "ST1Onev(16b|8h|4s|2d)_POST$")>;
 761 def : InstRW<[M1WriteVSTA],   (instregex "ST1Twov(8b|4h|2s|1d)$")>;
 762 def : InstRW<[M1WriteVSTA,
 763               WriteAdr],      (instregex "ST1Twov(8b|4h|2s|1d)_POST$")>;
 764 def : InstRW<[M1WriteVSTA],   (instregex "ST1Twov(16b|8h|4s|2d)$")>;
 765 def : InstRW<[M1WriteVSTA,
 766               WriteAdr],      (instregex "ST1Twov(16b|8h|4s|2d)_POST$")>;
 767 def : InstRW<[M1WriteVSTB],   (instregex "ST1Threev(8b|4h|2s|1d)$")>;
 768 def : InstRW<[M1WriteVSTB,
 769               WriteAdr],      (instregex "ST1Threev(8b|4h|2s|1d)_POST$")>;
 770 def : InstRW<[M1WriteVSTB],   (instregex "ST1Threev(16b|8h|4s|2d)$")>;
 771 def : InstRW<[M1WriteVSTB,
 772               WriteAdr],      (instregex "ST1Threev(16b|8h|4s|2d)_POST$")>;
 773 def : InstRW<[M1WriteVSTC],   (instregex "ST1Fourv(8b|4h|2s|1d)$")>;
 774 def : InstRW<[M1WriteVSTC,
 775               WriteAdr],      (instregex "ST1Fourv(8b|4h|2s|1d)_POST$")>;
 776 def : InstRW<[M1WriteVSTC],   (instregex "ST1Fourv(16b|8h|4s|2d)$")>;
 777 def : InstRW<[M1WriteVSTC,
 778               WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST$")>;
 779
 780 def : InstRW<[M1WriteVSTD],   (instregex "ST2i(8|16|32)$")>;
 781 def : InstRW<[M1WriteVSTD,
 782               WriteAdr],      (instregex "ST2i(8|16|32)_POST$")>;
 783 def : InstRW<[M1WriteVSTD],   (instregex "ST2i(64)$")>;
 784 def : InstRW<[M1WriteVSTD,
 785               WriteAdr],      (instregex "ST2i(64)_POST$")>;
 786
 787 def : InstRW<[M1WriteVSTD],   (instregex "ST2Twov(8b|4h|2s)$")>;
 788 def : InstRW<[M1WriteVSTD,
 789               WriteAdr],      (instregex "ST2Twov(8b|4h|2s)_POST$")>;
 790 def : InstRW<[M1WriteVSTE],   (instregex "ST2Twov(16b|8h|4s)$")>;
 791 def : InstRW<[M1WriteVSTE,
 792               WriteAdr],      (instregex "ST2Twov(16b|8h|4s)_POST$")>;
 793 def : InstRW<[M1WriteVSTE],   (instregex "ST2Twov(2d)$")>;
 794 def : InstRW<[M1WriteVSTE,
 795               WriteAdr],      (instregex "ST2Twov(2d)_POST$")>;
 796
 797 def : InstRW<[M1WriteVSTH],   (instregex "ST3i(8|16)$")>;
 798 def : InstRW<[M1WriteVSTH,
 799               WriteAdr],      (instregex "ST3i(8|16)_POST$")>;
 800 def : InstRW<[M1WriteVSTH],   (instregex "ST3i(32)$")>;
 801 def : InstRW<[M1WriteVSTH,
 802               WriteAdr],      (instregex "ST3i(32)_POST$")>;
 803 def : InstRW<[M1WriteVSTF],   (instregex "ST3i(64)$")>;
 804 def : InstRW<[M1WriteVSTF,
 805               WriteAdr],      (instregex "ST3i(64)_POST$")>;
 806
 807 def : InstRW<[M1WriteVSTF],   (instregex "ST3Threev(8b|4h|2s)$")>;
 808 def : InstRW<[M1WriteVSTF,
 809               WriteAdr],      (instregex "ST3Threev(8b|4h|2s)_POST$")>;
 810 def : InstRW<[M1WriteVSTG],   (instregex "ST3Threev(16b|8h|4s)$")>;
 811 def : InstRW<[M1WriteVSTG,
 812               WriteAdr],      (instregex "ST3Threev(16b|8h|4s)_POST$")>;
 813 def : InstRW<[M1WriteVSTG],   (instregex "ST3Threev(2d)$")>;
 814 def : InstRW<[M1WriteVSTG,
 815               WriteAdr],      (instregex "ST3Threev(2d)_POST$")>;
 816
 817 def : InstRW<[M1WriteVSTH],   (instregex "ST4i(8|16)$")>;
 818 def : InstRW<[M1WriteVSTH,
 819               WriteAdr],      (instregex "ST4i(8|16)_POST$")>;
 820 def : InstRW<[M1WriteVSTH],   (instregex "ST4i(32)$")>;
 821 def : InstRW<[M1WriteVSTH,
 822               WriteAdr],      (instregex "ST4i(32)_POST$")>;
 823 def : InstRW<[M1WriteVSTF],   (instregex "ST4i(64)$")>;
 824 def : InstRW<[M1WriteVSTF,
 825               WriteAdr],      (instregex "ST4i(64)_POST$")>;
 826
 827 def : InstRW<[M1WriteVSTF],   (instregex "ST4Fourv(8b|4h|2s)$")>;
 828 def : InstRW<[M1WriteVSTF,
 829               WriteAdr],      (instregex "ST4Fourv(8b|4h|2s)_POST$")>;
 830 def : InstRW<[M1WriteVSTI],   (instregex "ST4Fourv(16b|8h|4s)$")>;
 831 def : InstRW<[M1WriteVSTI,
 832               WriteAdr],      (instregex "ST4Fourv(16b|8h|4s)_POST$")>;
 833 def : InstRW<[M1WriteVSTI],   (instregex "ST4Fourv(2d)$")>;
 834 def : InstRW<[M1WriteVSTI,
 835               WriteAdr],      (instregex "ST4Fourv(2d)_POST$")>;
 836
 837 // Cryptography instructions.
 838 def : InstRW<[M1WriteAES], (instregex "^AES[DE]")>;
 839 def : InstRW<[M1WriteAES, M1ReadAES], (instregex "^AESI?MC")>;
 840
 841 def : InstRW<[M1WriteNCRYPT1], (instregex "^PMUL")>;
 842 def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA1(H|SU)")>;
 843 def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA1[CMP]")>;
 844 def : InstRW<[M1WriteNCRYPT1], (instregex "^SHA256SU0")>;
 845 def : InstRW<[M1WriteNCRYPT5], (instregex "^SHA256(H|SU1)")>;
 846
 847 // CRC instructions.
 848 def : InstRW<[M1WriteC2], (instregex "^CRC32")>;
 849
 850 } // SchedModel = ExynosM1Model