lib/Target/ARM/Thumb2InstrInfo.h

   1 //===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
  14 #define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
  15
  16 #include "ARMBaseInstrInfo.h"
  17 #include "ThumbRegisterInfo.h"
  18
  19 namespace llvm {
  20 class ARMSubtarget;
  21 class ScheduleHazardRecognizer;
  22
  23 class Thumb2InstrInfo : public ARMBaseInstrInfo {
  24   ThumbRegisterInfo RI;
  25 public:
  26   explicit Thumb2InstrInfo(const ARMSubtarget &STI);
  27
  28   /// Return the noop instruction to use for a noop.
  29   void getNoop(MCInst &NopInst) const override;
  30
  31   // Return the non-pre/post incrementing version of 'Opc'. Return 0
  32   // if there is not such an opcode.
  33   unsigned getUnindexedOpcode(unsigned Opc) const override;
  34
  35   void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
  36                                MachineBasicBlock *NewDest) const override;
  37
  38   bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
  39                            MachineBasicBlock::iterator MBBI) const override;
  40
  41   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
  42                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
  43                    bool KillSrc) const override;
  44
  45   void storeRegToStackSlot(MachineBasicBlock &MBB,
  46                            MachineBasicBlock::iterator MBBI,
  47                            unsigned SrcReg, bool isKill, int FrameIndex,
  48                            const TargetRegisterClass *RC,
  49                            const TargetRegisterInfo *TRI) const override;
  50
  51   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  52                             MachineBasicBlock::iterator MBBI,
  53                             unsigned DestReg, int FrameIndex,
  54                             const TargetRegisterClass *RC,
  55                             const TargetRegisterInfo *TRI) const override;
  56
  57   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  58   /// such, whenever a client has an instance of instruction info, it should
  59   /// always be able to get register info as well (through this method).
  60   ///
  61   const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
  62
  63 private:
  64   void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
  65 };
  66
  67 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
  68 /// to llvm::getInstrPredicate except it returns AL for conditional branch
  69 /// instructions which are "predicated", but are not in IT blocks.
  70 ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
  71
  72 // getVPTInstrPredicate: VPT analogue of that, plus a helper function
  73 // corresponding to MachineInstr::findFirstPredOperandIdx.
  74 int findFirstVPTPredOperandIdx(const MachineInstr &MI);
  75 ARMVCC::VPTCodes getVPTInstrPredicate(const MachineInstr &MI,
  76                                       unsigned &PredReg);
  77 }
  78
  79 #endif