| blob | 8cc0029fc896feac76d191546393122def20dc9d |
1 //===--- MicroMipsInstrFormats.td - microMIPS Inst Defs -*- tablegen -*----===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This files describes the defintions of the microMIPSr3 instructions.
10 //
11 //===----------------------------------------------------------------------===//
13 def addrimm11 : ComplexPattern<iPTR, 2, "selectIntAddr11MM", [frameindex]>;
14 def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddr12MM", [frameindex]>;
15 def addrimm16 : ComplexPattern<iPTR, 2, "selectIntAddr16MM", [frameindex]>;
16 def addrimm4lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrLSL2MM", [frameindex]>;
18 def simm9_addiusp : Operand<i32> {
19 let EncoderMethod = "getSImm9AddiuspValue";
20 let DecoderMethod = "DecodeSimm9SP";
21 }
23 def uimm3_shift : Operand<i32> {
24 let EncoderMethod = "getUImm3Mod8Encoding";
25 let DecoderMethod = "DecodePOOL16BEncodedField";
26 }
28 def simm3_lsa2 : Operand<i32> {
29 let EncoderMethod = "getSImm3Lsa2Value";
30 let DecoderMethod = "DecodeAddiur2Simm7";
31 }
33 def uimm4_andi : Operand<i32> {
34 let EncoderMethod = "getUImm4AndValue";
35 let DecoderMethod = "DecodeANDI16Imm";
36 }
38 def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 ||
39 ((Imm % 4 == 0) &&
40 Imm < 28 && Imm > 0);}]>;
42 def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
44 def immZExtAndi16 : ImmLeaf<i32,
45 [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
46 Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
47 Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>;
49 def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>;
51 def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>;
53 def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass {
54 let Name = "MicroMipsMem";
55 let RenderMethod = "addMicroMipsMemOperands";
56 let ParserMethod = "parseMemOperand";
57 let PredicateMethod = "isMemWithGRPMM16Base";
58 }
60 // Define the classes of pointers used by microMIPS.
61 // The numbers must match those in MipsRegisterInfo::MipsPtrClass.
62 def ptr_gpr16mm_rc : PointerLikeRegClass<1>;
63 def ptr_sp_rc : PointerLikeRegClass<2>;
64 def ptr_gp_rc : PointerLikeRegClass<3>;
66 class mem_mm_4_generic : Operand<i32> {
67 let PrintMethod = "printMemOperand";
68 let MIOperandInfo = (ops ptr_gpr16mm_rc, simm4);
69 let OperandType = "OPERAND_MEMORY";
70 let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand;
71 }
73 def mem_mm_4 : mem_mm_4_generic {
74 let EncoderMethod = "getMemEncodingMMImm4";
75 }
77 def mem_mm_4_lsl1 : mem_mm_4_generic {
78 let EncoderMethod = "getMemEncodingMMImm4Lsl1";
79 }
81 def mem_mm_4_lsl2 : mem_mm_4_generic {
82 let EncoderMethod = "getMemEncodingMMImm4Lsl2";
83 }
85 def MicroMipsMemSPAsmOperand : AsmOperandClass {
86 let Name = "MicroMipsMemSP";
87 let RenderMethod = "addMemOperands";
88 let ParserMethod = "parseMemOperand";
89 let PredicateMethod = "isMemWithUimmWordAlignedOffsetSP<7>";
90 }
92 def MicroMipsMemGPAsmOperand : AsmOperandClass {
93 let Name = "MicroMipsMemGP";
94 let RenderMethod = "addMemOperands";
95 let ParserMethod = "parseMemOperand";
96 let PredicateMethod = "isMemWithSimmWordAlignedOffsetGP<9>";
97 }
99 def mem_mm_sp_imm5_lsl2 : Operand<i32> {
100 let PrintMethod = "printMemOperand";
101 let MIOperandInfo = (ops ptr_sp_rc:$base, simm5:$offset);
102 let OperandType = "OPERAND_MEMORY";
103 let ParserMatchClass = MicroMipsMemSPAsmOperand;
104 let EncoderMethod = "getMemEncodingMMSPImm5Lsl2";
105 }
107 def mem_mm_gp_simm7_lsl2 : Operand<i32> {
108 let PrintMethod = "printMemOperand";
109 let MIOperandInfo = (ops ptr_gp_rc:$base, simm7_lsl2:$offset);
110 let OperandType = "OPERAND_MEMORY";
111 let ParserMatchClass = MicroMipsMemGPAsmOperand;
112 let EncoderMethod = "getMemEncodingMMGPImm7Lsl2";
113 }
115 def mem_mm_9 : Operand<i32> {
116 let PrintMethod = "printMemOperand";
117 let MIOperandInfo = (ops ptr_rc, simm9);
118 let EncoderMethod = "getMemEncodingMMImm9";
119 let ParserMatchClass = MipsMemSimm9AsmOperand;
120 let OperandType = "OPERAND_MEMORY";
121 }
123 def mem_mm_11 : Operand<i32> {
124 let PrintMethod = "printMemOperand";
125 let MIOperandInfo = (ops GPR32, simm11);
126 let EncoderMethod = "getMemEncodingMMImm11";
127 let ParserMatchClass = MipsMemSimm11AsmOperand;
128 let OperandType = "OPERAND_MEMORY";
129 }
131 def mem_mm_12 : Operand<i32> {
132 let PrintMethod = "printMemOperand";
133 let MIOperandInfo = (ops ptr_rc, simm12);
134 let EncoderMethod = "getMemEncodingMMImm12";
135 let ParserMatchClass = MipsMemAsmOperand;
136 let OperandType = "OPERAND_MEMORY";
137 }
139 def mem_mm_16 : Operand<i32> {
140 let PrintMethod = "printMemOperand";
141 let MIOperandInfo = (ops ptr_rc, simm16);
142 let EncoderMethod = "getMemEncodingMMImm16";
143 let DecoderMethod = "DecodeMemMMImm16";
144 let ParserMatchClass = MipsMemSimm16AsmOperand;
145 let OperandType = "OPERAND_MEMORY";
146 }
148 def MipsMemUimm4AsmOperand : AsmOperandClass {
149 let Name = "MemOffsetUimm4";
150 let SuperClasses = [MipsMemAsmOperand];
151 let RenderMethod = "addMemOperands";
152 let ParserMethod = "parseMemOperand";
153 let PredicateMethod = "isMemWithUimmOffsetSP<6>";
154 }
156 def mem_mm_4sp : Operand<i32> {
157 let PrintMethod = "printMemOperand";
158 let MIOperandInfo = (ops ptr_sp_rc, uimm8);
159 let EncoderMethod = "getMemEncodingMMImm4sp";
160 let ParserMatchClass = MipsMemUimm4AsmOperand;
161 let OperandType = "OPERAND_MEMORY";
162 }
164 def jmptarget_mm : Operand<OtherVT> {
165 let EncoderMethod = "getJumpTargetOpValueMM";
166 }
168 def calltarget_mm : Operand<iPTR> {
169 let EncoderMethod = "getJumpTargetOpValueMM";
170 }
172 def brtarget7_mm : Operand<OtherVT> {
173 let EncoderMethod = "getBranchTarget7OpValueMM";
174 let OperandType = "OPERAND_PCREL";
175 let DecoderMethod = "DecodeBranchTarget7MM";
176 let ParserMatchClass = MipsJumpTargetAsmOperand;
177 }
179 def brtarget10_mm : Operand<OtherVT> {
180 let EncoderMethod = "getBranchTargetOpValueMMPC10";
181 let OperandType = "OPERAND_PCREL";
182 let DecoderMethod = "DecodeBranchTarget10MM";
183 let ParserMatchClass = MipsJumpTargetAsmOperand;
184 }
186 def brtarget_mm : Operand<OtherVT> {
187 let EncoderMethod = "getBranchTargetOpValueMM";
188 let OperandType = "OPERAND_PCREL";
189 let DecoderMethod = "DecodeBranchTargetMM";
190 let ParserMatchClass = MipsJumpTargetAsmOperand;
191 }
193 def simm23_lsl2 : Operand<i32> {
194 let EncoderMethod = "getSimm23Lsl2Encoding";
195 let DecoderMethod = "DecodeSimm23Lsl2";
196 }
198 class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op,
199 RegisterOperand RO> :
200 InstSE<(outs), (ins RO:$rs, opnd:$offset),
201 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZC, FrmI> {
202 let isBranch = 1;
203 let isTerminator = 1;
204 let hasDelaySlot = 0;
205 let Defs = [AT];
206 }
208 let canFoldAsLoad = 1 in
209 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
210 Operand MemOpnd, InstrItinClass Itin> :
211 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
212 !strconcat(opstr, "\t$rt, $addr"),
213 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
214 Itin, FrmI> {
215 let DecoderMethod = "DecodeMemMMImm12";
216 string Constraints = "$src = $rt";
217 let BaseOpcode = opstr;
218 bit mayLoad = 1;
219 bit mayStore = 0;
220 }
222 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
223 Operand MemOpnd, InstrItinClass Itin>:
224 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr),
225 !strconcat(opstr, "\t$rt, $addr"),
226 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
227 let DecoderMethod = "DecodeMemMMImm12";
228 let BaseOpcode = opstr;
229 bit mayLoad = 0;
230 bit mayStore = 1;
231 }
233 class MovePMM16<string opstr, RegisterOperand RO1, RegisterOperand RO2,
234 RegisterOperand RO3> :
235 MicroMipsInst16<(outs RO1:$rd1, RO2:$rd2), (ins RO3:$rs, RO3:$rt),
236 !strconcat(opstr, "\t$rd1, $rd2, $rs, $rt"), [],
237 NoItinerary, FrmR> {
238 let isReMaterializable = 1;
239 let isMoveReg = 1;
240 let DecoderMethod = "DecodeMovePOperands";
241 }
243 class StorePairMM<string opstr, ComplexPattern Addr = addr>
244 : InstSE<(outs), (ins GPR32Opnd:$rt, GPR32Opnd:$rt2, mem_simm12:$addr),
245 !strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> {
246 let DecoderMethod = "DecodeMemMMImm12";
247 let mayStore = 1;
248 let AsmMatchConverter = "ConvertXWPOperands";
249 }
251 class LoadPairMM<string opstr, ComplexPattern Addr = addr>
252 : InstSE<(outs GPR32Opnd:$rt, GPR32Opnd:$rt2), (ins mem_simm12:$addr),
253 !strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> {
254 let DecoderMethod = "DecodeMemMMImm12";
255 let mayLoad = 1;
256 let AsmMatchConverter = "ConvertXWPOperands";
257 }
259 class LLBaseMM<string opstr, RegisterOperand RO> :
260 InstSE<(outs RO:$rt), (ins mem_mm_12:$addr),
261 !strconcat(opstr, "\t$rt, $addr"), [], II_LL, FrmI> {
262 let DecoderMethod = "DecodeMemMMImm12";
263 let mayLoad = 1;
264 }
266 class LLEBaseMM<string opstr, RegisterOperand RO> :
267 InstSE<(outs RO:$rt), (ins mem_simm9:$addr),
268 !strconcat(opstr, "\t$rt, $addr"), [], II_LLE, FrmI> {
269 let DecoderMethod = "DecodeMemMMImm9";
270 string BaseOpcode = opstr;
271 let mayLoad = 1;
272 }
274 class SCBaseMM<string opstr, RegisterOperand RO> :
275 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
276 !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> {
277 let DecoderMethod = "DecodeMemMMImm12";
278 let mayStore = 1;
279 let Constraints = "$rt = $dst";
280 }
282 class SCEBaseMM<string opstr, RegisterOperand RO> :
283 InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
284 !strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> {
285 let DecoderMethod = "DecodeMemMMImm9";
286 string BaseOpcode = opstr;
287 let mayStore = 1;
288 let Constraints = "$rt = $dst";
289 }
291 class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
292 InstrItinClass Itin = NoItinerary, DAGOperand MO = mem_mm_12> :
293 InstSE<(outs RO:$rt), (ins MO:$addr),
294 !strconcat(opstr, "\t$rt, $addr"),
295 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
296 let DecoderMethod = "DecodeMemMMImm12";
297 let canFoldAsLoad = 1;
298 let mayLoad = 1;
299 }
301 class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0,
302 InstrItinClass Itin = NoItinerary,
303 SDPatternOperator OpNode = null_frag> :
304 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
305 !strconcat(opstr, "\t$rd, $rs, $rt"),
306 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
307 let isCommutable = isComm;
308 }
310 class AndImmMM16<string opstr, RegisterOperand RO,
311 InstrItinClass Itin = NoItinerary> :
312 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm),
313 !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>;
315 class LogicRMM16<string opstr, RegisterOperand RO,
316 InstrItinClass Itin = NoItinerary,
317 SDPatternOperator OpNode = null_frag> :
318 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
319 !strconcat(opstr, "\t$rt, $rs"),
320 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
321 let isCommutable = 1;
322 let Constraints = "$rt = $dst";
323 }
325 class NotMM16<string opstr, RegisterOperand RO> :
326 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
327 !strconcat(opstr, "\t$rt, $rs"),
328 [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
330 class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO,
331 InstrItinClass Itin = NoItinerary> :
332 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
333 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
335 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
336 InstrItinClass Itin, Operand MemOpnd> :
337 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr),
338 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
339 let DecoderMethod = "DecodeMemMMImm4";
340 let canFoldAsLoad = 1;
341 let mayLoad = 1;
342 }
344 class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO,
345 SDPatternOperator OpNode, InstrItinClass Itin,
346 Operand MemOpnd> :
347 MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
348 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
349 let DecoderMethod = "DecodeMemMMImm4";
350 let mayStore = 1;
351 }
353 class LoadSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
354 Operand MemOpnd> :
355 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
356 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
357 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
358 let canFoldAsLoad = 1;
359 let mayLoad = 1;
360 }
362 class StoreSPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
363 Operand MemOpnd> :
364 MicroMipsInst16<(outs), (ins RO:$rt, MemOpnd:$offset),
365 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
366 let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
367 let mayStore = 1;
368 }
370 class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin,
371 Operand MemOpnd> :
372 MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$offset),
373 !strconcat(opstr, "\t$rt, $offset"), [], Itin, FrmI> {
374 let DecoderMethod = "DecodeMemMMGPImm7Lsl2";
375 let canFoldAsLoad = 1;
376 let mayLoad = 1;
377 }
379 class AddImmUR2<string opstr, RegisterOperand RO> :
380 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm),
381 !strconcat(opstr, "\t$rd, $rs, $imm"),
382 [], II_ADDIU, FrmR> {
383 let isCommutable = 1;
384 }
386 class AddImmUS5<string opstr, RegisterOperand RO> :
387 MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
388 !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR> {
389 let Constraints = "$rd = $dst";
390 }
392 class AddImmUR1SP<string opstr, RegisterOperand RO> :
393 MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm),
394 !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR>;
396 class AddImmUSP<string opstr> :
397 MicroMipsInst16<(outs), (ins simm9_addiusp:$imm),
398 !strconcat(opstr, "\t$imm"), [], II_ADDIU, FrmI>;
400 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
401 MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"),
402 [], II_MFHI_MFLO, FrmR> {
403 let Uses = [UseReg];
404 let hasSideEffects = 0;
405 let isMoveReg = 1;
406 }
408 class MoveMM16<string opstr, RegisterOperand RO>
409 : MicroMipsInst16<(outs RO:$rd), (ins RO:$rs),
410 !strconcat(opstr, "\t$rd, $rs"), [], II_MOVE, FrmR> {
411 let isReMaterializable = 1;
412 let isMoveReg = 1;
413 }
415 class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> :
416 MicroMipsInst16<(outs RO:$rd), (ins Od:$imm),
417 !strconcat(opstr, "\t$rd, $imm"), [], II_LI, FrmI> {
418 let isReMaterializable = 1;
419 }
421 // 16-bit Jump and Link (Call)
422 class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
423 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
424 [(MipsJmpLink RO:$rs)], II_JALR, FrmR> {
425 let isCall = 1;
426 let hasDelaySlot = 1;
427 let Defs = [RA];
428 let hasPostISelHook = 1;
429 }
431 // 16-bit Jump Reg
432 class JumpRegMM16<string opstr, RegisterOperand RO> :
433 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
434 [], II_JR, FrmR> {
435 let hasDelaySlot = 1;
436 let isBranch = 1;
437 let isIndirectBranch = 1;
438 }
440 // Base class for JRADDIUSP instruction.
441 class JumpRAddiuStackMM16 :
442 MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm",
443 [], II_JRADDIUSP, FrmR> {
444 let isTerminator = 1;
445 let isBarrier = 1;
446 let isBranch = 1;
447 let isIndirectBranch = 1;
448 }
450 // 16-bit Jump and Link (Call) - Short Delay Slot
451 class JumpLinkRegSMM16<string opstr, RegisterOperand RO> :
452 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
453 [], II_JALRS, FrmR> {
454 let isCall = 1;
455 let hasDelaySlot = 1;
456 let Defs = [RA];
457 }
459 // 16-bit Jump Register Compact - No delay slot
460 class JumpRegCMM16<string opstr, RegisterOperand RO> :
461 MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
462 [], II_JRC, FrmR> {
463 let isTerminator = 1;
464 let isBarrier = 1;
465 let isBranch = 1;
466 let isIndirectBranch = 1;
467 }
469 // Break16 and Sdbbp16
470 class BrkSdbbp16MM<string opstr, InstrItinClass Itin> :
471 MicroMipsInst16<(outs), (ins uimm4:$code_),
472 !strconcat(opstr, "\t$code_"),
473 [], Itin, FrmOther>;
475 class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> :
476 MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset),
477 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZ, FrmI> {
478 let isBranch = 1;
479 let isTerminator = 1;
480 let hasDelaySlot = 1;
481 let Defs = [AT];
482 }
484 // MicroMIPS Jump and Link (Call) - Short Delay Slot
485 let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
486 class JumpLinkMM<string opstr, DAGOperand opnd> :
487 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
488 [], II_JALS, FrmJ, opstr> {
489 let DecoderMethod = "DecodeJumpTargetMM";
490 }
492 class JumpLinkRegMM<string opstr, RegisterOperand RO>:
493 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
494 [], II_JALRS, FrmR>;
496 class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd,
497 RegisterOperand RO> :
498 InstSE<(outs), (ins RO:$rs, opnd:$offset),
499 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZALS, FrmI, opstr>;
500 }
502 class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO,
503 SDPatternOperator OpNode = null_frag> :
504 InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index),
505 !strconcat(opstr, "\t$rd, ${index}(${base})"), [], II_LWXS, FrmFI>;
507 class PrefetchIndexed<string opstr> :
508 InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint),
509 !strconcat(opstr, "\t$hint, ${index}(${base})"), [], II_PREF, FrmOther>;
511 class AddImmUPC<string opstr, RegisterOperand RO> :
512 InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm),
513 !strconcat(opstr, "\t$rs, $imm"), [], II_ADDIU, FrmR>;
515 /// A list of registers used by load/store multiple instructions.
516 def RegListAsmOperand : AsmOperandClass {
517 let Name = "RegList";
518 let ParserMethod = "parseRegisterList";
519 }
521 def reglist : Operand<i32> {
522 let EncoderMethod = "getRegisterListOpValue";
523 let ParserMatchClass = RegListAsmOperand;
524 let PrintMethod = "printRegisterList";
525 let DecoderMethod = "DecodeRegListOperand";
526 }
528 def RegList16AsmOperand : AsmOperandClass {
529 let Name = "RegList16";
530 let ParserMethod = "parseRegisterList";
531 let PredicateMethod = "isRegList16";
532 let RenderMethod = "addRegListOperands";
533 }
535 def reglist16 : Operand<i32> {
536 let EncoderMethod = "getRegisterListOpValue16";
537 let DecoderMethod = "DecodeRegListOperand16";
538 let PrintMethod = "printRegisterList";
539 let ParserMatchClass = RegList16AsmOperand;
540 }
542 class StoreMultMM<string opstr,
543 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
544 InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr),
545 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
546 let DecoderMethod = "DecodeMemMMImm12";
547 let mayStore = 1;
548 }
550 class LoadMultMM<string opstr,
551 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
552 InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr),
553 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> {
554 let DecoderMethod = "DecodeMemMMImm12";
555 let mayLoad = 1;
556 }
558 class StoreMultMM16<string opstr,
559 InstrItinClass Itin = NoItinerary,
560 ComplexPattern Addr = addr> :
561 MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
562 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
563 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
564 let mayStore = 1;
565 }
567 class LoadMultMM16<string opstr,
568 InstrItinClass Itin = NoItinerary,
569 ComplexPattern Addr = addr> :
570 MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
571 !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> {
572 let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
573 let mayLoad = 1;
574 }
576 class UncondBranchMM16<string opstr> :
577 MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
578 !strconcat(opstr, "\t$offset"),
579 [], II_B, FrmI> {
580 let isBranch = 1;
581 let isTerminator = 1;
582 let isBarrier = 1;
583 let hasDelaySlot = 1;
584 let Predicates = [RelocPIC, InMicroMips];
585 let Defs = [AT];
586 }
588 class HypcallMM<string opstr> :
589 InstSE<(outs), (ins uimm10:$code_),
590 !strconcat(opstr, "\t$code_"), [], II_HYPCALL, FrmOther> {
591 let BaseOpcode = opstr;
592 }
594 class TLBINVMM<string opstr, InstrItinClass Itin> :
595 InstSE<(outs), (ins), opstr, [], Itin, FrmOther> {
596 let BaseOpcode = opstr;
597 }
599 class MfCop0MM<string opstr, RegisterOperand DstRC,
600 RegisterOperand SrcRC, InstrItinClass Itin> :
601 InstSE<(outs DstRC:$rt), (ins SrcRC:$rs, uimm3:$sel),
602 !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {
603 let BaseOpcode = opstr;
604 }
606 class MtCop0MM<string opstr, RegisterOperand DstRC,
607 RegisterOperand SrcRC, InstrItinClass Itin> :
608 InstSE<(outs DstRC:$rs), (ins SrcRC:$rt, uimm3:$sel),
609 !strconcat(opstr, "\t$rt, $rs, $sel"), [], Itin, FrmR> {
610 let BaseOpcode = opstr;
611 }
613 let FastISelShouldIgnore = 1 in {
614 def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
615 ARITH_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;
616 def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
617 LOGIC_FM_MM16<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
618 }
620 def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
621 ISA_MICROMIPS32_NOT_MIPS32R6;
622 def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
623 ISA_MICROMIPS32_NOT_MIPS32R6;
624 let FastISelShouldIgnore = 1 in
625 def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
626 ISA_MICROMIPS32_NOT_MIPS32R6;
627 def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
628 SHIFT_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;
629 def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
630 SHIFT_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;
632 let FastISelShouldIgnore = 1 in {
633 def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
634 ARITH_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;
635 def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
636 LOGIC_FM_MM16<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;
637 }
638 def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
639 mem_mm_4>, LOAD_STORE_FM_MM16<0x02>, ISA_MICROMIPS;
640 def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU,
641 mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>, ISA_MICROMIPS;
642 def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>,
643 LOAD_STORE_FM_MM16<0x1a>, ISA_MICROMIPS;
644 def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8,
645 II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>,
646 ISA_MICROMIPS32_NOT_MIPS32R6;
647 def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16,
648 II_SH, mem_mm_4_lsl1>,
649 LOAD_STORE_FM_MM16<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6;
650 def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW,
651 mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>,
652 ISA_MICROMIPS32_NOT_MIPS32R6;
653 def LWGP_MM : LoadGPMM16<"lw", GPRMM16Opnd, II_LW, mem_mm_gp_simm7_lsl2>,
654 LOAD_GP_FM_MM16<0x19>, ISA_MICROMIPS;
655 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
656 LOAD_STORE_SP_FM_MM16<0x12>, ISA_MICROMIPS;
657 def SWSP_MM : StoreSPMM16<"swsp", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
658 LOAD_STORE_SP_FM_MM16<0x32>, ISA_MICROMIPS32_NOT_MIPS32R6;
659 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16,
660 ISA_MICROMIPS;
661 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16,
662 ISA_MICROMIPS;
663 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16,
664 ISA_MICROMIPS;
665 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16, ISA_MICROMIPS;
666 def MFHI16_MM : MoveFromHILOMM<"mfhi16", GPR32Opnd, AC0>,
667 MFHILO_FM_MM16<0x10>, ISA_MICROMIPS32_NOT_MIPS32R6;
668 def MFLO16_MM : MoveFromHILOMM<"mflo16", GPR32Opnd, AC0>,
669 MFHILO_FM_MM16<0x12>, ISA_MICROMIPS32_NOT_MIPS32R6;
670 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>,
671 ISA_MICROMIPS32_NOT_MIPS32R6;
672 def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMovePPairFirst,
673 GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP>,
674 MOVEP_FM_MM16, ISA_MICROMIPS32_NOT_MIPS32R6;
675 def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
676 IsAsCheapAsAMove, ISA_MICROMIPS32_NOT_MIPS32R6;
677 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
678 ISA_MICROMIPS32_NOT_MIPS32R6;
679 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>,
680 ISA_MICROMIPS32_NOT_MIPS32R6;
681 def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>,
682 ISA_MICROMIPS32_NOT_MIPS32R6;
683 def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>,
684 ISA_MICROMIPS32_NOT_MIPS32R6;
685 def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>,
686 ISA_MICROMIPS32_NOT_MIPS32R6;
687 def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>,
688 BEQNEZ_FM_MM16<0x23>, ISA_MICROMIPS32_NOT_MIPS32R6;
689 def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>,
690 BEQNEZ_FM_MM16<0x2b>, ISA_MICROMIPS32_NOT_MIPS32R6;
691 def B16_MM : UncondBranchMM16<"b16">, B16_FM, ISA_MICROMIPS32_NOT_MIPS32R6;
692 def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
693 ISA_MICROMIPS32_NOT_MIPS32R6;
694 def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
695 ISA_MICROMIPS32_NOT_MIPS32R6;
697 class WaitMM<string opstr> :
698 InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [],
699 II_WAIT, FrmOther, opstr>;
701 let DecoderNamespace = "MicroMips" in {
702 /// Load and Store Instructions - multiple
703 def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>,
704 ISA_MICROMIPS32_NOT_MIPS32R6;
705 def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>,
706 ISA_MICROMIPS32_NOT_MIPS32R6;
707 def CFC2_MM : InstSE<(outs GPR32Opnd:$rt), (ins COP2Opnd:$impl),
708 "cfc2\t$rt, $impl", [], II_CFC2, FrmFR, "cfc2">,
709 POOL32A_CFTC2_FM_MM<0b1100110100>, ISA_MICROMIPS;
710 def CTC2_MM : InstSE<(outs COP2Opnd:$impl), (ins GPR32Opnd:$rt),
711 "ctc2\t$rt, $impl", [], II_CTC2, FrmFR, "ctc2">,
712 POOL32A_CFTC2_FM_MM<0b1101110100>, ISA_MICROMIPS;
714 /// Compact Branch Instructions
715 def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>,
716 COMPACT_BRANCH_FM_MM<0x7>, ISA_MICROMIPS32_NOT_MIPS32R6;
717 def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>,
718 COMPACT_BRANCH_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;
720 /// Arithmetic Instructions (ALU Immediate)
721 def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>,
722 ADDI_FM_MM<0xc>, ISA_MICROMIPS32_NOT_MIPS32R6;
723 def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>,
724 ADDI_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6;
725 def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
726 SLTI_FM_MM<0x24>, ISA_MICROMIPS;
727 def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
728 SLTI_FM_MM<0x2c>, ISA_MICROMIPS;
729 def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>,
730 ADDI_FM_MM<0x34>, ISA_MICROMIPS32_NOT_MIPS32R6;
731 def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
732 or>, ADDI_FM_MM<0x14>,
733 ISA_MICROMIPS32_NOT_MIPS32R6;
734 def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI,
735 immZExt16, xor>, ADDI_FM_MM<0x1c>,
736 ISA_MICROMIPS32_NOT_MIPS32R6;
737 def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM_MM,
738 ISA_MICROMIPS32_NOT_MIPS32R6;
740 def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
741 LW_FM_MM<0xc>, ISA_MICROMIPS;
743 /// Arithmetic Instructions (3-Operand, R-Type)
744 def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
745 ADD_FM_MM<0, 0x150>, ISA_MICROMIPS32_NOT_MIPS32R6;
746 def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
747 ADD_FM_MM<0, 0x1d0>, ISA_MICROMIPS32_NOT_MIPS32R6;
748 let Defs = [HI0, LO0] in
749 def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
750 ADD_FM_MM<0, 0x210>, ISA_MICROMIPS32_NOT_MIPS32R6;
751 def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>,
752 ADD_FM_MM<0, 0x110>, ISA_MICROMIPS32_NOT_MIPS32R6;
753 def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>,
754 ADD_FM_MM<0, 0x190>, ISA_MICROMIPS32_NOT_MIPS32R6;
755 def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>,
756 ISA_MICROMIPS;
757 def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>,
758 ADD_FM_MM<0, 0x390>, ISA_MICROMIPS;
759 def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
760 ADD_FM_MM<0, 0x250>, ISA_MICROMIPS32_NOT_MIPS32R6;
761 def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
762 ADD_FM_MM<0, 0x290>, ISA_MICROMIPS32_NOT_MIPS32R6;
763 def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
764 ADD_FM_MM<0, 0x310>, ISA_MICROMIPS32_NOT_MIPS32R6;
765 def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>,
766 ISA_MICROMIPS32_NOT_MIPS32R6;
767 def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
768 MULT_FM_MM<0x22c>, ISA_MICROMIPS32_NOT_MIPS32R6;
769 def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
770 MULT_FM_MM<0x26c>, ISA_MICROMIPS32_NOT_MIPS32R6;
771 def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
772 MULT_FM_MM<0x2ac>, ISA_MICROMIPS32_NOT_MIPS32R6;
773 def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
774 MULT_FM_MM<0x2ec>, ISA_MICROMIPS32_NOT_MIPS32R6;
776 /// Arithmetic Instructions with PC and Immediate
777 def ADDIUPC_MM : AddImmUPC<"addiupc", GPRMM16Opnd>, ADDIUPC_FM_MM,
778 ISA_MICROMIPS32_NOT_MIPS32R6;
780 /// Shift Instructions
781 def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>,
782 SRA_FM_MM<0, 0>, ISA_MICROMIPS;
783 def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>,
784 SRA_FM_MM<0x40, 0>, ISA_MICROMIPS;
785 def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>,
786 SRA_FM_MM<0x80, 0>, ISA_MICROMIPS;
787 def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>,
788 SRLV_FM_MM<0x10, 0>, ISA_MICROMIPS;
789 def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>,
790 SRLV_FM_MM<0x50, 0>, ISA_MICROMIPS;
791 def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>,
792 SRLV_FM_MM<0x90, 0>, ISA_MICROMIPS;
793 def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>,
794 SRA_FM_MM<0xc0, 0>, ISA_MICROMIPS {
795 list<dag> Pattern = [(set GPR32Opnd:$rd,
796 (rotr GPR32Opnd:$rt, immZExt5:$shamt))];
797 }
798 def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
799 SRLV_FM_MM<0xd0, 0>, ISA_MICROMIPS {
800 list<dag> Pattern = [(set GPR32Opnd:$rd,
801 (rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];
802 }
804 /// Load and Store Instructions - aligned
805 let DecoderMethod = "DecodeMemMMImm16" in {
806 def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, sextloadi8, II_LB>,
807 MMRel, LW_FM_MM<0x7>, ISA_MICROMIPS;
808 def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, zextloadi8, II_LBU>,
809 MMRel, LW_FM_MM<0x5>, ISA_MICROMIPS;
810 def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simmptr, sextloadi16, II_LH,
811 addrDefault>, MMRel, LW_FM_MM<0xf>, ISA_MICROMIPS;
812 def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simmptr, zextloadi16, II_LHU>,
813 MMRel, LW_FM_MM<0xd>, ISA_MICROMIPS;
814 def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>,
815 ISA_MICROMIPS;
816 def SB_MM : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
817 LW_FM_MM<0x6>, ISA_MICROMIPS;
818 def SH_MM : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel,
819 LW_FM_MM<0xe>, ISA_MICROMIPS;
820 def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
821 LW_FM_MM<0x3e>, ISA_MICROMIPS;
822 }
824 let DecoderMethod = "DecodeMemMMImm9" in {
825 def LBE_MM : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
826 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>, ISA_MICROMIPS, ASE_EVA;
827 def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
828 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>, ISA_MICROMIPS, ASE_EVA;
829 def LHE_MM : MMRel, LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag,
830 II_LHE>,
831 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>, ISA_MICROMIPS, ASE_EVA;
832 def LHuE_MM : MMRel, LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag,
833 II_LHUE>,
834 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>, ISA_MICROMIPS, ASE_EVA;
835 def LWE_MM : MMRel, LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag,
836 II_LWE>,
837 POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>, ISA_MICROMIPS, ASE_EVA;
838 def SBE_MM : MMRel, StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag,
839 II_SBE>,
840 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>, ISA_MICROMIPS, ASE_EVA;
841 def SHE_MM : MMRel, StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag,
842 II_SHE>,
843 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>, ISA_MICROMIPS, ASE_EVA;
844 def SWE_MM : MMRel, StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag,
845 II_SWE>,
846 POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>, ISA_MICROMIPS, ASE_EVA;
847 def LWLE_MM : MMRel, LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9,
848 II_LWLE>,
849 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>,
850 ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
851 def LWRE_MM : MMRel, LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9,
852 II_LWRE>,
853 POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>,
854 ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
855 def SWLE_MM : MMRel, StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9,
856 II_SWLE>,
857 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>,
858 ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
859 def SWRE_MM : MMRel, StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9,
860 II_SWRE>,
861 POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>,
862 ISA_MICROMIPS32_NOT_MIPS32R6, ASE_EVA;
863 }
865 def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>,
866 ISA_MICROMIPS;
868 /// Load and Store Instructions - unaligned
869 def LWL_MM : MMRel, LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12,
870 II_LWL>, LWL_FM_MM<0x0>,
871 ISA_MICROMIPS32_NOT_MIPS32R6;
872 def LWR_MM : MMRel, LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12,
873 II_LWR>, LWL_FM_MM<0x1>,
874 ISA_MICROMIPS32_NOT_MIPS32R6;
875 def SWL_MM : MMRel, StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12,
876 II_SWL>, LWL_FM_MM<0x8>,
877 ISA_MICROMIPS32_NOT_MIPS32R6;
878 def SWR_MM : MMRel, StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12,
879 II_SWR>, LWL_FM_MM<0x9>,
880 ISA_MICROMIPS32_NOT_MIPS32R6;
882 /// Load and Store Instructions - multiple
883 def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>, ISA_MICROMIPS;
884 def LWM32_MM : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>, ISA_MICROMIPS;
886 /// Load and Store Pair Instructions
887 def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>, ISA_MICROMIPS;
888 def LWP_MM : LoadPairMM<"lwp">, LWM_FM_MM<0x1>, ISA_MICROMIPS;
890 /// Load and Store multiple pseudo Instructions
891 class LoadWordMultMM<string instr_asm > :
892 MipsAsmPseudoInst<(outs reglist:$rt), (ins mem_mm_12:$addr),
893 !strconcat(instr_asm, "\t$rt, $addr")> ;
895 class StoreWordMultMM<string instr_asm > :
896 MipsAsmPseudoInst<(outs), (ins reglist:$rt, mem_mm_12:$addr),
897 !strconcat(instr_asm, "\t$rt, $addr")> ;
900 def SWM_MM : StoreWordMultMM<"swm">, ISA_MICROMIPS;
901 def LWM_MM : LoadWordMultMM<"lwm">, ISA_MICROMIPS;
903 /// Move Conditional
904 def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
905 II_MOVZ>, ADD_FM_MM<0, 0x58>,
906 ISA_MICROMIPS32_NOT_MIPS32R6;
907 def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
908 II_MOVN>, ADD_FM_MM<0, 0x18>,
909 ISA_MICROMIPS32_NOT_MIPS32R6;
910 def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
911 CMov_F_I_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;
912 def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
913 CMov_F_I_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;
914 /// Move to/from HI/LO
915 def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
916 MTLO_FM_MM<0x0b5>, ISA_MICROMIPS32_NOT_MIPS32R6;
917 def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
918 MTLO_FM_MM<0x0f5>, ISA_MICROMIPS32_NOT_MIPS32R6;
919 def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
920 MFLO_FM_MM<0x035>, ISA_MICROMIPS32_NOT_MIPS32R6;
921 def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
922 MFLO_FM_MM<0x075>, ISA_MICROMIPS32_NOT_MIPS32R6;
924 /// Multiply Add/Sub Instructions
925 def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>,
926 ISA_MICROMIPS32_NOT_MIPS32R6;
927 def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>,
928 ISA_MICROMIPS32_NOT_MIPS32R6;
929 def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>,
930 ISA_MICROMIPS32_NOT_MIPS32R6;
931 def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>,
932 ISA_MICROMIPS32_NOT_MIPS32R6;
934 /// Count Leading
935 def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
936 ISA_MICROMIPS;
937 def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,
938 ISA_MICROMIPS;
940 /// Sign Ext In Register Instructions.
941 def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
942 SEB_FM_MM<0x0ac>, ISA_MICROMIPS;
943 def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
944 SEB_FM_MM<0x0ec>, ISA_MICROMIPS;
946 /// Word Swap Bytes Within Halfwords
947 def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
948 SEB_FM_MM<0x1ec>, ISA_MICROMIPS;
949 // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
950 def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
951 immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>,
952 ISA_MICROMIPS32_NOT_MIPS32R6;
953 def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
954 immZExt5, immZExt5Plus1>,
955 EXT_FM_MM<0x0c>, ISA_MICROMIPS32_NOT_MIPS32R6;
957 /// Jump Instructions
958 let DecoderMethod = "DecodeJumpTargetMM" in {
959 def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
960 J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,
961 IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;
962 def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>,
963 ISA_MICROMIPS32_NOT_MIPS32R6;
964 }
966 let DecoderMethod = "DecodeJumpTargetXMM" in
967 def JALX_MM : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>,
968 ISA_MICROMIPS32_NOT_MIPS32R6;
970 def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
971 ISA_MICROMIPS32_NOT_MIPS32R6;
972 def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>,
973 ISA_MICROMIPS32_NOT_MIPS32R6;
975 /// Jump Instructions - Short Delay Slot
976 def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>,
977 ISA_MICROMIPS32_NOT_MIPS32R6;
978 def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>,
979 ISA_MICROMIPS32_NOT_MIPS32R6;
981 /// Branch Instructions
982 def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>,
983 BEQ_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;
984 def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>,
985 BEQ_FM_MM<0x2d>, ISA_MICROMIPS32_NOT_MIPS32R6;
986 def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>,
987 BGEZ_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
988 def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>,
989 BGEZ_FM_MM<0x6>, ISA_MICROMIPS32_NOT_MIPS32R6;
990 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
991 BGEZ_FM_MM<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6;
992 def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>,
993 BGEZ_FM_MM<0x0>, ISA_MICROMIPS32_NOT_MIPS32R6;
994 def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>,
995 BGEZAL_FM_MM<0x03>, ISA_MICROMIPS32_NOT_MIPS32R6;
996 def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>,
997 BGEZAL_FM_MM<0x01>, ISA_MICROMIPS32_NOT_MIPS32R6;
998 def BAL_BR_MM : BAL_BR_Pseudo<BGEZAL_MM, brtarget_mm>,
999 ISA_MICROMIPS32_NOT_MIPS32R6;
1001 /// Branch Instructions - Short Delay Slot
1002 def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm,
1003 GPR32Opnd>, BGEZAL_FM_MM<0x13>,
1004 ISA_MICROMIPS32_NOT_MIPS32R6;
1005 def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm,
1006 GPR32Opnd>, BGEZAL_FM_MM<0x11>,
1007 ISA_MICROMIPS32_NOT_MIPS32R6;
1008 def B_MM : UncondBranch<BEQ_MM, brtarget_mm>, IsBranch,
1009 ISA_MICROMIPS32_NOT_MIPS32R6;
1011 /// Control Instructions
1012 def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM, ISA_MICROMIPS;
1013 let DecoderMethod = "DecodeSyncI_MM" in
1014 def SYNCI_MM : MMRel, SYNCI_FT<"synci", mem_mm_16>, SYNCI_FM_MM,
1015 ISA_MICROMIPS32_NOT_MIPS32R6;
1016 def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM, ISA_MICROMIPS;
1017 def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM,
1018 ISA_MICROMIPS;
1019 def WAIT_MM : MMRel, WaitMM<"wait">, WAIT_FM_MM, ISA_MICROMIPS;
1020 def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>,
1021 ISA_MICROMIPS;
1022 def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>,
1023 ISA_MICROMIPS;
1024 def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>,
1025 ISA_MICROMIPS;
1026 def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>,
1027 ISA_MICROMIPS;
1028 def TRAP_MM : TrapBase<BREAK_MM>, ISA_MICROMIPS;
1030 /// Trap Instructions
1031 def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>,
1032 ISA_MICROMIPS;
1033 def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>,
1034 ISA_MICROMIPS;
1035 def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>,
1036 TEQ_FM_MM<0x10>, ISA_MICROMIPS;
1037 def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>,
1038 ISA_MICROMIPS;
1039 def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>,
1040 TEQ_FM_MM<0x28>, ISA_MICROMIPS;
1041 def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>,
1042 ISA_MICROMIPS;
1044 def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>,
1045 ISA_MICROMIPS32_NOT_MIPS32R6;
1046 def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>,
1047 ISA_MICROMIPS32_NOT_MIPS32R6;
1048 def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>,
1049 TEQI_FM_MM<0x0b>, ISA_MICROMIPS32_NOT_MIPS32R6;
1050 def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>,
1051 ISA_MICROMIPS32_NOT_MIPS32R6;
1052 def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>,
1053 TEQI_FM_MM<0x0a>, ISA_MICROMIPS32_NOT_MIPS32R6;
1054 def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>,
1055 ISA_MICROMIPS32_NOT_MIPS32R6;
1057 /// Load-linked, Store-conditional
1058 def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>,
1059 ISA_MICROMIPS32_NOT_MIPS32R6;
1060 def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>,
1061 ISA_MICROMIPS32_NOT_MIPS32R6;
1063 def LLE_MM : MMRel, LLEBaseMM<"lle", GPR32Opnd>, LLE_FM_MM<0x6>,
1064 ISA_MICROMIPS, ASE_EVA;
1065 def SCE_MM : MMRel, SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>,
1066 ISA_MICROMIPS, ASE_EVA;
1068 let DecoderMethod = "DecodeCacheOpMM" in {
1069 def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>,
1070 CACHE_PREF_FM_MM<0x08, 0x6>, ISA_MICROMIPS32_NOT_MIPS32R6;
1071 def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>,
1072 CACHE_PREF_FM_MM<0x18, 0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
1073 }
1075 let DecoderMethod = "DecodePrefeOpMM" in {
1076 def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>,
1077 CACHE_PREFE_FM_MM<0x18, 0x2>, ISA_MICROMIPS, ASE_EVA;
1078 def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>,
1079 CACHE_PREFE_FM_MM<0x18, 0x3>, ISA_MICROMIPS, ASE_EVA;
1080 }
1081 def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>,
1082 ISA_MICROMIPS;
1083 def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>,
1084 ISA_MICROMIPS;
1085 def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>,
1086 ISA_MICROMIPS;
1088 def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>,
1089 ISA_MICROMIPS;
1090 def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>,
1091 ISA_MICROMIPS;
1092 def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>,
1093 ISA_MICROMIPS;
1094 def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>,
1095 ISA_MICROMIPS;
1097 def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10, II_SDBBP>, SDBBP_FM_MM,
1098 ISA_MICROMIPS;
1100 def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>,
1101 ISA_MICROMIPS32_NOT_MIPS32R6;
1102 }
1104 let AdditionalPredicates = [NotDSP] in {
1105 def PseudoMULT_MM : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1106 ISA_MICROMIPS32_NOT_MIPS32R6;
1107 def PseudoMULTu_MM : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1108 ISA_MICROMIPS32_NOT_MIPS32R6;
1109 def PseudoMFHI_MM : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>,
1110 ISA_MICROMIPS32_NOT_MIPS32R6;
1111 def PseudoMFLO_MM : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>,
1112 ISA_MICROMIPS32_NOT_MIPS32R6;
1113 def PseudoMTLOHI_MM : PseudoMTLOHI<ACC64, GPR32>,
1114 ISA_MICROMIPS32_NOT_MIPS32R6;
1115 def PseudoMADD_MM : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1116 ISA_MICROMIPS32_NOT_MIPS32R6;
1117 def PseudoMADDU_MM : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1118 ISA_MICROMIPS32_NOT_MIPS32R6;
1119 def PseudoMSUB_MM : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1120 ISA_MICROMIPS32_NOT_MIPS32R6;
1121 def PseudoMSUBU_MM : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1122 ISA_MICROMIPS32_NOT_MIPS32R6;
1123 }
1125 def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>,
1126 ISA_MICROMIPS32_NOT_MIPS32R6;
1128 def TAILCALLREG_MM : TailCallReg<JRC16_MM, GPR32Opnd>,
1129 ISA_MICROMIPS32_NOT_MIPS32R6;
1131 def PseudoIndirectBranch_MM : PseudoIndirectBranchBase<JR_MM, GPR32Opnd>,
1132 ISA_MICROMIPS32_NOT_MIPS32R6;
1134 let DecoderNamespace = "MicroMips" in {
1135 def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
1136 RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
1137 def LWU_MM : MMRel, LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU,
1138 mem_simm12>, LL_FM_MM<0xe>,
1139 ISA_MICROMIPS32_NOT_MIPS32R6;
1141 def MFGC0_MM : MMRel, MfCop0MM<"mfgc0", GPR32Opnd, COP0Opnd, II_MFGC0>,
1142 POOL32A_MFTC0_FM_MM<0b10011, 0b111100>,
1143 ISA_MICROMIPS32R5, ASE_VIRT;
1144 def MFHGC0_MM : MMRel, MfCop0MM<"mfhgc0", GPR32Opnd, COP0Opnd, II_MFHGC0>,
1145 POOL32A_MFTC0_FM_MM<0b10011, 0b110100>,
1146 ISA_MICROMIPS32R5, ASE_VIRT;
1147 def MTGC0_MM : MMRel, MtCop0MM<"mtgc0", COP0Opnd, GPR32Opnd, II_MTGC0>,
1148 POOL32A_MFTC0_FM_MM<0b11011, 0b111100>,
1149 ISA_MICROMIPS32R5, ASE_VIRT;
1150 def MTHGC0_MM : MMRel, MtCop0MM<"mthgc0", COP0Opnd, GPR32Opnd, II_MTHGC0>,
1151 POOL32A_MFTC0_FM_MM<0b11011, 0b110100>,
1152 ISA_MICROMIPS32R5, ASE_VIRT;
1153 def HYPCALL_MM : MMRel, HypcallMM<"hypcall">, POOL32A_HYPCALL_FM_MM,
1154 ISA_MICROMIPS32R5, ASE_VIRT;
1155 def TLBGINV_MM : MMRel, TLBINVMM<"tlbginv", II_TLBGINV>,
1156 POOL32A_TLBINV_FM_MM<0x105>, ISA_MICROMIPS32R5, ASE_VIRT;
1157 def TLBGINVF_MM : MMRel, TLBINVMM<"tlbginvf", II_TLBGINVF>,
1158 POOL32A_TLBINV_FM_MM<0x145>, ISA_MICROMIPS32R5, ASE_VIRT;
1159 def TLBGP_MM : MMRel, TLBINVMM<"tlbgp", II_TLBGP>,
1160 POOL32A_TLBINV_FM_MM<0x5>, ISA_MICROMIPS32R5, ASE_VIRT;
1161 def TLBGR_MM : MMRel, TLBINVMM<"tlbgr", II_TLBGR>,
1162 POOL32A_TLBINV_FM_MM<0x45>, ISA_MICROMIPS32R5, ASE_VIRT;
1163 def TLBGWI_MM : MMRel, TLBINVMM<"tlbgwi", II_TLBGWI>,
1164 POOL32A_TLBINV_FM_MM<0x85>, ISA_MICROMIPS32R5, ASE_VIRT;
1165 def TLBGWR_MM : MMRel, TLBINVMM<"tlbgwr", II_TLBGWR>,
1166 POOL32A_TLBINV_FM_MM<0xc5>, ISA_MICROMIPS32R5, ASE_VIRT;
1167 }
1169 //===----------------------------------------------------------------------===//
1170 // MicroMips arbitrary patterns that map to one or more instructions
1171 //===----------------------------------------------------------------------===//
1173 defm : MipsHiLoRelocs<LUi_MM, ADDiu_MM, ZERO, GPR32Opnd>, ISA_MICROMIPS;
1175 def : MipsPat<(MipsGotHi tglobaladdr:$in), (LUi_MM tglobaladdr:$in)>,
1176 ISA_MICROMIPS;
1177 def : MipsPat<(MipsGotHi texternalsym:$in), (LUi_MM texternalsym:$in)>,
1178 ISA_MICROMIPS;
1180 def : MipsPat<(MipsTlsHi tglobaltlsaddr:$in), (LUi_MM tglobaltlsaddr:$in)>,
1181 ISA_MICROMIPS;
1183 // gp_rel relocs
1184 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1185 (ADDiu_MM GPR32:$gp, tglobaladdr:$in)>, ISA_MICROMIPS;
1186 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1187 (ADDiu_MM GPR32:$gp, tconstpool:$in)>, ISA_MICROMIPS;
1189 def : WrapperPat<tglobaladdr, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1190 def : WrapperPat<tconstpool, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1191 def : WrapperPat<texternalsym, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1192 def : WrapperPat<tblockaddress, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1193 def : WrapperPat<tjumptable, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1194 def : WrapperPat<tglobaltlsaddr, ADDiu_MM, GPR32>, ISA_MICROMIPS;
1196 def : MipsPat<(atomic_load_8 addr:$a), (LB_MM addr:$a)>, ISA_MICROMIPS;
1197 def : MipsPat<(atomic_load_16 addr:$a), (LH_MM addr:$a)>, ISA_MICROMIPS;
1198 def : MipsPat<(atomic_load_32 addr:$a), (LW_MM addr:$a)>, ISA_MICROMIPS;
1200 def : MipsPat<(i32 immLi16:$imm),
1201 (LI16_MM immLi16:$imm)>, ISA_MICROMIPS;
1203 defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>, ISA_MICROMIPS;
1205 def : MipsPat<(not GPRMM16:$in),
1206 (NOT16_MM GPRMM16:$in)>, ISA_MICROMIPS;
1207 def : MipsPat<(not GPR32:$in),
1208 (NOR_MM GPR32Opnd:$in, ZERO)>, ISA_MICROMIPS;
1210 def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm),
1211 (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>, ISA_MICROMIPS;
1212 def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
1213 (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>, ISA_MICROMIPS;
1214 def : MipsPat<(add GPR32:$src, immSExt16:$imm),
1215 (ADDiu_MM GPR32:$src, immSExt16:$imm)>, ISA_MICROMIPS;
1217 def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
1218 (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>, ISA_MICROMIPS;
1219 def : MipsPat<(and GPR32:$src, immZExt16:$imm),
1220 (ANDi_MM GPR32:$src, immZExt16:$imm)>, ISA_MICROMIPS;
1222 def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm),
1223 (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>, ISA_MICROMIPS;
1224 def : MipsPat<(shl GPR32:$src, immZExt5:$imm),
1225 (SLL_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;
1226 def : MipsPat<(shl GPR32:$lhs, GPR32:$rhs),
1227 (SLLV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1229 def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm),
1230 (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>, ISA_MICROMIPS;
1231 def : MipsPat<(srl GPR32:$src, immZExt5:$imm),
1232 (SRL_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;
1233 def : MipsPat<(srl GPR32:$lhs, GPR32:$rhs),
1234 (SRLV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1236 def : MipsPat<(sra GPR32:$src, immZExt5:$imm),
1237 (SRA_MM GPR32:$src, immZExt5:$imm)>, ISA_MICROMIPS;
1238 def : MipsPat<(sra GPR32:$lhs, GPR32:$rhs),
1239 (SRAV_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1241 def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
1242 (SW16_MM GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS;
1243 def : MipsPat<(store GPR32:$src, addr:$addr),
1244 (SW_MM GPR32:$src, addr:$addr)>, ISA_MICROMIPS;
1246 def : MipsPat<(load addrimm4lsl2:$addr),
1247 (LW16_MM addrimm4lsl2:$addr)>, ISA_MICROMIPS;
1248 def : MipsPat<(load addr:$addr),
1249 (LW_MM addr:$addr)>, ISA_MICROMIPS;
1250 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1251 (SUBu_MM GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS;
1253 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_MM addr:$src)>,
1254 ISA_MICROMIPS;
1256 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_MM addr:$src)>,
1257 ISA_MICROMIPS;
1259 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>,
1260 ISA_MICROMIPS;
1262 let AddedComplexity = 40 in
1263 def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
1264 (LH_MM addrRegImm:$a)>, ISA_MICROMIPS;
1267 def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>,
1268 ISA_MICROMIPS;
1270 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1271 (JAL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1272 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1273 (TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1274 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1275 (TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1277 defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
1278 SLTiu_MM, ZERO>, ISA_MICROMIPS32_NOT_MIPS32R6;
1280 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1281 (BLEZ_MM i32:$lhs, bb:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1282 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1283 (BGEZ_MM i32:$lhs, bb:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
1285 defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>, ISA_MICROMIPS;
1286 defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>, ISA_MICROMIPS;
1287 defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>, ISA_MICROMIPS;
1288 defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>, ISA_MICROMIPS;
1289 defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>, ISA_MICROMIPS;
1291 // Select patterns
1293 // Instantiation of conditional move patterns.
1294 defm : MovzPats0<GPR32, GPR32, MOVZ_I_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,
1295 ISA_MICROMIPS32_NOT_MIPS32R6;
1296 defm : MovzPats1<GPR32, GPR32, MOVZ_I_MM, XOR_MM>,
1297 ISA_MICROMIPS32_NOT_MIPS32R6;
1298 defm : MovzPats2<GPR32, GPR32, MOVZ_I_MM, XORi_MM>,
1299 ISA_MICROMIPS32_NOT_MIPS32R6;
1302 defm : MovnPats<GPR32, GPR32, MOVN_I_MM, XOR_MM>, INSN_MIPS4_32_NOT_32R6_64R6;
1304 // Instantiation of conditional move patterns.
1305 defm : MovzPats0<GPR32, GPR32, MOVZ_I_MM, SLT_MM, SLTu_MM, SLTi_MM, SLTiu_MM>,
1306 ISA_MICROMIPS32_NOT_MIPS32R6;
1307 defm : MovzPats1<GPR32, GPR32, MOVZ_I_MM, XOR_MM>,
1308 ISA_MICROMIPS32_NOT_MIPS32R6;
1309 defm : MovzPats2<GPR32, GPR32, MOVZ_I_MM, XORi_MM>,
1310 ISA_MICROMIPS32_NOT_MIPS32R6;
1312 defm : MovnPats<GPR32, GPR32, MOVN_I_MM, XOR_MM>, ISA_MICROMIPS32_NOT_MIPS32R6;
1314 //===----------------------------------------------------------------------===//
1315 // MicroMips instruction aliases
1316 //===----------------------------------------------------------------------===//
1318 class UncondBranchMMPseudo<string opstr> :
1319 MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
1320 !strconcat(opstr, "\t$offset")>;
1322 def B_MM_Pseudo : UncondBranchMMPseudo<"b">, ISA_MICROMIPS;
1324 let EncodingPredicates = [InMicroMips] in {
1325 def SDIV_MM_Pseudo : MultDivPseudo<SDIV_MM, ACC64, GPR32Opnd, MipsDivRem,
1326 II_DIV, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1327 def UDIV_MM_Pseudo : MultDivPseudo<UDIV_MM, ACC64, GPR32Opnd, MipsDivRemU,
1328 II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1330 def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
1331 def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
1332 def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>, ISA_MICROMIPS;
1333 def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
1334 def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;
1335 def : MipsInstAlias<"neg $rt, $rs",
1336 (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1337 ISA_MICROMIPS32_NOT_MIPS32R6;
1338 def : MipsInstAlias<"neg $rt",
1339 (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1340 ISA_MICROMIPS32_NOT_MIPS32R6;
1341 def : MipsInstAlias<"negu $rt, $rs",
1342 (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>,
1343 ISA_MICROMIPS32_NOT_MIPS32R6;
1344 def : MipsInstAlias<"negu $rt",
1345 (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>,
1346 ISA_MICROMIPS32_NOT_MIPS32R6;
1347 def : MipsInstAlias<"teq $rs, $rt",
1348 (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1349 def : MipsInstAlias<"tge $rs, $rt",
1350 (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1351 def : MipsInstAlias<"tgeu $rs, $rt",
1352 (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1353 def : MipsInstAlias<"tlt $rs, $rt",
1354 (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1355 def : MipsInstAlias<"tltu $rs, $rt",
1356 (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1357 def : MipsInstAlias<"tne $rs, $rt",
1358 (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1359 def : MipsInstAlias<
1360 "sgt $rd, $rs, $rt",
1361 (SLT_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1362 def : MipsInstAlias<
1363 "sgt $rs, $rt",
1364 (SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1365 def : MipsInstAlias<
1366 "sgtu $rd, $rs, $rt",
1367 (SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1368 def : MipsInstAlias<
1369 "sgtu $rs, $rt",
1370 (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1371 def : MipsInstAlias<"sll $rd, $rt, $rs",
1372 (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1373 def : MipsInstAlias<"sra $rd, $rt, $rs",
1374 (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1375 def : MipsInstAlias<"srl $rd, $rt, $rs",
1376 (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1377 def : MipsInstAlias<"sll $rd, $rt",
1378 (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1379 def : MipsInstAlias<"sra $rd, $rt",
1380 (SRAV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1381 def : MipsInstAlias<"srl $rd, $rt",
1382 (SRLV_MM GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>;
1383 def : MipsInstAlias<"sll $rd, $shamt",
1384 (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1385 def : MipsInstAlias<"sra $rd, $shamt",
1386 (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1387 def : MipsInstAlias<"srl $rd, $shamt",
1388 (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1389 def : MipsInstAlias<"rotr $rt, $imm",
1390 (ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
1391 def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>, ISA_MICROMIPS;
1393 def : MipsInstAlias<"sync", (SYNC_MM 0), 1>, ISA_MICROMIPS;
1395 defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>, ISA_MICROMIPS;
1397 defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>, ISA_MICROMIPS;
1399 defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>, ISA_MICROMIPS;
1401 defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>, ISA_MICROMIPS;
1403 defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi_MM>, ISA_MICROMIPS;
1405 defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi_MM>, ISA_MICROMIPS;
1407 defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>, ISA_MICROMIPS;
1409 def : MipsInstAlias<"not $rt, $rs",
1410 (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>,
1411 ISA_MICROMIPS32_NOT_MIPS32R6;
1412 def : MipsInstAlias<"not $rt",
1413 (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>,
1414 ISA_MICROMIPS32_NOT_MIPS32R6;
1415 def : MipsInstAlias<"bnez $rs,$offset",
1416 (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
1417 ISA_MICROMIPS;
1418 def : MipsInstAlias<"beqz $rs,$offset",
1419 (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
1420 ISA_MICROMIPS;
1421 def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
1422 ISA_MICROMIPS;
1423 def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>,
1424 ISA_MICROMIPS;
1425 def : MipsInstAlias<"break", (BREAK_MM 0, 0), 1>, ISA_MICROMIPS;
1426 def : MipsInstAlias<"break $imm", (BREAK_MM uimm10:$imm, 0), 1>,
1427 ISA_MICROMIPS;
1428 def : MipsInstAlias<"bal $offset", (BGEZAL_MM ZERO, brtarget_mm:$offset), 1>,
1429 ISA_MICROMIPS32_NOT_MIPS32R6;
1431 def : MipsInstAlias<"j $rs", (JR_MM GPR32Opnd:$rs), 0>,
1432 ISA_MICROMIPS32_NOT_MIPS32R6;
1433 }
1434 def : MipsInstAlias<"rdhwr $rt, $rs",
1435 (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
1436 ISA_MICROMIPS32_NOT_MIPS32R6;
1438 def : MipsInstAlias<"hypcall", (HYPCALL_MM 0), 1>,
1439 ISA_MICROMIPS32R5, ASE_VIRT;
1440 def : MipsInstAlias<"mfgc0 $rt, $rs",
1441 (MFGC0_MM GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1442 ISA_MICROMIPS32R5, ASE_VIRT;
1443 def : MipsInstAlias<"mfhgc0 $rt, $rs",
1444 (MFHGC0_MM GPR32Opnd:$rt, COP0Opnd:$rs, 0), 0>,
1445 ISA_MICROMIPS32R5, ASE_VIRT;
1446 def : MipsInstAlias<"mtgc0 $rt, $rs",
1447 (MTGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1448 ISA_MICROMIPS32R5, ASE_VIRT;
1449 def : MipsInstAlias<"mthgc0 $rt, $rs",
1450 (MTHGC0_MM COP0Opnd:$rs, GPR32Opnd:$rt, 0), 0>,
1451 ISA_MICROMIPS32R5, ASE_VIRT;
1452 def : MipsInstAlias<"sw $rt, $offset",
1453 (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset), 1>,
1454 ISA_MICROMIPS;