1 //===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 //===----------------------------------------------------------------------===//
10 // Describe MIPS instructions format
12 // CPU INSTRUCTION FORMATS
14 // funct or f Function field
16 // immediate 4-,5-,8- or 11-bit immediate, branch displacement, or
17 // or imm address displacement
19 // op 5-bit major operation code
21 // rx 3-bit source or destination register
23 // ry 3-bit source or destination register
25 // rz 3-bit source or destination register
27 // sa 3- or 5-bit shift amount
29 //===----------------------------------------------------------------------===//
32 // Base class for Mips 16 Format
33 // This class does not depend on the instruction size
35 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
36 InstrItinClass itin>: Instruction
39 let Namespace = "Mips";
41 let OutOperandList = outs;
42 let InOperandList = ins;
44 let AsmString = asmstr;
45 let Pattern = pattern;
48 let Predicates = [InMips16Mode];
52 // Generic Mips 16 Format
54 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
56 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
61 // Top 5 bits are the 'opcode' field
62 let Inst{15-11} = Opcode;
65 field bits<16> SoftFail = 0;
69 // For 32 bit extended instruction forms.
71 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
73 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
78 field bits<32> SoftFail = 0;
81 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
83 MipsInst16_32<outs, ins, asmstr, pattern, itin>
85 let Inst{31-27} = 0b11110;
90 // Mips Pseudo Instructions Format
91 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
92 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
93 let isCodeGenOnly = 1;
98 //===----------------------------------------------------------------------===//
99 // Format I instruction class in Mips : <|opcode|imm11|>
100 //===----------------------------------------------------------------------===//
102 class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
103 InstrItinClass itin>:
104 MipsInst16<outs, ins, asmstr, pattern, itin>
110 let Inst{10-0} = imm11;
113 //===----------------------------------------------------------------------===//
114 // Format RI instruction class in Mips : <|opcode|rx|imm8|>
115 //===----------------------------------------------------------------------===//
117 class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
118 list<dag> pattern, InstrItinClass itin>:
119 MipsInst16<outs, ins, asmstr, pattern, itin>
127 let Inst{7-0} = imm8;
130 //===----------------------------------------------------------------------===//
131 // Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
132 //===----------------------------------------------------------------------===//
134 class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
135 list<dag> pattern, InstrItinClass itin>:
136 MipsInst16<outs, ins, asmstr, pattern, itin>
142 let Opcode = 0b11101;
147 let Inst{4-0} = funct;
150 class FRRBreak16<dag outs, dag ins, string asmstr,
151 list<dag> pattern, InstrItinClass itin>:
152 MipsInst16<outs, ins, asmstr, pattern, itin>
157 let Opcode = 0b11101;
160 let Inst{10-5} = Code;
161 let Inst{4-0} = funct;
165 // For conversion functions.
167 class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
168 string asmstr, list<dag> pattern, InstrItinClass itin>:
169 MipsInst16<outs, ins, asmstr, pattern, itin>
175 let Opcode = 0b11101; // RR
177 let subfunct = _subfunct;
180 let Inst{7-5} = subfunct;
181 let Inst{4-0} = funct;
185 // just used for breakpoint (hardware and software) instructions.
187 class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
188 list<dag> pattern, InstrItinClass itin>:
189 MipsInst16<outs, ins, asmstr, pattern, itin>
191 bits<6> _code; // code is a keyword in tablegen
194 let Opcode = 0b11101; // RR
197 let Inst{10-5} = _code;
198 let Inst{4-0} = funct;
202 // J(AL)R(C) subformat
204 class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
205 dag outs, dag ins, string asmstr,
206 list<dag> pattern, InstrItinClass itin>:
207 MipsInst16<outs, ins, asmstr, pattern, itin>
218 let Opcode = 0b11101;
227 //===----------------------------------------------------------------------===//
228 // Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
229 //===----------------------------------------------------------------------===//
231 class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
232 list<dag> pattern, InstrItinClass itin>:
233 MipsInst16<outs, ins, asmstr, pattern, itin>
244 let Inst{4-0} = imm5;
247 //===----------------------------------------------------------------------===//
248 // Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
249 //===----------------------------------------------------------------------===//
251 class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
252 list<dag> pattern, InstrItinClass itin>:
253 MipsInst16<outs, ins, asmstr, pattern, itin>
260 let Opcode = 0b11100;
269 //===----------------------------------------------------------------------===//
270 // Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
271 //===----------------------------------------------------------------------===//
273 class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
274 list<dag> pattern, InstrItinClass itin>:
275 MipsInst16<outs, ins, asmstr, pattern, itin>
282 let Opcode = 0b01000;
288 let Inst{3-0} = imm4;
291 //===----------------------------------------------------------------------===//
292 // Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
293 //===----------------------------------------------------------------------===//
295 class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
296 list<dag> pattern, InstrItinClass itin>:
297 MipsInst16<outs, ins, asmstr, pattern, itin>
304 let Opcode = 0b00110;
313 //===----------------------------------------------------------------------===//
314 // Format i8 instruction class in Mips : <|opcode|funct|imm8>
315 //===----------------------------------------------------------------------===//
317 class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
318 list<dag> pattern, InstrItinClass itin>:
319 MipsInst16<outs, ins, asmstr, pattern, itin>
324 let Opcode = 0b01100;
327 let Inst{10-8} = func;
328 let Inst{7-0} = imm8;
331 //===----------------------------------------------------------------------===//
332 // Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
333 //===----------------------------------------------------------------------===//
335 class FI8_MOVR3216<dag outs, dag ins, string asmstr,
336 list<dag> pattern, InstrItinClass itin>:
337 MipsInst16<outs, ins, asmstr, pattern, itin>
343 let Opcode = 0b01100;
345 let Inst{10-8} = 0b111;
353 //===----------------------------------------------------------------------===//
354 // Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz>
355 //===----------------------------------------------------------------------===//
357 class FI8_MOV32R16<dag outs, dag ins, string asmstr,
358 list<dag> pattern, InstrItinClass itin>:
359 MipsInst16<outs, ins, asmstr, pattern, itin>
367 let Opcode = 0b01100;
369 let Inst{10-8} = 0b101;
370 let Inst{7-5} = r32{2-0};
371 let Inst{4-3} = r32{4-3};
376 //===----------------------------------------------------------------------===//
377 // Format i8_SVRS instruction class in Mips :
378 // <|opcode|svrs|s|ra|s0|s1|framesize>
379 //===----------------------------------------------------------------------===//
381 class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
382 list<dag> pattern, InstrItinClass itin>:
383 MipsInst16<outs, ins, asmstr, pattern, itin>
389 bits<4> framesize = 0;
392 let Opcode = 0b01100;
394 let Inst{10-8} = 0b100;
399 let Inst{3-0} = framesize;
403 //===----------------------------------------------------------------------===//
404 // Format JAL instruction class in Mips16 :
405 // <|opcode|svrs|s|ra|s0|s1|framesize>
406 //===----------------------------------------------------------------------===//
408 class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
409 list<dag> pattern, InstrItinClass itin>:
410 MipsInst16_32<outs, ins, asmstr, pattern, itin>
418 let Inst{31-27} = 0b00011;
420 let Inst{25-21} = imm26{20-16};
421 let Inst{20-16} = imm26{25-21};
422 let Inst{15-0} = imm26{15-0};
426 //===----------------------------------------------------------------------===//
427 // Format EXT-I instruction class in Mips16 :
428 // <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
429 //===----------------------------------------------------------------------===//
431 class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
432 list<dag> pattern, InstrItinClass itin>:
433 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
440 let Inst{26-21} = imm16{10-5};
441 let Inst{20-16} = imm16{15-11};
442 let Inst{15-11} = eop;
444 let Inst{4-0} = imm16{4-0};
448 //===----------------------------------------------------------------------===//
449 // Format ASMACRO instruction class in Mips16 :
450 // <EXTEND|select|p4|p3|RRR|p2|p1|p0>
451 //===----------------------------------------------------------------------===//
453 class FASMACRO16<dag outs, dag ins, string asmstr,
454 list<dag> pattern, InstrItinClass itin>:
455 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
460 bits<5> RRR = 0b11100;
466 let Inst{26-24} = select;
467 let Inst{23-21} = p4;
468 let Inst{20-16} = p3;
469 let Inst{15-11} = RRR;
477 //===----------------------------------------------------------------------===//
478 // Format EXT-RI instruction class in Mips16 :
479 // <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
480 //===----------------------------------------------------------------------===//
482 class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
483 list<dag> pattern, InstrItinClass itin>:
484 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
492 let Inst{26-21} = imm16{10-5};
493 let Inst{20-16} = imm16{15-11};
494 let Inst{15-11} = op;
497 let Inst{4-0} = imm16{4-0};
501 //===----------------------------------------------------------------------===//
502 // Format EXT-RRI instruction class in Mips16 :
503 // <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
504 //===----------------------------------------------------------------------===//
506 class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
507 list<dag> pattern, InstrItinClass itin>:
508 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
517 let Inst{26-21} = imm16{10-5};
518 let Inst{20-16} = imm16{15-11};
519 let Inst{15-11} = op;
522 let Inst{4-0} = imm16{4-0};
526 //===----------------------------------------------------------------------===//
527 // Format EXT-RRI-A instruction class in Mips16 :
528 // <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
529 //===----------------------------------------------------------------------===//
531 class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
532 list<dag> pattern, InstrItinClass itin>:
533 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
542 let Inst{26-20} = imm15{10-4};
543 let Inst{19-16} = imm15{14-11};
544 let Inst{15-11} = 0b01000;
548 let Inst{3-0} = imm15{3-0};
552 //===----------------------------------------------------------------------===//
553 // Format EXT-SHIFT instruction class in Mips16 :
554 // <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
555 //===----------------------------------------------------------------------===//
557 class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
558 list<dag> pattern, InstrItinClass itin>:
559 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
568 let Inst{26-22} = sa6{4-0};
569 let Inst{21} = sa6{5};
571 let Inst{15-11} = 0b00110;
579 //===----------------------------------------------------------------------===//
580 // Format EXT-I8 instruction class in Mips16 :
581 // <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
582 //===----------------------------------------------------------------------===//
584 class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
585 list<dag> pattern, InstrItinClass itin>:
586 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
595 let Inst{26-21} = imm16{10-5};
596 let Inst{20-16} = imm16{15-11};
597 let Inst{15-11} = I8;
598 let Inst{10-8} = funct;
600 let Inst{4-0} = imm16{4-0};
604 //===----------------------------------------------------------------------===//
605 // Format EXT-I8_SVRS instruction class in Mips16 :
606 // <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
607 //===----------------------------------------------------------------------===//
609 class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
610 list<dag> pattern, InstrItinClass itin>:
611 MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
614 bits<8> framesize =0;
616 bits<5> I8 = 0b01100;
617 bits<3> SVRS = 0b100;
625 let Inst{26-24} = xsregs;
626 let Inst{23-20} = framesize{7-4};
628 let Inst{18-16} = aregs;
629 let Inst{15-11} = I8;
630 let Inst{10-8} = SVRS;
635 let Inst{3-0} = framesize{3-0};