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[InstCombine] Signed saturation patterns
[llvm-core.git] / lib / Target / Mips / MipsISelLowering.cpp
blobbf1b4756b24faaa3f5d236bd7c6dee52140ef412
1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that Mips uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "MipsISelLowering.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MCTargetDesc/MipsInstPrinter.h"
17 #include "MCTargetDesc/MipsMCTargetDesc.h"
18 #include "MipsCCState.h"
19 #include "MipsInstrInfo.h"
20 #include "MipsMachineFunction.h"
21 #include "MipsRegisterInfo.h"
22 #include "MipsSubtarget.h"
23 #include "MipsTargetMachine.h"
24 #include "MipsTargetObjectFile.h"
25 #include "llvm/ADT/APFloat.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/SmallVector.h"
28 #include "llvm/ADT/Statistic.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/StringSwitch.h"
31 #include "llvm/CodeGen/CallingConvLower.h"
32 #include "llvm/CodeGen/FunctionLoweringInfo.h"
33 #include "llvm/CodeGen/ISDOpcodes.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstr.h"
38 #include "llvm/CodeGen/MachineInstrBuilder.h"
39 #include "llvm/CodeGen/MachineJumpTableInfo.h"
40 #include "llvm/CodeGen/MachineMemOperand.h"
41 #include "llvm/CodeGen/MachineOperand.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/RuntimeLibcalls.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/CodeGen/SelectionDAGNodes.h"
46 #include "llvm/CodeGen/TargetFrameLowering.h"
47 #include "llvm/CodeGen/TargetInstrInfo.h"
48 #include "llvm/CodeGen/TargetRegisterInfo.h"
49 #include "llvm/CodeGen/ValueTypes.h"
50 #include "llvm/IR/CallingConv.h"
51 #include "llvm/IR/Constants.h"
52 #include "llvm/IR/DataLayout.h"
53 #include "llvm/IR/DebugLoc.h"
54 #include "llvm/IR/DerivedTypes.h"
55 #include "llvm/IR/Function.h"
56 #include "llvm/IR/GlobalValue.h"
57 #include "llvm/IR/Type.h"
58 #include "llvm/IR/Value.h"
59 #include "llvm/MC/MCContext.h"
60 #include "llvm/MC/MCRegisterInfo.h"
61 #include "llvm/Support/Casting.h"
62 #include "llvm/Support/CodeGen.h"
63 #include "llvm/Support/CommandLine.h"
64 #include "llvm/Support/Compiler.h"
65 #include "llvm/Support/ErrorHandling.h"
66 #include "llvm/Support/MachineValueType.h"
67 #include "llvm/Support/MathExtras.h"
68 #include "llvm/Target/TargetMachine.h"
69 #include "llvm/Target/TargetOptions.h"
70 #include <algorithm>
71 #include <cassert>
72 #include <cctype>
73 #include <cstdint>
74 #include <deque>
75 #include <iterator>
76 #include <utility>
77 #include <vector>
78
79 using namespace llvm;
80
81 #define DEBUG_TYPE "mips-lower"
82
83 STATISTIC(NumTailCalls, "Number of tail calls");
84
85 static cl::opt<bool>
86 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
87 cl::desc("MIPS: Don't trap on integer division by zero."),
88 cl::init(false));
89
90 extern cl::opt<bool> EmitJalrReloc;
91
92 static const MCPhysReg Mips64DPRegs[8] = {
93 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
94 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
95 };
96
97 // If I is a shifted mask, set the size (Size) and the first bit of the
98 // mask (Pos), and return true.
99 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11).
100 static bool isShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) {
101 if (!isShiftedMask_64(I))
102 return false;
103
104 Size = countPopulation(I);
105 Pos = countTrailingZeros(I);
106 return true;
107 }
108
109 // The MIPS MSA ABI passes vector arguments in the integer register set.
110 // The number of integer registers used is dependant on the ABI used.
111 MVT MipsTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
112 CallingConv::ID CC,
113 EVT VT) const {
114 if (VT.isVector()) {
115 if (Subtarget.isABI_O32()) {
116 return MVT::i32;
117 } else {
118 return (VT.getSizeInBits() == 32) ? MVT::i32 : MVT::i64;
119 }
120 }
121 return MipsTargetLowering::getRegisterType(Context, VT);
122 }
123
124 unsigned MipsTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
125 CallingConv::ID CC,
126 EVT VT) const {
127 if (VT.isVector())
128 return std::max((VT.getSizeInBits() / (Subtarget.isABI_O32() ? 32 : 64)),
129 1U);
130 return MipsTargetLowering::getNumRegisters(Context, VT);
131 }
132
133 unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv(
134 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
135 unsigned &NumIntermediates, MVT &RegisterVT) const {
136 // Break down vector types to either 2 i64s or 4 i32s.
137 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT);
138 IntermediateVT = RegisterVT;
139 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits()
140 ? VT.getVectorNumElements()
141 : VT.getSizeInBits() / RegisterVT.getSizeInBits();
142
143 return NumIntermediates;
144 }
145
146 SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const {
147 MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo<MipsFunctionInfo>();
148 return DAG.getRegister(FI->getGlobalBaseReg(), Ty);
149 }
150
151 SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty,
152 SelectionDAG &DAG,
153 unsigned Flag) const {
154 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag);
155 }
156
157 SDValue MipsTargetLowering::getTargetNode(ExternalSymbolSDNode *N, EVT Ty,
158 SelectionDAG &DAG,
159 unsigned Flag) const {
160 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag);
161 }
162
163 SDValue MipsTargetLowering::getTargetNode(BlockAddressSDNode *N, EVT Ty,
164 SelectionDAG &DAG,
165 unsigned Flag) const {
166 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag);
167 }
168
169 SDValue MipsTargetLowering::getTargetNode(JumpTableSDNode *N, EVT Ty,
170 SelectionDAG &DAG,
171 unsigned Flag) const {
172 return DAG.getTargetJumpTable(N->getIndex(), Ty, Flag);
173 }
174
175 SDValue MipsTargetLowering::getTargetNode(ConstantPoolSDNode *N, EVT Ty,
176 SelectionDAG &DAG,
177 unsigned Flag) const {
178 return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
179 N->getOffset(), Flag);
180 }
181
182 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
183 switch ((MipsISD::NodeType)Opcode) {
184 case MipsISD::FIRST_NUMBER: break;
185 case MipsISD::JmpLink: return "MipsISD::JmpLink";
186 case MipsISD::TailCall: return "MipsISD::TailCall";
187 case MipsISD::Highest: return "MipsISD::Highest";
188 case MipsISD::Higher: return "MipsISD::Higher";
189 case MipsISD::Hi: return "MipsISD::Hi";
190 case MipsISD::Lo: return "MipsISD::Lo";
191 case MipsISD::GotHi: return "MipsISD::GotHi";
192 case MipsISD::TlsHi: return "MipsISD::TlsHi";
193 case MipsISD::GPRel: return "MipsISD::GPRel";
194 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer";
195 case MipsISD::Ret: return "MipsISD::Ret";
196 case MipsISD::ERet: return "MipsISD::ERet";
197 case MipsISD::EH_RETURN: return "MipsISD::EH_RETURN";
198 case MipsISD::FMS: return "MipsISD::FMS";
199 case MipsISD::FPBrcond: return "MipsISD::FPBrcond";
200 case MipsISD::FPCmp: return "MipsISD::FPCmp";
201 case MipsISD::FSELECT: return "MipsISD::FSELECT";
202 case MipsISD::MTC1_D64: return "MipsISD::MTC1_D64";
203 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T";
204 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F";
205 case MipsISD::TruncIntFP: return "MipsISD::TruncIntFP";
206 case MipsISD::MFHI: return "MipsISD::MFHI";
207 case MipsISD::MFLO: return "MipsISD::MFLO";
208 case MipsISD::MTLOHI: return "MipsISD::MTLOHI";
209 case MipsISD::Mult: return "MipsISD::Mult";
210 case MipsISD::Multu: return "MipsISD::Multu";
211 case MipsISD::MAdd: return "MipsISD::MAdd";
212 case MipsISD::MAddu: return "MipsISD::MAddu";
213 case MipsISD::MSub: return "MipsISD::MSub";
214 case MipsISD::MSubu: return "MipsISD::MSubu";
215 case MipsISD::DivRem: return "MipsISD::DivRem";
216 case MipsISD::DivRemU: return "MipsISD::DivRemU";
217 case MipsISD::DivRem16: return "MipsISD::DivRem16";
218 case MipsISD::DivRemU16: return "MipsISD::DivRemU16";
219 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64";
220 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
221 case MipsISD::Wrapper: return "MipsISD::Wrapper";
222 case MipsISD::DynAlloc: return "MipsISD::DynAlloc";
223 case MipsISD::Sync: return "MipsISD::Sync";
224 case MipsISD::Ext: return "MipsISD::Ext";
225 case MipsISD::Ins: return "MipsISD::Ins";
226 case MipsISD::CIns: return "MipsISD::CIns";
227 case MipsISD::LWL: return "MipsISD::LWL";
228 case MipsISD::LWR: return "MipsISD::LWR";
229 case MipsISD::SWL: return "MipsISD::SWL";
230 case MipsISD::SWR: return "MipsISD::SWR";
231 case MipsISD::LDL: return "MipsISD::LDL";
232 case MipsISD::LDR: return "MipsISD::LDR";
233 case MipsISD::SDL: return "MipsISD::SDL";
234 case MipsISD::SDR: return "MipsISD::SDR";
235 case MipsISD::EXTP: return "MipsISD::EXTP";
236 case MipsISD::EXTPDP: return "MipsISD::EXTPDP";
237 case MipsISD::EXTR_S_H: return "MipsISD::EXTR_S_H";
238 case MipsISD::EXTR_W: return "MipsISD::EXTR_W";
239 case MipsISD::EXTR_R_W: return "MipsISD::EXTR_R_W";
240 case MipsISD::EXTR_RS_W: return "MipsISD::EXTR_RS_W";
241 case MipsISD::SHILO: return "MipsISD::SHILO";
242 case MipsISD::MTHLIP: return "MipsISD::MTHLIP";
243 case MipsISD::MULSAQ_S_W_PH: return "MipsISD::MULSAQ_S_W_PH";
244 case MipsISD::MAQ_S_W_PHL: return "MipsISD::MAQ_S_W_PHL";
245 case MipsISD::MAQ_S_W_PHR: return "MipsISD::MAQ_S_W_PHR";
246 case MipsISD::MAQ_SA_W_PHL: return "MipsISD::MAQ_SA_W_PHL";
247 case MipsISD::MAQ_SA_W_PHR: return "MipsISD::MAQ_SA_W_PHR";
248 case MipsISD::DPAU_H_QBL: return "MipsISD::DPAU_H_QBL";
249 case MipsISD::DPAU_H_QBR: return "MipsISD::DPAU_H_QBR";
250 case MipsISD::DPSU_H_QBL: return "MipsISD::DPSU_H_QBL";
251 case MipsISD::DPSU_H_QBR: return "MipsISD::DPSU_H_QBR";
252 case MipsISD::DPAQ_S_W_PH: return "MipsISD::DPAQ_S_W_PH";
253 case MipsISD::DPSQ_S_W_PH: return "MipsISD::DPSQ_S_W_PH";
254 case MipsISD::DPAQ_SA_L_W: return "MipsISD::DPAQ_SA_L_W";
255 case MipsISD::DPSQ_SA_L_W: return "MipsISD::DPSQ_SA_L_W";
256 case MipsISD::DPA_W_PH: return "MipsISD::DPA_W_PH";
257 case MipsISD::DPS_W_PH: return "MipsISD::DPS_W_PH";
258 case MipsISD::DPAQX_S_W_PH: return "MipsISD::DPAQX_S_W_PH";
259 case MipsISD::DPAQX_SA_W_PH: return "MipsISD::DPAQX_SA_W_PH";
260 case MipsISD::DPAX_W_PH: return "MipsISD::DPAX_W_PH";
261 case MipsISD::DPSX_W_PH: return "MipsISD::DPSX_W_PH";
262 case MipsISD::DPSQX_S_W_PH: return "MipsISD::DPSQX_S_W_PH";
263 case MipsISD::DPSQX_SA_W_PH: return "MipsISD::DPSQX_SA_W_PH";
264 case MipsISD::MULSA_W_PH: return "MipsISD::MULSA_W_PH";
265 case MipsISD::MULT: return "MipsISD::MULT";
266 case MipsISD::MULTU: return "MipsISD::MULTU";
267 case MipsISD::MADD_DSP: return "MipsISD::MADD_DSP";
268 case MipsISD::MADDU_DSP: return "MipsISD::MADDU_DSP";
269 case MipsISD::MSUB_DSP: return "MipsISD::MSUB_DSP";
270 case MipsISD::MSUBU_DSP: return "MipsISD::MSUBU_DSP";
271 case MipsISD::SHLL_DSP: return "MipsISD::SHLL_DSP";
272 case MipsISD::SHRA_DSP: return "MipsISD::SHRA_DSP";
273 case MipsISD::SHRL_DSP: return "MipsISD::SHRL_DSP";
274 case MipsISD::SETCC_DSP: return "MipsISD::SETCC_DSP";
275 case MipsISD::SELECT_CC_DSP: return "MipsISD::SELECT_CC_DSP";
276 case MipsISD::VALL_ZERO: return "MipsISD::VALL_ZERO";
277 case MipsISD::VANY_ZERO: return "MipsISD::VANY_ZERO";
278 case MipsISD::VALL_NONZERO: return "MipsISD::VALL_NONZERO";
279 case MipsISD::VANY_NONZERO: return "MipsISD::VANY_NONZERO";
280 case MipsISD::VCEQ: return "MipsISD::VCEQ";
281 case MipsISD::VCLE_S: return "MipsISD::VCLE_S";
282 case MipsISD::VCLE_U: return "MipsISD::VCLE_U";
283 case MipsISD::VCLT_S: return "MipsISD::VCLT_S";
284 case MipsISD::VCLT_U: return "MipsISD::VCLT_U";
285 case MipsISD::VEXTRACT_SEXT_ELT: return "MipsISD::VEXTRACT_SEXT_ELT";
286 case MipsISD::VEXTRACT_ZEXT_ELT: return "MipsISD::VEXTRACT_ZEXT_ELT";
287 case MipsISD::VNOR: return "MipsISD::VNOR";
288 case MipsISD::VSHF: return "MipsISD::VSHF";
289 case MipsISD::SHF: return "MipsISD::SHF";
290 case MipsISD::ILVEV: return "MipsISD::ILVEV";
291 case MipsISD::ILVOD: return "MipsISD::ILVOD";
292 case MipsISD::ILVL: return "MipsISD::ILVL";
293 case MipsISD::ILVR: return "MipsISD::ILVR";
294 case MipsISD::PCKEV: return "MipsISD::PCKEV";
295 case MipsISD::PCKOD: return "MipsISD::PCKOD";
296 case MipsISD::INSVE: return "MipsISD::INSVE";
297 }
298 return nullptr;
299 }
300
301 MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
302 const MipsSubtarget &STI)
303 : TargetLowering(TM), Subtarget(STI), ABI(TM.getABI()) {
304 // Mips does not have i1 type, so use i32 for
305 // setcc operations results (slt, sgt, ...).
306 setBooleanContents(ZeroOrOneBooleanContent);
307 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
308 // The cmp.cond.fmt instruction in MIPS32r6/MIPS64r6 uses 0 and -1 like MSA
309 // does. Integer booleans still use 0 and 1.
310 if (Subtarget.hasMips32r6())
311 setBooleanContents(ZeroOrOneBooleanContent,
312 ZeroOrNegativeOneBooleanContent);
313
314 // Load extented operations for i1 types must be promoted
315 for (MVT VT : MVT::integer_valuetypes()) {
316 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
317 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
318 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
319 }
320
321 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
322 // for f32, f16
323 for (MVT VT : MVT::fp_valuetypes()) {
324 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
325 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
326 }
327
328 // Set LoadExtAction for f16 vectors to Expand
329 for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) {
330 MVT F16VT = MVT::getVectorVT(MVT::f16, VT.getVectorNumElements());
331 if (F16VT.isValid())
332 setLoadExtAction(ISD::EXTLOAD, VT, F16VT, Expand);
333 }
334
335 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
336 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
337
338 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
339
340 // Used by legalize types to correctly generate the setcc result.
341 // Without this, every float setcc comes with a AND/OR with the result,
342 // we don't want this, since the fpcmp result goes to a flag register,
343 // which is used implicitly by brcond and select operations.
344 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
345
346 // Mips Custom Operations
347 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
348 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
349 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
350 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
351 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
352 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
353 setOperationAction(ISD::SELECT, MVT::f32, Custom);
354 setOperationAction(ISD::SELECT, MVT::f64, Custom);
355 setOperationAction(ISD::SELECT, MVT::i32, Custom);
356 setOperationAction(ISD::SETCC, MVT::f32, Custom);
357 setOperationAction(ISD::SETCC, MVT::f64, Custom);
358 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
359 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
360 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
361 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
362
363 if (!(TM.Options.NoNaNsFPMath || Subtarget.inAbs2008Mode())) {
364 setOperationAction(ISD::FABS, MVT::f32, Custom);
365 setOperationAction(ISD::FABS, MVT::f64, Custom);
366 }
367
368 if (Subtarget.isGP64bit()) {
369 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
370 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
371 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
372 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
373 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
374 setOperationAction(ISD::SELECT, MVT::i64, Custom);
375 setOperationAction(ISD::LOAD, MVT::i64, Custom);
376 setOperationAction(ISD::STORE, MVT::i64, Custom);
377 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
378 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
379 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
380 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
381 }
382
383 if (!Subtarget.isGP64bit()) {
384 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
385 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
386 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
387 }
388
389 setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom);
390 if (Subtarget.isGP64bit())
391 setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
392
393 setOperationAction(ISD::SDIV, MVT::i32, Expand);
394 setOperationAction(ISD::SREM, MVT::i32, Expand);
395 setOperationAction(ISD::UDIV, MVT::i32, Expand);
396 setOperationAction(ISD::UREM, MVT::i32, Expand);
397 setOperationAction(ISD::SDIV, MVT::i64, Expand);
398 setOperationAction(ISD::SREM, MVT::i64, Expand);
399 setOperationAction(ISD::UDIV, MVT::i64, Expand);
400 setOperationAction(ISD::UREM, MVT::i64, Expand);
401
402 // Operations not directly supported by Mips.
403 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
404 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
405 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
406 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
407 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
408 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
409 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
410 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
411 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
412 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
413 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
414 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
415 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
416 if (Subtarget.hasCnMips()) {
417 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
418 setOperationAction(ISD::CTPOP, MVT::i64, Legal);
419 } else {
420 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
421 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
422 }
423 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
424 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
425 setOperationAction(ISD::ROTL, MVT::i32, Expand);
426 setOperationAction(ISD::ROTL, MVT::i64, Expand);
427 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
428 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
429
430 if (!Subtarget.hasMips32r2())
431 setOperationAction(ISD::ROTR, MVT::i32, Expand);
432
433 if (!Subtarget.hasMips64r2())
434 setOperationAction(ISD::ROTR, MVT::i64, Expand);
435
436 setOperationAction(ISD::FSIN, MVT::f32, Expand);
437 setOperationAction(ISD::FSIN, MVT::f64, Expand);
438 setOperationAction(ISD::FCOS, MVT::f32, Expand);
439 setOperationAction(ISD::FCOS, MVT::f64, Expand);
440 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
441 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
442 setOperationAction(ISD::FPOW, MVT::f32, Expand);
443 setOperationAction(ISD::FPOW, MVT::f64, Expand);
444 setOperationAction(ISD::FLOG, MVT::f32, Expand);
445 setOperationAction(ISD::FLOG2, MVT::f32, Expand);
446 setOperationAction(ISD::FLOG10, MVT::f32, Expand);
447 setOperationAction(ISD::FEXP, MVT::f32, Expand);
448 setOperationAction(ISD::FMA, MVT::f32, Expand);
449 setOperationAction(ISD::FMA, MVT::f64, Expand);
450 setOperationAction(ISD::FREM, MVT::f32, Expand);
451 setOperationAction(ISD::FREM, MVT::f64, Expand);
452
453 // Lower f16 conversion operations into library calls
454 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
455 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
456 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
457 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
458
459 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
460
461 setOperationAction(ISD::VASTART, MVT::Other, Custom);
462 setOperationAction(ISD::VAARG, MVT::Other, Custom);
463 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
464 setOperationAction(ISD::VAEND, MVT::Other, Expand);
465
466 // Use the default for now
467 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
468 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
469
470 if (!Subtarget.isGP64bit()) {
471 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
472 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
473 }
474
475 if (!Subtarget.hasMips32r2()) {
476 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
477 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
478 }
479
480 // MIPS16 lacks MIPS32's clz and clo instructions.
481 if (!Subtarget.hasMips32() || Subtarget.inMips16Mode())
482 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
483 if (!Subtarget.hasMips64())
484 setOperationAction(ISD::CTLZ, MVT::i64, Expand);
485
486 if (!Subtarget.hasMips32r2())
487 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
488 if (!Subtarget.hasMips64r2())
489 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
490
491 if (Subtarget.isGP64bit()) {
492 setLoadExtAction(ISD::SEXTLOAD, MVT::i64, MVT::i32, Custom);
493 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
494 setLoadExtAction(ISD::EXTLOAD, MVT::i64, MVT::i32, Custom);
495 setTruncStoreAction(MVT::i64, MVT::i32, Custom);
496 }
497
498 setOperationAction(ISD::TRAP, MVT::Other, Legal);
499
500 setTargetDAGCombine(ISD::SDIVREM);
501 setTargetDAGCombine(ISD::UDIVREM);
502 setTargetDAGCombine(ISD::SELECT);
503 setTargetDAGCombine(ISD::AND);
504 setTargetDAGCombine(ISD::OR);
505 setTargetDAGCombine(ISD::ADD);
506 setTargetDAGCombine(ISD::SUB);
507 setTargetDAGCombine(ISD::AssertZext);
508 setTargetDAGCombine(ISD::SHL);
509
510 if (ABI.IsO32()) {
511 // These libcalls are not available in 32-bit.
512 setLibcallName(RTLIB::SHL_I128, nullptr);
513 setLibcallName(RTLIB::SRL_I128, nullptr);
514 setLibcallName(RTLIB::SRA_I128, nullptr);
515 }
516
517 setMinFunctionAlignment(Subtarget.isGP64bit() ? Align(8) : Align(4));
518
519 // The arguments on the stack are defined in terms of 4-byte slots on O32
520 // and 8-byte slots on N32/N64.
521 setMinStackArgumentAlignment((ABI.IsN32() || ABI.IsN64()) ? Align(8)
522 : Align(4));
523
524 setStackPointerRegisterToSaveRestore(ABI.IsN64() ? Mips::SP_64 : Mips::SP);
525
526 MaxStoresPerMemcpy = 16;
527
528 isMicroMips = Subtarget.inMicroMipsMode();
529 }
530
531 const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM,
532 const MipsSubtarget &STI) {
533 if (STI.inMips16Mode())
534 return createMips16TargetLowering(TM, STI);
535
536 return createMipsSETargetLowering(TM, STI);
537 }
538
539 // Create a fast isel object.
540 FastISel *
541 MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
542 const TargetLibraryInfo *libInfo) const {
543 const MipsTargetMachine &TM =
544 static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget());
545
546 // We support only the standard encoding [MIPS32,MIPS32R5] ISAs.
547 bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() &&
548 !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() &&
549 !Subtarget.inMicroMipsMode();
550
551 // Disable if either of the following is true:
552 // We do not generate PIC, the ABI is not O32, XGOT is being used.
553 if (!TM.isPositionIndependent() || !TM.getABI().IsO32() ||
554 Subtarget.useXGOT())
555 UseFastISel = false;
556
557 return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr;
558 }
559
560 EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
561 EVT VT) const {
562 if (!VT.isVector())
563 return MVT::i32;
564 return VT.changeVectorElementTypeToInteger();
565 }
566
567 static SDValue performDivRemCombine(SDNode *N, SelectionDAG &DAG,
568 TargetLowering::DAGCombinerInfo &DCI,
569 const MipsSubtarget &Subtarget) {
570 if (DCI.isBeforeLegalizeOps())
571 return SDValue();
572
573 EVT Ty = N->getValueType(0);
574 unsigned LO = (Ty == MVT::i32) ? Mips::LO0 : Mips::LO0_64;
575 unsigned HI = (Ty == MVT::i32) ? Mips::HI0 : Mips::HI0_64;
576 unsigned Opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem16 :
577 MipsISD::DivRemU16;
578 SDLoc DL(N);
579
580 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue,
581 N->getOperand(0), N->getOperand(1));
582 SDValue InChain = DAG.getEntryNode();
583 SDValue InGlue = DivRem;
584
585 // insert MFLO
586 if (N->hasAnyUseOfValue(0)) {
587 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty,
588 InGlue);
589 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo);
590 InChain = CopyFromLo.getValue(1);
591 InGlue = CopyFromLo.getValue(2);
592 }
593
594 // insert MFHI
595 if (N->hasAnyUseOfValue(1)) {
596 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL,
597 HI, Ty, InGlue);
598 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi);
599 }
600
601 return SDValue();
602 }
603
604 static Mips::CondCode condCodeToFCC(ISD::CondCode CC) {
605 switch (CC) {
606 default: llvm_unreachable("Unknown fp condition code!");
607 case ISD::SETEQ:
608 case ISD::SETOEQ: return Mips::FCOND_OEQ;
609 case ISD::SETUNE: return Mips::FCOND_UNE;
610 case ISD::SETLT:
611 case ISD::SETOLT: return Mips::FCOND_OLT;
612 case ISD::SETGT:
613 case ISD::SETOGT: return Mips::FCOND_OGT;
614 case ISD::SETLE:
615 case ISD::SETOLE: return Mips::FCOND_OLE;
616 case ISD::SETGE:
617 case ISD::SETOGE: return Mips::FCOND_OGE;
618 case ISD::SETULT: return Mips::FCOND_ULT;
619 case ISD::SETULE: return Mips::FCOND_ULE;
620 case ISD::SETUGT: return Mips::FCOND_UGT;
621 case ISD::SETUGE: return Mips::FCOND_UGE;
622 case ISD::SETUO: return Mips::FCOND_UN;
623 case ISD::SETO: return Mips::FCOND_OR;
624 case ISD::SETNE:
625 case ISD::SETONE: return Mips::FCOND_ONE;
626 case ISD::SETUEQ: return Mips::FCOND_UEQ;
627 }
628 }
629
630 /// This function returns true if the floating point conditional branches and
631 /// conditional moves which use condition code CC should be inverted.
632 static bool invertFPCondCodeUser(Mips::CondCode CC) {
633 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
634 return false;
635
636 assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) &&
637 "Illegal Condition Code");
638
639 return true;
640 }
641
642 // Creates and returns an FPCmp node from a setcc node.
643 // Returns Op if setcc is not a floating point comparison.
644 static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) {
645 // must be a SETCC node
646 if (Op.getOpcode() != ISD::SETCC)
647 return Op;
648
649 SDValue LHS = Op.getOperand(0);
650
651 if (!LHS.getValueType().isFloatingPoint())
652 return Op;
653
654 SDValue RHS = Op.getOperand(1);
655 SDLoc DL(Op);
656
657 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of
658 // node if necessary.
659 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
660
661 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS,
662 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32));
663 }
664
665 // Creates and returns a CMovFPT/F node.
666 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
667 SDValue False, const SDLoc &DL) {
668 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
669 bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
670 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
671
672 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL,
673 True.getValueType(), True, FCC0, False, Cond);
674 }
675
676 static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
677 TargetLowering::DAGCombinerInfo &DCI,
678 const MipsSubtarget &Subtarget) {
679 if (DCI.isBeforeLegalizeOps())
680 return SDValue();
681
682 SDValue SetCC = N->getOperand(0);
683
684 if ((SetCC.getOpcode() != ISD::SETCC) ||
685 !SetCC.getOperand(0).getValueType().isInteger())
686 return SDValue();
687
688 SDValue False = N->getOperand(2);
689 EVT FalseTy = False.getValueType();
690
691 if (!FalseTy.isInteger())
692 return SDValue();
693
694 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
695
696 // If the RHS (False) is 0, we swap the order of the operands
697 // of ISD::SELECT (obviously also inverting the condition) so that we can
698 // take advantage of conditional moves using the $0 register.
699 // Example:
700 // return (a != 0) ? x : 0;
701 // load $reg, x
702 // movz $reg, $0, a
703 if (!FalseC)
704 return SDValue();
705
706 const SDLoc DL(N);
707
708 if (!FalseC->getZExtValue()) {
709 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
710 SDValue True = N->getOperand(1);
711
712 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
713 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
714
715 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
716 }
717
718 // If both operands are integer constants there's a possibility that we
719 // can do some interesting optimizations.
720 SDValue True = N->getOperand(1);
721 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
722
723 if (!TrueC || !True.getValueType().isInteger())
724 return SDValue();
725
726 // We'll also ignore MVT::i64 operands as this optimizations proves
727 // to be ineffective because of the required sign extensions as the result
728 // of a SETCC operator is always MVT::i32 for non-vector types.
729 if (True.getValueType() == MVT::i64)
730 return SDValue();
731
732 int64_t Diff = TrueC->getSExtValue() - FalseC->getSExtValue();
733
734 // 1) (a < x) ? y : y-1
735 // slti $reg1, a, x
736 // addiu $reg2, $reg1, y-1
737 if (Diff == 1)
738 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
739
740 // 2) (a < x) ? y-1 : y
741 // slti $reg1, a, x
742 // xor $reg1, $reg1, 1
743 // addiu $reg2, $reg1, y-1
744 if (Diff == -1) {
745 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
746 SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
747 SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
748 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, True);
749 }
750
751 // Could not optimize.
752 return SDValue();
753 }
754
755 static SDValue performCMovFPCombine(SDNode *N, SelectionDAG &DAG,
756 TargetLowering::DAGCombinerInfo &DCI,
757 const MipsSubtarget &Subtarget) {
758 if (DCI.isBeforeLegalizeOps())
759 return SDValue();
760
761 SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
762
763 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
764 if (!FalseC || FalseC->getZExtValue())
765 return SDValue();
766
767 // Since RHS (False) is 0, we swap the order of the True/False operands
768 // (obviously also inverting the condition) so that we can
769 // take advantage of conditional moves using the $0 register.
770 // Example:
771 // return (a != 0) ? x : 0;
772 // load $reg, x
773 // movz $reg, $0, a
774 unsigned Opc = (N->getOpcode() == MipsISD::CMovFP_T) ? MipsISD::CMovFP_F :
775 MipsISD::CMovFP_T;
776
777 SDValue FCC = N->getOperand(1), Glue = N->getOperand(3);
778 return DAG.getNode(Opc, SDLoc(N), ValueIfFalse.getValueType(),
779 ValueIfFalse, FCC, ValueIfTrue, Glue);
780 }
781
782 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
783 TargetLowering::DAGCombinerInfo &DCI,
784 const MipsSubtarget &Subtarget) {
785 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
786 return SDValue();
787
788 SDValue FirstOperand = N->getOperand(0);
789 unsigned FirstOperandOpc = FirstOperand.getOpcode();
790 SDValue Mask = N->getOperand(1);
791 EVT ValTy = N->getValueType(0);
792 SDLoc DL(N);
793
794 uint64_t Pos = 0, SMPos, SMSize;
795 ConstantSDNode *CN;
796 SDValue NewOperand;
797 unsigned Opc;
798
799 // Op's second operand must be a shifted mask.
800 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
801 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
802 return SDValue();
803
804 if (FirstOperandOpc == ISD::SRA || FirstOperandOpc == ISD::SRL) {
805 // Pattern match EXT.
806 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
807 // => ext $dst, $src, pos, size
808
809 // The second operand of the shift must be an immediate.
810 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
811 return SDValue();
812
813 Pos = CN->getZExtValue();
814
815 // Return if the shifted mask does not start at bit 0 or the sum of its size
816 // and Pos exceeds the word's size.
817 if (SMPos != 0 || Pos + SMSize > ValTy.getSizeInBits())
818 return SDValue();
819
820 Opc = MipsISD::Ext;
821 NewOperand = FirstOperand.getOperand(0);
822 } else if (FirstOperandOpc == ISD::SHL && Subtarget.hasCnMips()) {
823 // Pattern match CINS.
824 // $dst = and (shl $src , pos), mask
825 // => cins $dst, $src, pos, size
826 // mask is a shifted mask with consecutive 1's, pos = shift amount,
827 // size = population count.
828
829 // The second operand of the shift must be an immediate.
830 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))))
831 return SDValue();
832
833 Pos = CN->getZExtValue();
834
835 if (SMPos != Pos || Pos >= ValTy.getSizeInBits() || SMSize >= 32 ||
836 Pos + SMSize > ValTy.getSizeInBits())
837 return SDValue();
838
839 NewOperand = FirstOperand.getOperand(0);
840 // SMSize is 'location' (position) in this case, not size.
841 SMSize--;
842 Opc = MipsISD::CIns;
843 } else {
844 // Pattern match EXT.
845 // $dst = and $src, (2**size - 1) , if size > 16
846 // => ext $dst, $src, pos, size , pos = 0
847
848 // If the mask is <= 0xffff, andi can be used instead.
849 if (CN->getZExtValue() <= 0xffff)
850 return SDValue();
851
852 // Return if the mask doesn't start at position 0.
853 if (SMPos)
854 return SDValue();
855
856 Opc = MipsISD::Ext;
857 NewOperand = FirstOperand;
858 }
859 return DAG.getNode(Opc, DL, ValTy, NewOperand,
860 DAG.getConstant(Pos, DL, MVT::i32),
861 DAG.getConstant(SMSize, DL, MVT::i32));
862 }
863
864 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
865 TargetLowering::DAGCombinerInfo &DCI,
866 const MipsSubtarget &Subtarget) {
867 // Pattern match INS.
868 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
869 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1
870 // => ins $dst, $src, size, pos, $src1
871 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert())
872 return SDValue();
873
874 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
875 uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
876 ConstantSDNode *CN, *CN1;
877
878 // See if Op's first operand matches (and $src1 , mask0).
879 if (And0.getOpcode() != ISD::AND)
880 return SDValue();
881
882 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
883 !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
884 return SDValue();
885
886 // See if Op's second operand matches (and (shl $src, pos), mask1).
887 if (And1.getOpcode() == ISD::AND &&
888 And1.getOperand(0).getOpcode() == ISD::SHL) {
889
890 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
891 !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
892 return SDValue();
893
894 // The shift masks must have the same position and size.
895 if (SMPos0 != SMPos1 || SMSize0 != SMSize1)
896 return SDValue();
897
898 SDValue Shl = And1.getOperand(0);
899
900 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
901 return SDValue();
902
903 unsigned Shamt = CN->getZExtValue();
904
905 // Return if the shift amount and the first bit position of mask are not the
906 // same.
907 EVT ValTy = N->getValueType(0);
908 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
909 return SDValue();
910
911 SDLoc DL(N);
912 return DAG.getNode(MipsISD::Ins, DL, ValTy, Shl.getOperand(0),
913 DAG.getConstant(SMPos0, DL, MVT::i32),
914 DAG.getConstant(SMSize0, DL, MVT::i32),
915 And0.getOperand(0));
916 } else {
917 // Pattern match DINS.
918 // $dst = or (and $src, mask0), mask1
919 // where mask0 = ((1 << SMSize0) -1) << SMPos0
920 // => dins $dst, $src, pos, size
921 if (~CN->getSExtValue() == ((((int64_t)1 << SMSize0) - 1) << SMPos0) &&
922 ((SMSize0 + SMPos0 <= 64 && Subtarget.hasMips64r2()) ||
923 (SMSize0 + SMPos0 <= 32))) {
924 // Check if AND instruction has constant as argument
925 bool isConstCase = And1.getOpcode() != ISD::AND;
926 if (And1.getOpcode() == ISD::AND) {
927 if (!(CN1 = dyn_cast<ConstantSDNode>(And1->getOperand(1))))
928 return SDValue();
929 } else {
930 if (!(CN1 = dyn_cast<ConstantSDNode>(N->getOperand(1))))
931 return SDValue();
932 }
933 // Don't generate INS if constant OR operand doesn't fit into bits
934 // cleared by constant AND operand.
935 if (CN->getSExtValue() & CN1->getSExtValue())
936 return SDValue();
937
938 SDLoc DL(N);
939 EVT ValTy = N->getOperand(0)->getValueType(0);
940 SDValue Const1;
941 SDValue SrlX;
942 if (!isConstCase) {
943 Const1 = DAG.getConstant(SMPos0, DL, MVT::i32);
944 SrlX = DAG.getNode(ISD::SRL, DL, And1->getValueType(0), And1, Const1);
945 }
946 return DAG.getNode(
947 MipsISD::Ins, DL, N->getValueType(0),
948 isConstCase
949 ? DAG.getConstant(CN1->getSExtValue() >> SMPos0, DL, ValTy)
950 : SrlX,
951 DAG.getConstant(SMPos0, DL, MVT::i32),
952 DAG.getConstant(ValTy.getSizeInBits() / 8 < 8 ? SMSize0 & 31
953 : SMSize0,
954 DL, MVT::i32),
955 And0->getOperand(0));
956
957 }
958 return SDValue();
959 }
960 }
961
962 static SDValue performMADD_MSUBCombine(SDNode *ROOTNode, SelectionDAG &CurDAG,
963 const MipsSubtarget &Subtarget) {
964 // ROOTNode must have a multiplication as an operand for the match to be
965 // successful.
966 if (ROOTNode->getOperand(0).getOpcode() != ISD::MUL &&
967 ROOTNode->getOperand(1).getOpcode() != ISD::MUL)
968 return SDValue();
969
970 // We don't handle vector types here.
971 if (ROOTNode->getValueType(0).isVector())
972 return SDValue();
973
974 // For MIPS64, madd / msub instructions are inefficent to use with 64 bit
975 // arithmetic. E.g.
976 // (add (mul a b) c) =>
977 // let res = (madd (mthi (drotr c 32))x(mtlo c) a b) in
978 // MIPS64: (or (dsll (mfhi res) 32) (dsrl (dsll (mflo res) 32) 32)
979 // or
980 // MIPS64R2: (dins (mflo res) (mfhi res) 32 32)
981 //
982 // The overhead of setting up the Hi/Lo registers and reassembling the
983 // result makes this a dubious optimzation for MIPS64. The core of the
984 // problem is that Hi/Lo contain the upper and lower 32 bits of the
985 // operand and result.
986 //
987 // It requires a chain of 4 add/mul for MIPS64R2 to get better code
988 // density than doing it naively, 5 for MIPS64. Additionally, using
989 // madd/msub on MIPS64 requires the operands actually be 32 bit sign
990 // extended operands, not true 64 bit values.
991 //
992 // FIXME: For the moment, disable this completely for MIPS64.
993 if (Subtarget.hasMips64())
994 return SDValue();
995
996 SDValue Mult = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
997 ? ROOTNode->getOperand(0)
998 : ROOTNode->getOperand(1);
999
1000 SDValue AddOperand = ROOTNode->getOperand(0).getOpcode() == ISD::MUL
1001 ? ROOTNode->getOperand(1)
1002 : ROOTNode->getOperand(0);
1003
1004 // Transform this to a MADD only if the user of this node is the add.
1005 // If there are other users of the mul, this function returns here.
1006 if (!Mult.hasOneUse())
1007 return SDValue();
1008
1009 // maddu and madd are unusual instructions in that on MIPS64 bits 63..31
1010 // must be in canonical form, i.e. sign extended. For MIPS32, the operands
1011 // of the multiply must have 32 or more sign bits, otherwise we cannot
1012 // perform this optimization. We have to check this here as we're performing
1013 // this optimization pre-legalization.
1014 SDValue MultLHS = Mult->getOperand(0);
1015 SDValue MultRHS = Mult->getOperand(1);
1016
1017 bool IsSigned = MultLHS->getOpcode() == ISD::SIGN_EXTEND &&
1018 MultRHS->getOpcode() == ISD::SIGN_EXTEND;
1019 bool IsUnsigned = MultLHS->getOpcode() == ISD::ZERO_EXTEND &&
1020 MultRHS->getOpcode() == ISD::ZERO_EXTEND;
1021
1022 if (!IsSigned && !IsUnsigned)
1023 return SDValue();
1024
1025 // Initialize accumulator.
1026 SDLoc DL(ROOTNode);
1027 SDValue TopHalf;
1028 SDValue BottomHalf;
1029 BottomHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1030 CurDAG.getIntPtrConstant(0, DL));
1031
1032 TopHalf = CurDAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, AddOperand,
1033 CurDAG.getIntPtrConstant(1, DL));
1034 SDValue ACCIn = CurDAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
1035 BottomHalf,
1036 TopHalf);
1037
1038 // Create MipsMAdd(u) / MipsMSub(u) node.
1039 bool IsAdd = ROOTNode->getOpcode() == ISD::ADD;
1040 unsigned Opcode = IsAdd ? (IsUnsigned ? MipsISD::MAddu : MipsISD::MAdd)
1041 : (IsUnsigned ? MipsISD::MSubu : MipsISD::MSub);
1042 SDValue MAddOps[3] = {
1043 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(0)),
1044 CurDAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mult->getOperand(1)), ACCIn};
1045 EVT VTs[2] = {MVT::i32, MVT::i32};
1046 SDValue MAdd = CurDAG.getNode(Opcode, DL, VTs, MAddOps);
1047
1048 SDValue ResLo = CurDAG.getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
1049 SDValue ResHi = CurDAG.getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
1050 SDValue Combined =
1051 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi);
1052 return Combined;
1053 }
1054
1055 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
1056 TargetLowering::DAGCombinerInfo &DCI,
1057 const MipsSubtarget &Subtarget) {
1058 // (sub v0 (mul v1, v2)) => (msub v1, v2, v0)
1059 if (DCI.isBeforeLegalizeOps()) {
1060 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1061 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1062 return performMADD_MSUBCombine(N, DAG, Subtarget);
1063
1064 return SDValue();
1065 }
1066
1067 return SDValue();
1068 }
1069
1070 static SDValue performADDCombine(SDNode *N, SelectionDAG &DAG,
1071 TargetLowering::DAGCombinerInfo &DCI,
1072 const MipsSubtarget &Subtarget) {
1073 // (add v0 (mul v1, v2)) => (madd v1, v2, v0)
1074 if (DCI.isBeforeLegalizeOps()) {
1075 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
1076 !Subtarget.inMips16Mode() && N->getValueType(0) == MVT::i64)
1077 return performMADD_MSUBCombine(N, DAG, Subtarget);
1078
1079 return SDValue();
1080 }
1081
1082 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
1083 SDValue Add = N->getOperand(1);
1084
1085 if (Add.getOpcode() != ISD::ADD)
1086 return SDValue();
1087
1088 SDValue Lo = Add.getOperand(1);
1089
1090 if ((Lo.getOpcode() != MipsISD::Lo) ||
1091 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable))
1092 return SDValue();
1093
1094 EVT ValTy = N->getValueType(0);
1095 SDLoc DL(N);
1096
1097 SDValue Add1 = DAG.getNode(ISD::ADD, DL, ValTy, N->getOperand(0),
1098 Add.getOperand(0));
1099 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo);
1100 }
1101
1102 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
1103 TargetLowering::DAGCombinerInfo &DCI,
1104 const MipsSubtarget &Subtarget) {
1105 // Pattern match CINS.
1106 // $dst = shl (and $src , imm), pos
1107 // => cins $dst, $src, pos, size
1108
1109 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips())
1110 return SDValue();
1111
1112 SDValue FirstOperand = N->getOperand(0);
1113 unsigned FirstOperandOpc = FirstOperand.getOpcode();
1114 SDValue SecondOperand = N->getOperand(1);
1115 EVT ValTy = N->getValueType(0);
1116 SDLoc DL(N);
1117
1118 uint64_t Pos = 0, SMPos, SMSize;
1119 ConstantSDNode *CN;
1120 SDValue NewOperand;
1121
1122 // The second operand of the shift must be an immediate.
1123 if (!(CN = dyn_cast<ConstantSDNode>(SecondOperand)))
1124 return SDValue();
1125
1126 Pos = CN->getZExtValue();
1127
1128 if (Pos >= ValTy.getSizeInBits())
1129 return SDValue();
1130
1131 if (FirstOperandOpc != ISD::AND)
1132 return SDValue();
1133
1134 // AND's second operand must be a shifted mask.
1135 if (!(CN = dyn_cast<ConstantSDNode>(FirstOperand.getOperand(1))) ||
1136 !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
1137 return SDValue();
1138
1139 // Return if the shifted mask does not start at bit 0 or the sum of its size
1140 // and Pos exceeds the word's size.
1141 if (SMPos != 0 || SMSize > 32 || Pos + SMSize > ValTy.getSizeInBits())
1142 return SDValue();
1143
1144 NewOperand = FirstOperand.getOperand(0);
1145 // SMSize is 'location' (position) in this case, not size.
1146 SMSize--;
1147
1148 return DAG.getNode(MipsISD::CIns, DL, ValTy, NewOperand,
1149 DAG.getConstant(Pos, DL, MVT::i32),
1150 DAG.getConstant(SMSize, DL, MVT::i32));
1151 }
1152
1153 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
1154 const {
1155 SelectionDAG &DAG = DCI.DAG;
1156 unsigned Opc = N->getOpcode();
1157
1158 switch (Opc) {
1159 default: break;
1160 case ISD::SDIVREM:
1161 case ISD::UDIVREM:
1162 return performDivRemCombine(N, DAG, DCI, Subtarget);
1163 case ISD::SELECT:
1164 return performSELECTCombine(N, DAG, DCI, Subtarget);
1165 case MipsISD::CMovFP_F:
1166 case MipsISD::CMovFP_T:
1167 return performCMovFPCombine(N, DAG, DCI, Subtarget);
1168 case ISD::AND:
1169 return performANDCombine(N, DAG, DCI, Subtarget);
1170 case ISD::OR:
1171 return performORCombine(N, DAG, DCI, Subtarget);
1172 case ISD::ADD:
1173 return performADDCombine(N, DAG, DCI, Subtarget);
1174 case ISD::SHL:
1175 return performSHLCombine(N, DAG, DCI, Subtarget);
1176 case ISD::SUB:
1177 return performSUBCombine(N, DAG, DCI, Subtarget);
1178 }
1179
1180 return SDValue();
1181 }
1182
1183 bool MipsTargetLowering::isCheapToSpeculateCttz() const {
1184 return Subtarget.hasMips32();
1185 }
1186
1187 bool MipsTargetLowering::isCheapToSpeculateCtlz() const {
1188 return Subtarget.hasMips32();
1189 }
1190
1191 bool MipsTargetLowering::shouldFoldConstantShiftPairToMask(
1192 const SDNode *N, CombineLevel Level) const {
1193 if (N->getOperand(0).getValueType().isVector())
1194 return false;
1195 return true;
1196 }
1197
1198 void
1199 MipsTargetLowering::LowerOperationWrapper(SDNode *N,
1200 SmallVectorImpl<SDValue> &Results,
1201 SelectionDAG &DAG) const {
1202 SDValue Res = LowerOperation(SDValue(N, 0), DAG);
1203
1204 if (Res)
1205 for (unsigned I = 0, E = Res->getNumValues(); I != E; ++I)
1206 Results.push_back(Res.getValue(I));
1207 }
1208
1209 void
1210 MipsTargetLowering::ReplaceNodeResults(SDNode *N,
1211 SmallVectorImpl<SDValue> &Results,
1212 SelectionDAG &DAG) const {
1213 return LowerOperationWrapper(N, Results, DAG);
1214 }
1215
1216 SDValue MipsTargetLowering::
1217 LowerOperation(SDValue Op, SelectionDAG &DAG) const
1218 {
1219 switch (Op.getOpcode())
1220 {
1221 case ISD::BRCOND: return lowerBRCOND(Op, DAG);
1222 case ISD::ConstantPool: return lowerConstantPool(Op, DAG);
1223 case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG);
1224 case ISD::BlockAddress: return lowerBlockAddress(Op, DAG);
1225 case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG);
1226 case ISD::JumpTable: return lowerJumpTable(Op, DAG);
1227 case ISD::SELECT: return lowerSELECT(Op, DAG);
1228 case ISD::SETCC: return lowerSETCC(Op, DAG);
1229 case ISD::VASTART: return lowerVASTART(Op, DAG);
1230 case ISD::VAARG: return lowerVAARG(Op, DAG);
1231 case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG);
1232 case ISD::FABS: return lowerFABS(Op, DAG);
1233 case ISD::FRAMEADDR: return lowerFRAMEADDR(Op, DAG);
1234 case ISD::RETURNADDR: return lowerRETURNADDR(Op, DAG);
1235 case ISD::EH_RETURN: return lowerEH_RETURN(Op, DAG);
1236 case ISD::ATOMIC_FENCE: return lowerATOMIC_FENCE(Op, DAG);
1237 case ISD::SHL_PARTS: return lowerShiftLeftParts(Op, DAG);
1238 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
1239 case ISD::SRL_PARTS: return lowerShiftRightParts(Op, DAG, false);
1240 case ISD::LOAD: return lowerLOAD(Op, DAG);
1241 case ISD::STORE: return lowerSTORE(Op, DAG);
1242 case ISD::EH_DWARF_CFA: return lowerEH_DWARF_CFA(Op, DAG);
1243 case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
1244 }
1245 return SDValue();
1246 }
1247
1248 //===----------------------------------------------------------------------===//
1249 // Lower helper functions
1250 //===----------------------------------------------------------------------===//
1251
1252 // addLiveIn - This helper function adds the specified physical register to the
1253 // MachineFunction as a live in value. It also creates a corresponding
1254 // virtual register for it.
1255 static unsigned
1256 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1257 {
1258 Register VReg = MF.getRegInfo().createVirtualRegister(RC);
1259 MF.getRegInfo().addLiveIn(PReg, VReg);
1260 return VReg;
1261 }
1262
1263 static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
1264 MachineBasicBlock &MBB,
1265 const TargetInstrInfo &TII,
1266 bool Is64Bit, bool IsMicroMips) {
1267 if (NoZeroDivCheck)
1268 return &MBB;
1269
1270 // Insert instruction "teq $divisor_reg, $zero, 7".
1271 MachineBasicBlock::iterator I(MI);
1272 MachineInstrBuilder MIB;
1273 MachineOperand &Divisor = MI.getOperand(2);
1274 MIB = BuildMI(MBB, std::next(I), MI.getDebugLoc(),
1275 TII.get(IsMicroMips ? Mips::TEQ_MM : Mips::TEQ))
1276 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1277 .addReg(Mips::ZERO)
1278 .addImm(7);
1279
1280 // Use the 32-bit sub-register if this is a 64-bit division.
1281 if (Is64Bit)
1282 MIB->getOperand(0).setSubReg(Mips::sub_32);
1283
1284 // Clear Divisor's kill flag.
1285 Divisor.setIsKill(false);
1286
1287 // We would normally delete the original instruction here but in this case
1288 // we only needed to inject an additional instruction rather than replace it.
1289
1290 return &MBB;
1291 }
1292
1293 MachineBasicBlock *
1294 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
1295 MachineBasicBlock *BB) const {
1296 switch (MI.getOpcode()) {
1297 default:
1298 llvm_unreachable("Unexpected instr type to insert");
1299 case Mips::ATOMIC_LOAD_ADD_I8:
1300 return emitAtomicBinaryPartword(MI, BB, 1);
1301 case Mips::ATOMIC_LOAD_ADD_I16:
1302 return emitAtomicBinaryPartword(MI, BB, 2);
1303 case Mips::ATOMIC_LOAD_ADD_I32:
1304 return emitAtomicBinary(MI, BB);
1305 case Mips::ATOMIC_LOAD_ADD_I64:
1306 return emitAtomicBinary(MI, BB);
1307
1308 case Mips::ATOMIC_LOAD_AND_I8:
1309 return emitAtomicBinaryPartword(MI, BB, 1);
1310 case Mips::ATOMIC_LOAD_AND_I16:
1311 return emitAtomicBinaryPartword(MI, BB, 2);
1312 case Mips::ATOMIC_LOAD_AND_I32:
1313 return emitAtomicBinary(MI, BB);
1314 case Mips::ATOMIC_LOAD_AND_I64:
1315 return emitAtomicBinary(MI, BB);
1316
1317 case Mips::ATOMIC_LOAD_OR_I8:
1318 return emitAtomicBinaryPartword(MI, BB, 1);
1319 case Mips::ATOMIC_LOAD_OR_I16:
1320 return emitAtomicBinaryPartword(MI, BB, 2);
1321 case Mips::ATOMIC_LOAD_OR_I32:
1322 return emitAtomicBinary(MI, BB);
1323 case Mips::ATOMIC_LOAD_OR_I64:
1324 return emitAtomicBinary(MI, BB);
1325
1326 case Mips::ATOMIC_LOAD_XOR_I8:
1327 return emitAtomicBinaryPartword(MI, BB, 1);
1328 case Mips::ATOMIC_LOAD_XOR_I16:
1329 return emitAtomicBinaryPartword(MI, BB, 2);
1330 case Mips::ATOMIC_LOAD_XOR_I32:
1331 return emitAtomicBinary(MI, BB);
1332 case Mips::ATOMIC_LOAD_XOR_I64:
1333 return emitAtomicBinary(MI, BB);
1334
1335 case Mips::ATOMIC_LOAD_NAND_I8:
1336 return emitAtomicBinaryPartword(MI, BB, 1);
1337 case Mips::ATOMIC_LOAD_NAND_I16:
1338 return emitAtomicBinaryPartword(MI, BB, 2);
1339 case Mips::ATOMIC_LOAD_NAND_I32:
1340 return emitAtomicBinary(MI, BB);
1341 case Mips::ATOMIC_LOAD_NAND_I64:
1342 return emitAtomicBinary(MI, BB);
1343
1344 case Mips::ATOMIC_LOAD_SUB_I8:
1345 return emitAtomicBinaryPartword(MI, BB, 1);
1346 case Mips::ATOMIC_LOAD_SUB_I16:
1347 return emitAtomicBinaryPartword(MI, BB, 2);
1348 case Mips::ATOMIC_LOAD_SUB_I32:
1349 return emitAtomicBinary(MI, BB);
1350 case Mips::ATOMIC_LOAD_SUB_I64:
1351 return emitAtomicBinary(MI, BB);
1352
1353 case Mips::ATOMIC_SWAP_I8:
1354 return emitAtomicBinaryPartword(MI, BB, 1);
1355 case Mips::ATOMIC_SWAP_I16:
1356 return emitAtomicBinaryPartword(MI, BB, 2);
1357 case Mips::ATOMIC_SWAP_I32:
1358 return emitAtomicBinary(MI, BB);
1359 case Mips::ATOMIC_SWAP_I64:
1360 return emitAtomicBinary(MI, BB);
1361
1362 case Mips::ATOMIC_CMP_SWAP_I8:
1363 return emitAtomicCmpSwapPartword(MI, BB, 1);
1364 case Mips::ATOMIC_CMP_SWAP_I16:
1365 return emitAtomicCmpSwapPartword(MI, BB, 2);
1366 case Mips::ATOMIC_CMP_SWAP_I32:
1367 return emitAtomicCmpSwap(MI, BB);
1368 case Mips::ATOMIC_CMP_SWAP_I64:
1369 return emitAtomicCmpSwap(MI, BB);
1370 case Mips::PseudoSDIV:
1371 case Mips::PseudoUDIV:
1372 case Mips::DIV:
1373 case Mips::DIVU:
1374 case Mips::MOD:
1375 case Mips::MODU:
1376 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false,
1377 false);
1378 case Mips::SDIV_MM_Pseudo:
1379 case Mips::UDIV_MM_Pseudo:
1380 case Mips::SDIV_MM:
1381 case Mips::UDIV_MM:
1382 case Mips::DIV_MMR6:
1383 case Mips::DIVU_MMR6:
1384 case Mips::MOD_MMR6:
1385 case Mips::MODU_MMR6:
1386 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), false, true);
1387 case Mips::PseudoDSDIV:
1388 case Mips::PseudoDUDIV:
1389 case Mips::DDIV:
1390 case Mips::DDIVU:
1391 case Mips::DMOD:
1392 case Mips::DMODU:
1393 return insertDivByZeroTrap(MI, *BB, *Subtarget.getInstrInfo(), true, false);
1394
1395 case Mips::PseudoSELECT_I:
1396 case Mips::PseudoSELECT_I64:
1397 case Mips::PseudoSELECT_S:
1398 case Mips::PseudoSELECT_D32:
1399 case Mips::PseudoSELECT_D64:
1400 return emitPseudoSELECT(MI, BB, false, Mips::BNE);
1401 case Mips::PseudoSELECTFP_F_I:
1402 case Mips::PseudoSELECTFP_F_I64:
1403 case Mips::PseudoSELECTFP_F_S:
1404 case Mips::PseudoSELECTFP_F_D32:
1405 case Mips::PseudoSELECTFP_F_D64:
1406 return emitPseudoSELECT(MI, BB, true, Mips::BC1F);
1407 case Mips::PseudoSELECTFP_T_I:
1408 case Mips::PseudoSELECTFP_T_I64:
1409 case Mips::PseudoSELECTFP_T_S:
1410 case Mips::PseudoSELECTFP_T_D32:
1411 case Mips::PseudoSELECTFP_T_D64:
1412 return emitPseudoSELECT(MI, BB, true, Mips::BC1T);
1413 case Mips::PseudoD_SELECT_I:
1414 case Mips::PseudoD_SELECT_I64:
1415 return emitPseudoD_SELECT(MI, BB);
1416 }
1417 }
1418
1419 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and
1420 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true)
1421 MachineBasicBlock *
1422 MipsTargetLowering::emitAtomicBinary(MachineInstr &MI,
1423 MachineBasicBlock *BB) const {
1424
1425 MachineFunction *MF = BB->getParent();
1426 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1427 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1428 DebugLoc DL = MI.getDebugLoc();
1429
1430 unsigned AtomicOp;
1431 switch (MI.getOpcode()) {
1432 case Mips::ATOMIC_LOAD_ADD_I32:
1433 AtomicOp = Mips::ATOMIC_LOAD_ADD_I32_POSTRA;
1434 break;
1435 case Mips::ATOMIC_LOAD_SUB_I32:
1436 AtomicOp = Mips::ATOMIC_LOAD_SUB_I32_POSTRA;
1437 break;
1438 case Mips::ATOMIC_LOAD_AND_I32:
1439 AtomicOp = Mips::ATOMIC_LOAD_AND_I32_POSTRA;
1440 break;
1441 case Mips::ATOMIC_LOAD_OR_I32:
1442 AtomicOp = Mips::ATOMIC_LOAD_OR_I32_POSTRA;
1443 break;
1444 case Mips::ATOMIC_LOAD_XOR_I32:
1445 AtomicOp = Mips::ATOMIC_LOAD_XOR_I32_POSTRA;
1446 break;
1447 case Mips::ATOMIC_LOAD_NAND_I32:
1448 AtomicOp = Mips::ATOMIC_LOAD_NAND_I32_POSTRA;
1449 break;
1450 case Mips::ATOMIC_SWAP_I32:
1451 AtomicOp = Mips::ATOMIC_SWAP_I32_POSTRA;
1452 break;
1453 case Mips::ATOMIC_LOAD_ADD_I64:
1454 AtomicOp = Mips::ATOMIC_LOAD_ADD_I64_POSTRA;
1455 break;
1456 case Mips::ATOMIC_LOAD_SUB_I64:
1457 AtomicOp = Mips::ATOMIC_LOAD_SUB_I64_POSTRA;
1458 break;
1459 case Mips::ATOMIC_LOAD_AND_I64:
1460 AtomicOp = Mips::ATOMIC_LOAD_AND_I64_POSTRA;
1461 break;
1462 case Mips::ATOMIC_LOAD_OR_I64:
1463 AtomicOp = Mips::ATOMIC_LOAD_OR_I64_POSTRA;
1464 break;
1465 case Mips::ATOMIC_LOAD_XOR_I64:
1466 AtomicOp = Mips::ATOMIC_LOAD_XOR_I64_POSTRA;
1467 break;
1468 case Mips::ATOMIC_LOAD_NAND_I64:
1469 AtomicOp = Mips::ATOMIC_LOAD_NAND_I64_POSTRA;
1470 break;
1471 case Mips::ATOMIC_SWAP_I64:
1472 AtomicOp = Mips::ATOMIC_SWAP_I64_POSTRA;
1473 break;
1474 default:
1475 llvm_unreachable("Unknown pseudo atomic for replacement!");
1476 }
1477
1478 Register OldVal = MI.getOperand(0).getReg();
1479 Register Ptr = MI.getOperand(1).getReg();
1480 Register Incr = MI.getOperand(2).getReg();
1481 Register Scratch = RegInfo.createVirtualRegister(RegInfo.getRegClass(OldVal));
1482
1483 MachineBasicBlock::iterator II(MI);
1484
1485 // The scratch registers here with the EarlyClobber | Define | Implicit
1486 // flags is used to persuade the register allocator and the machine
1487 // verifier to accept the usage of this register. This has to be a real
1488 // register which has an UNDEF value but is dead after the instruction which
1489 // is unique among the registers chosen for the instruction.
1490
1491 // The EarlyClobber flag has the semantic properties that the operand it is
1492 // attached to is clobbered before the rest of the inputs are read. Hence it
1493 // must be unique among the operands to the instruction.
1494 // The Define flag is needed to coerce the machine verifier that an Undef
1495 // value isn't a problem.
1496 // The Dead flag is needed as the value in scratch isn't used by any other
1497 // instruction. Kill isn't used as Dead is more precise.
1498 // The implicit flag is here due to the interaction between the other flags
1499 // and the machine verifier.
1500
1501 // For correctness purpose, a new pseudo is introduced here. We need this
1502 // new pseudo, so that FastRegisterAllocator does not see an ll/sc sequence
1503 // that is spread over >1 basic blocks. A register allocator which
1504 // introduces (or any codegen infact) a store, can violate the expectations
1505 // of the hardware.
1506 //
1507 // An atomic read-modify-write sequence starts with a linked load
1508 // instruction and ends with a store conditional instruction. The atomic
1509 // read-modify-write sequence fails if any of the following conditions
1510 // occur between the execution of ll and sc:
1511 // * A coherent store is completed by another process or coherent I/O
1512 // module into the block of synchronizable physical memory containing
1513 // the word. The size and alignment of the block is
1514 // implementation-dependent.
1515 // * A coherent store is executed between an LL and SC sequence on the
1516 // same processor to the block of synchornizable physical memory
1517 // containing the word.
1518 //
1519
1520 Register PtrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Ptr));
1521 Register IncrCopy = RegInfo.createVirtualRegister(RegInfo.getRegClass(Incr));
1522
1523 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1524 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1525
1526 BuildMI(*BB, II, DL, TII->get(AtomicOp))
1527 .addReg(OldVal, RegState::Define | RegState::EarlyClobber)
1528 .addReg(PtrCopy)
1529 .addReg(IncrCopy)
1530 .addReg(Scratch, RegState::Define | RegState::EarlyClobber |
1531 RegState::Implicit | RegState::Dead);
1532
1533 MI.eraseFromParent();
1534
1535 return BB;
1536 }
1537
1538 MachineBasicBlock *MipsTargetLowering::emitSignExtendToI32InReg(
1539 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size, unsigned DstReg,
1540 unsigned SrcReg) const {
1541 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1542 const DebugLoc &DL = MI.getDebugLoc();
1543
1544 if (Subtarget.hasMips32r2() && Size == 1) {
1545 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1546 return BB;
1547 }
1548
1549 if (Subtarget.hasMips32r2() && Size == 2) {
1550 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1551 return BB;
1552 }
1553
1554 MachineFunction *MF = BB->getParent();
1555 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1556 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1557 Register ScrReg = RegInfo.createVirtualRegister(RC);
1558
1559 assert(Size < 32);
1560 int64_t ShiftImm = 32 - (Size * 8);
1561
1562 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1563 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1564
1565 return BB;
1566 }
1567
1568 MachineBasicBlock *MipsTargetLowering::emitAtomicBinaryPartword(
1569 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1570 assert((Size == 1 || Size == 2) &&
1571 "Unsupported size for EmitAtomicBinaryPartial.");
1572
1573 MachineFunction *MF = BB->getParent();
1574 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1575 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1576 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1577 const TargetRegisterClass *RCp =
1578 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1579 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1580 DebugLoc DL = MI.getDebugLoc();
1581
1582 Register Dest = MI.getOperand(0).getReg();
1583 Register Ptr = MI.getOperand(1).getReg();
1584 Register Incr = MI.getOperand(2).getReg();
1585
1586 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1587 Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1588 Register Mask = RegInfo.createVirtualRegister(RC);
1589 Register Mask2 = RegInfo.createVirtualRegister(RC);
1590 Register Incr2 = RegInfo.createVirtualRegister(RC);
1591 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1592 Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1593 Register MaskUpper = RegInfo.createVirtualRegister(RC);
1594 Register Scratch = RegInfo.createVirtualRegister(RC);
1595 Register Scratch2 = RegInfo.createVirtualRegister(RC);
1596 Register Scratch3 = RegInfo.createVirtualRegister(RC);
1597
1598 unsigned AtomicOp = 0;
1599 switch (MI.getOpcode()) {
1600 case Mips::ATOMIC_LOAD_NAND_I8:
1601 AtomicOp = Mips::ATOMIC_LOAD_NAND_I8_POSTRA;
1602 break;
1603 case Mips::ATOMIC_LOAD_NAND_I16:
1604 AtomicOp = Mips::ATOMIC_LOAD_NAND_I16_POSTRA;
1605 break;
1606 case Mips::ATOMIC_SWAP_I8:
1607 AtomicOp = Mips::ATOMIC_SWAP_I8_POSTRA;
1608 break;
1609 case Mips::ATOMIC_SWAP_I16:
1610 AtomicOp = Mips::ATOMIC_SWAP_I16_POSTRA;
1611 break;
1612 case Mips::ATOMIC_LOAD_ADD_I8:
1613 AtomicOp = Mips::ATOMIC_LOAD_ADD_I8_POSTRA;
1614 break;
1615 case Mips::ATOMIC_LOAD_ADD_I16:
1616 AtomicOp = Mips::ATOMIC_LOAD_ADD_I16_POSTRA;
1617 break;
1618 case Mips::ATOMIC_LOAD_SUB_I8:
1619 AtomicOp = Mips::ATOMIC_LOAD_SUB_I8_POSTRA;
1620 break;
1621 case Mips::ATOMIC_LOAD_SUB_I16:
1622 AtomicOp = Mips::ATOMIC_LOAD_SUB_I16_POSTRA;
1623 break;
1624 case Mips::ATOMIC_LOAD_AND_I8:
1625 AtomicOp = Mips::ATOMIC_LOAD_AND_I8_POSTRA;
1626 break;
1627 case Mips::ATOMIC_LOAD_AND_I16:
1628 AtomicOp = Mips::ATOMIC_LOAD_AND_I16_POSTRA;
1629 break;
1630 case Mips::ATOMIC_LOAD_OR_I8:
1631 AtomicOp = Mips::ATOMIC_LOAD_OR_I8_POSTRA;
1632 break;
1633 case Mips::ATOMIC_LOAD_OR_I16:
1634 AtomicOp = Mips::ATOMIC_LOAD_OR_I16_POSTRA;
1635 break;
1636 case Mips::ATOMIC_LOAD_XOR_I8:
1637 AtomicOp = Mips::ATOMIC_LOAD_XOR_I8_POSTRA;
1638 break;
1639 case Mips::ATOMIC_LOAD_XOR_I16:
1640 AtomicOp = Mips::ATOMIC_LOAD_XOR_I16_POSTRA;
1641 break;
1642 default:
1643 llvm_unreachable("Unknown subword atomic pseudo for expansion!");
1644 }
1645
1646 // insert new blocks after the current block
1647 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1648 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1649 MachineFunction::iterator It = ++BB->getIterator();
1650 MF->insert(It, exitMBB);
1651
1652 // Transfer the remainder of BB and its successor edges to exitMBB.
1653 exitMBB->splice(exitMBB->begin(), BB,
1654 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1655 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1656
1657 BB->addSuccessor(exitMBB, BranchProbability::getOne());
1658
1659 // thisMBB:
1660 // addiu masklsb2,$0,-4 # 0xfffffffc
1661 // and alignedaddr,ptr,masklsb2
1662 // andi ptrlsb2,ptr,3
1663 // sll shiftamt,ptrlsb2,3
1664 // ori maskupper,$0,255 # 0xff
1665 // sll mask,maskupper,shiftamt
1666 // nor mask2,$0,mask
1667 // sll incr2,incr,shiftamt
1668
1669 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1670 BuildMI(BB, DL, TII->get(ABI.GetPtrAddiuOp()), MaskLSB2)
1671 .addReg(ABI.GetNullPtr()).addImm(-4);
1672 BuildMI(BB, DL, TII->get(ABI.GetPtrAndOp()), AlignedAddr)
1673 .addReg(Ptr).addReg(MaskLSB2);
1674 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1675 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1676 if (Subtarget.isLittle()) {
1677 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1678 } else {
1679 Register Off = RegInfo.createVirtualRegister(RC);
1680 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1681 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1682 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1683 }
1684 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1685 .addReg(Mips::ZERO).addImm(MaskImm);
1686 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1687 .addReg(MaskUpper).addReg(ShiftAmt);
1688 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1689 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1690
1691
1692 // The purposes of the flags on the scratch registers is explained in
1693 // emitAtomicBinary. In summary, we need a scratch register which is going to
1694 // be undef, that is unique among registers chosen for the instruction.
1695
1696 BuildMI(BB, DL, TII->get(AtomicOp))
1697 .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1698 .addReg(AlignedAddr)
1699 .addReg(Incr2)
1700 .addReg(Mask)
1701 .addReg(Mask2)
1702 .addReg(ShiftAmt)
1703 .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1704 RegState::Dead | RegState::Implicit)
1705 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
1706 RegState::Dead | RegState::Implicit)
1707 .addReg(Scratch3, RegState::EarlyClobber | RegState::Define |
1708 RegState::Dead | RegState::Implicit);
1709
1710 MI.eraseFromParent(); // The instruction is gone now.
1711
1712 return exitMBB;
1713 }
1714
1715 // Lower atomic compare and swap to a pseudo instruction, taking care to
1716 // define a scratch register for the pseudo instruction's expansion. The
1717 // instruction is expanded after the register allocator as to prevent
1718 // the insertion of stores between the linked load and the store conditional.
1719
1720 MachineBasicBlock *
1721 MipsTargetLowering::emitAtomicCmpSwap(MachineInstr &MI,
1722 MachineBasicBlock *BB) const {
1723
1724 assert((MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ||
1725 MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I64) &&
1726 "Unsupported atomic pseudo for EmitAtomicCmpSwap.");
1727
1728 const unsigned Size = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32 ? 4 : 8;
1729
1730 MachineFunction *MF = BB->getParent();
1731 MachineRegisterInfo &MRI = MF->getRegInfo();
1732 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1733 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1734 DebugLoc DL = MI.getDebugLoc();
1735
1736 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I32
1737 ? Mips::ATOMIC_CMP_SWAP_I32_POSTRA
1738 : Mips::ATOMIC_CMP_SWAP_I64_POSTRA;
1739 Register Dest = MI.getOperand(0).getReg();
1740 Register Ptr = MI.getOperand(1).getReg();
1741 Register OldVal = MI.getOperand(2).getReg();
1742 Register NewVal = MI.getOperand(3).getReg();
1743
1744 Register Scratch = MRI.createVirtualRegister(RC);
1745 MachineBasicBlock::iterator II(MI);
1746
1747 // We need to create copies of the various registers and kill them at the
1748 // atomic pseudo. If the copies are not made, when the atomic is expanded
1749 // after fast register allocation, the spills will end up outside of the
1750 // blocks that their values are defined in, causing livein errors.
1751
1752 Register PtrCopy = MRI.createVirtualRegister(MRI.getRegClass(Ptr));
1753 Register OldValCopy = MRI.createVirtualRegister(MRI.getRegClass(OldVal));
1754 Register NewValCopy = MRI.createVirtualRegister(MRI.getRegClass(NewVal));
1755
1756 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1757 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1758 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1759
1760 // The purposes of the flags on the scratch registers is explained in
1761 // emitAtomicBinary. In summary, we need a scratch register which is going to
1762 // be undef, that is unique among registers chosen for the instruction.
1763
1764 BuildMI(*BB, II, DL, TII->get(AtomicOp))
1765 .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1766 .addReg(PtrCopy, RegState::Kill)
1767 .addReg(OldValCopy, RegState::Kill)
1768 .addReg(NewValCopy, RegState::Kill)
1769 .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1770 RegState::Dead | RegState::Implicit);
1771
1772 MI.eraseFromParent(); // The instruction is gone now.
1773
1774 return BB;
1775 }
1776
1777 MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
1778 MachineInstr &MI, MachineBasicBlock *BB, unsigned Size) const {
1779 assert((Size == 1 || Size == 2) &&
1780 "Unsupported size for EmitAtomicCmpSwapPartial.");
1781
1782 MachineFunction *MF = BB->getParent();
1783 MachineRegisterInfo &RegInfo = MF->getRegInfo();
1784 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1785 const bool ArePtrs64bit = ABI.ArePtrs64bit();
1786 const TargetRegisterClass *RCp =
1787 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32);
1788 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
1789 DebugLoc DL = MI.getDebugLoc();
1790
1791 Register Dest = MI.getOperand(0).getReg();
1792 Register Ptr = MI.getOperand(1).getReg();
1793 Register CmpVal = MI.getOperand(2).getReg();
1794 Register NewVal = MI.getOperand(3).getReg();
1795
1796 Register AlignedAddr = RegInfo.createVirtualRegister(RCp);
1797 Register ShiftAmt = RegInfo.createVirtualRegister(RC);
1798 Register Mask = RegInfo.createVirtualRegister(RC);
1799 Register Mask2 = RegInfo.createVirtualRegister(RC);
1800 Register ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1801 Register ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1802 Register MaskLSB2 = RegInfo.createVirtualRegister(RCp);
1803 Register PtrLSB2 = RegInfo.createVirtualRegister(RC);
1804 Register MaskUpper = RegInfo.createVirtualRegister(RC);
1805 Register MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1806 Register MaskedNewVal = RegInfo.createVirtualRegister(RC);
1807 unsigned AtomicOp = MI.getOpcode() == Mips::ATOMIC_CMP_SWAP_I8
1808 ? Mips::ATOMIC_CMP_SWAP_I8_POSTRA
1809 : Mips::ATOMIC_CMP_SWAP_I16_POSTRA;
1810
1811 // The scratch registers here with the EarlyClobber | Define | Dead | Implicit
1812 // flags are used to coerce the register allocator and the machine verifier to
1813 // accept the usage of these registers.
1814 // The EarlyClobber flag has the semantic properties that the operand it is
1815 // attached to is clobbered before the rest of the inputs are read. Hence it
1816 // must be unique among the operands to the instruction.
1817 // The Define flag is needed to coerce the machine verifier that an Undef
1818 // value isn't a problem.
1819 // The Dead flag is needed as the value in scratch isn't used by any other
1820 // instruction. Kill isn't used as Dead is more precise.
1821 Register Scratch = RegInfo.createVirtualRegister(RC);
1822 Register Scratch2 = RegInfo.createVirtualRegister(RC);
1823
1824 // insert new blocks after the current block
1825 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1826 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
1827 MachineFunction::iterator It = ++BB->getIterator();
1828 MF->insert(It, exitMBB);
1829
1830 // Transfer the remainder of BB and its successor edges to exitMBB.
1831 exitMBB->splice(exitMBB->begin(), BB,
1832 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1833 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
1834
1835 BB->addSuccessor(exitMBB, BranchProbability::getOne());
1836
1837 // thisMBB:
1838 // addiu masklsb2,$0,-4 # 0xfffffffc
1839 // and alignedaddr,ptr,masklsb2
1840 // andi ptrlsb2,ptr,3
1841 // xori ptrlsb2,ptrlsb2,3 # Only for BE
1842 // sll shiftamt,ptrlsb2,3
1843 // ori maskupper,$0,255 # 0xff
1844 // sll mask,maskupper,shiftamt
1845 // nor mask2,$0,mask
1846 // andi maskedcmpval,cmpval,255
1847 // sll shiftedcmpval,maskedcmpval,shiftamt
1848 // andi maskednewval,newval,255
1849 // sll shiftednewval,maskednewval,shiftamt
1850 int64_t MaskImm = (Size == 1) ? 255 : 65535;
1851 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2)
1852 .addReg(ABI.GetNullPtr()).addImm(-4);
1853 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::AND64 : Mips::AND), AlignedAddr)
1854 .addReg(Ptr).addReg(MaskLSB2);
1855 BuildMI(BB, DL, TII->get(Mips::ANDi), PtrLSB2)
1856 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1857 if (Subtarget.isLittle()) {
1858 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1859 } else {
1860 Register Off = RegInfo.createVirtualRegister(RC);
1861 BuildMI(BB, DL, TII->get(Mips::XORi), Off)
1862 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1863 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1864 }
1865 BuildMI(BB, DL, TII->get(Mips::ORi), MaskUpper)
1866 .addReg(Mips::ZERO).addImm(MaskImm);
1867 BuildMI(BB, DL, TII->get(Mips::SLLV), Mask)
1868 .addReg(MaskUpper).addReg(ShiftAmt);
1869 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1870 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedCmpVal)
1871 .addReg(CmpVal).addImm(MaskImm);
1872 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedCmpVal)
1873 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1874 BuildMI(BB, DL, TII->get(Mips::ANDi), MaskedNewVal)
1875 .addReg(NewVal).addImm(MaskImm);
1876 BuildMI(BB, DL, TII->get(Mips::SLLV), ShiftedNewVal)
1877 .addReg(MaskedNewVal).addReg(ShiftAmt);
1878
1879 // The purposes of the flags on the scratch registers are explained in
1880 // emitAtomicBinary. In summary, we need a scratch register which is going to
1881 // be undef, that is unique among the register chosen for the instruction.
1882
1883 BuildMI(BB, DL, TII->get(AtomicOp))
1884 .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1885 .addReg(AlignedAddr)
1886 .addReg(Mask)
1887 .addReg(ShiftedCmpVal)
1888 .addReg(Mask2)
1889 .addReg(ShiftedNewVal)
1890 .addReg(ShiftAmt)
1891 .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1892 RegState::Dead | RegState::Implicit)
1893 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
1894 RegState::Dead | RegState::Implicit);
1895
1896 MI.eraseFromParent(); // The instruction is gone now.
1897
1898 return exitMBB;
1899 }
1900
1901 SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
1902 // The first operand is the chain, the second is the condition, the third is
1903 // the block to branch to if the condition is true.
1904 SDValue Chain = Op.getOperand(0);
1905 SDValue Dest = Op.getOperand(2);
1906 SDLoc DL(Op);
1907
1908 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1909 SDValue CondRes = createFPCmp(DAG, Op.getOperand(1));
1910
1911 // Return if flag is not set by a floating point comparison.
1912 if (CondRes.getOpcode() != MipsISD::FPCmp)
1913 return Op;
1914
1915 SDValue CCNode = CondRes.getOperand(2);
1916 Mips::CondCode CC =
1917 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
1918 unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
1919 SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
1920 SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
1921 return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode,
1922 FCC0, Dest, CondRes);
1923 }
1924
1925 SDValue MipsTargetLowering::
1926 lowerSELECT(SDValue Op, SelectionDAG &DAG) const
1927 {
1928 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1929 SDValue Cond = createFPCmp(DAG, Op.getOperand(0));
1930
1931 // Return if flag is not set by a floating point comparison.
1932 if (Cond.getOpcode() != MipsISD::FPCmp)
1933 return Op;
1934
1935 return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2),
1936 SDLoc(Op));
1937 }
1938
1939 SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1940 assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6());
1941 SDValue Cond = createFPCmp(DAG, Op);
1942
1943 assert(Cond.getOpcode() == MipsISD::FPCmp &&
1944 "Floating point operand expected.");
1945
1946 SDLoc DL(Op);
1947 SDValue True = DAG.getConstant(1, DL, MVT::i32);
1948 SDValue False = DAG.getConstant(0, DL, MVT::i32);
1949
1950 return createCMovFP(DAG, Cond, True, False, DL);
1951 }
1952
1953 SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op,
1954 SelectionDAG &DAG) const {
1955 EVT Ty = Op.getValueType();
1956 GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
1957 const GlobalValue *GV = N->getGlobal();
1958
1959 if (!isPositionIndependent()) {
1960 const MipsTargetObjectFile *TLOF =
1961 static_cast<const MipsTargetObjectFile *>(
1962 getTargetMachine().getObjFileLowering());
1963 const GlobalObject *GO = GV->getBaseObject();
1964 if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
1965 // %gp_rel relocation
1966 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
1967
1968 // %hi/%lo relocation
1969 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
1970 // %highest/%higher/%hi/%lo relocation
1971 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
1972 }
1973
1974 // Every other architecture would use shouldAssumeDSOLocal in here, but
1975 // mips is special.
1976 // * In PIC code mips requires got loads even for local statics!
1977 // * To save on got entries, for local statics the got entry contains the
1978 // page and an additional add instruction takes care of the low bits.
1979 // * It is legal to access a hidden symbol with a non hidden undefined,
1980 // so one cannot guarantee that all access to a hidden symbol will know
1981 // it is hidden.
1982 // * Mips linkers don't support creating a page and a full got entry for
1983 // the same symbol.
1984 // * Given all that, we have to use a full got entry for hidden symbols :-(
1985 if (GV->hasLocalLinkage())
1986 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
1987
1988 if (Subtarget.useXGOT())
1989 return getAddrGlobalLargeGOT(
1990 N, SDLoc(N), Ty, DAG, MipsII::MO_GOT_HI16, MipsII::MO_GOT_LO16,
1991 DAG.getEntryNode(),
1992 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1993
1994 return getAddrGlobal(
1995 N, SDLoc(N), Ty, DAG,
1996 (ABI.IsN32() || ABI.IsN64()) ? MipsII::MO_GOT_DISP : MipsII::MO_GOT,
1997 DAG.getEntryNode(), MachinePointerInfo::getGOT(DAG.getMachineFunction()));
1998 }
1999
2000 SDValue MipsTargetLowering::lowerBlockAddress(SDValue Op,
2001 SelectionDAG &DAG) const {
2002 BlockAddressSDNode *N = cast<BlockAddressSDNode>(Op);
2003 EVT Ty = Op.getValueType();
2004
2005 if (!isPositionIndependent())
2006 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2007 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2008
2009 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2010 }
2011
2012 SDValue MipsTargetLowering::
2013 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
2014 {
2015 // If the relocation model is PIC, use the General Dynamic TLS Model or
2016 // Local Dynamic TLS model, otherwise use the Initial Exec or
2017 // Local Exec TLS Model.
2018
2019 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2020 if (DAG.getTarget().useEmulatedTLS())
2021 return LowerToTLSEmulatedModel(GA, DAG);
2022
2023 SDLoc DL(GA);
2024 const GlobalValue *GV = GA->getGlobal();
2025 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2026
2027 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
2028
2029 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
2030 // General Dynamic and Local Dynamic TLS Model.
2031 unsigned Flag = (model == TLSModel::LocalDynamic) ? MipsII::MO_TLSLDM
2032 : MipsII::MO_TLSGD;
2033
2034 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, Flag);
2035 SDValue Argument = DAG.getNode(MipsISD::Wrapper, DL, PtrVT,
2036 getGlobalReg(DAG, PtrVT), TGA);
2037 unsigned PtrSize = PtrVT.getSizeInBits();
2038 IntegerType *PtrTy = Type::getIntNTy(*DAG.getContext(), PtrSize);
2039
2040 SDValue TlsGetAddr = DAG.getExternalSymbol("__tls_get_addr", PtrVT);
2041
2042 ArgListTy Args;
2043 ArgListEntry Entry;
2044 Entry.Node = Argument;
2045 Entry.Ty = PtrTy;
2046 Args.push_back(Entry);
2047
2048 TargetLowering::CallLoweringInfo CLI(DAG);
2049 CLI.setDebugLoc(DL)
2050 .setChain(DAG.getEntryNode())
2051 .setLibCallee(CallingConv::C, PtrTy, TlsGetAddr, std::move(Args));
2052 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2053
2054 SDValue Ret = CallResult.first;
2055
2056 if (model != TLSModel::LocalDynamic)
2057 return Ret;
2058
2059 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2060 MipsII::MO_DTPREL_HI);
2061 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2062 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2063 MipsII::MO_DTPREL_LO);
2064 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2065 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Ret);
2066 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo);
2067 }
2068
2069 SDValue Offset;
2070 if (model == TLSModel::InitialExec) {
2071 // Initial Exec TLS Model
2072 SDValue TGA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2073 MipsII::MO_GOTTPREL);
2074 TGA = DAG.getNode(MipsISD::Wrapper, DL, PtrVT, getGlobalReg(DAG, PtrVT),
2075 TGA);
2076 Offset =
2077 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), TGA, MachinePointerInfo());
2078 } else {
2079 // Local Exec TLS Model
2080 assert(model == TLSModel::LocalExec);
2081 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2082 MipsII::MO_TPREL_HI);
2083 SDValue TGALo = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2084 MipsII::MO_TPREL_LO);
2085 SDValue Hi = DAG.getNode(MipsISD::TlsHi, DL, PtrVT, TGAHi);
2086 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo);
2087 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
2088 }
2089
2090 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2091 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadPointer, Offset);
2092 }
2093
2094 SDValue MipsTargetLowering::
2095 lowerJumpTable(SDValue Op, SelectionDAG &DAG) const
2096 {
2097 JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
2098 EVT Ty = Op.getValueType();
2099
2100 if (!isPositionIndependent())
2101 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2102 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2103
2104 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2105 }
2106
2107 SDValue MipsTargetLowering::
2108 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const
2109 {
2110 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
2111 EVT Ty = Op.getValueType();
2112
2113 if (!isPositionIndependent()) {
2114 const MipsTargetObjectFile *TLOF =
2115 static_cast<const MipsTargetObjectFile *>(
2116 getTargetMachine().getObjFileLowering());
2117
2118 if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
2119 getTargetMachine()))
2120 // %gp_rel relocation
2121 return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
2122
2123 return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
2124 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
2125 }
2126
2127 return getAddrLocal(N, SDLoc(N), Ty, DAG, ABI.IsN32() || ABI.IsN64());
2128 }
2129
2130 SDValue MipsTargetLowering::lowerVASTART(SDValue Op, SelectionDAG &DAG) const {
2131 MachineFunction &MF = DAG.getMachineFunction();
2132 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
2133
2134 SDLoc DL(Op);
2135 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2136 getPointerTy(MF.getDataLayout()));
2137
2138 // vastart just stores the address of the VarArgsFrameIndex slot into the
2139 // memory location argument.
2140 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2141 return DAG.getStore(Op.getOperand(0), DL, FI, Op.getOperand(1),
2142 MachinePointerInfo(SV));
2143 }
2144
2145 SDValue MipsTargetLowering::lowerVAARG(SDValue Op, SelectionDAG &DAG) const {
2146 SDNode *Node = Op.getNode();
2147 EVT VT = Node->getValueType(0);
2148 SDValue Chain = Node->getOperand(0);
2149 SDValue VAListPtr = Node->getOperand(1);
2150 const Align Align =
2151 llvm::MaybeAlign(Node->getConstantOperandVal(3)).valueOrOne();
2152 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2153 SDLoc DL(Node);
2154 unsigned ArgSlotSizeInBytes = (ABI.IsN32() || ABI.IsN64()) ? 8 : 4;
2155
2156 SDValue VAListLoad = DAG.getLoad(getPointerTy(DAG.getDataLayout()), DL, Chain,
2157 VAListPtr, MachinePointerInfo(SV));
2158 SDValue VAList = VAListLoad;
2159
2160 // Re-align the pointer if necessary.
2161 // It should only ever be necessary for 64-bit types on O32 since the minimum
2162 // argument alignment is the same as the maximum type alignment for N32/N64.
2163 //
2164 // FIXME: We currently align too often. The code generator doesn't notice
2165 // when the pointer is still aligned from the last va_arg (or pair of
2166 // va_args for the i64 on O32 case).
2167 if (Align > getMinStackArgumentAlignment()) {
2168 VAList = DAG.getNode(
2169 ISD::ADD, DL, VAList.getValueType(), VAList,
2170 DAG.getConstant(Align.value() - 1, DL, VAList.getValueType()));
2171
2172 VAList = DAG.getNode(
2173 ISD::AND, DL, VAList.getValueType(), VAList,
2174 DAG.getConstant(-(int64_t)Align.value(), DL, VAList.getValueType()));
2175 }
2176
2177 // Increment the pointer, VAList, to the next vaarg.
2178 auto &TD = DAG.getDataLayout();
2179 unsigned ArgSizeInBytes =
2180 TD.getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext()));
2181 SDValue Tmp3 =
2182 DAG.getNode(ISD::ADD, DL, VAList.getValueType(), VAList,
2183 DAG.getConstant(alignTo(ArgSizeInBytes, ArgSlotSizeInBytes),
2184 DL, VAList.getValueType()));
2185 // Store the incremented VAList to the legalized pointer
2186 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
2187 MachinePointerInfo(SV));
2188
2189 // In big-endian mode we must adjust the pointer when the load size is smaller
2190 // than the argument slot size. We must also reduce the known alignment to
2191 // match. For example in the N64 ABI, we must add 4 bytes to the offset to get
2192 // the correct half of the slot, and reduce the alignment from 8 (slot
2193 // alignment) down to 4 (type alignment).
2194 if (!Subtarget.isLittle() && ArgSizeInBytes < ArgSlotSizeInBytes) {
2195 unsigned Adjustment = ArgSlotSizeInBytes - ArgSizeInBytes;
2196 VAList = DAG.getNode(ISD::ADD, DL, VAListPtr.getValueType(), VAList,
2197 DAG.getIntPtrConstant(Adjustment, DL));
2198 }
2199 // Load the actual argument out of the pointer VAList
2200 return DAG.getLoad(VT, DL, Chain, VAList, MachinePointerInfo());
2201 }
2202
2203 static SDValue lowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG,
2204 bool HasExtractInsert) {
2205 EVT TyX = Op.getOperand(0).getValueType();
2206 EVT TyY = Op.getOperand(1).getValueType();
2207 SDLoc DL(Op);
2208 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2209 SDValue Const31 = DAG.getConstant(31, DL, MVT::i32);
2210 SDValue Res;
2211
2212 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2213 // to i32.
2214 SDValue X = (TyX == MVT::f32) ?
2215 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0)) :
2216 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2217 Const1);
2218 SDValue Y = (TyY == MVT::f32) ?
2219 DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(1)) :
2220 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(1),
2221 Const1);
2222
2223 if (HasExtractInsert) {
2224 // ext E, Y, 31, 1 ; extract bit31 of Y
2225 // ins X, E, 31, 1 ; insert extracted bit at bit31 of X
2226 SDValue E = DAG.getNode(MipsISD::Ext, DL, MVT::i32, Y, Const31, Const1);
2227 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32, E, Const31, Const1, X);
2228 } else {
2229 // sll SllX, X, 1
2230 // srl SrlX, SllX, 1
2231 // srl SrlY, Y, 31
2232 // sll SllY, SrlX, 31
2233 // or Or, SrlX, SllY
2234 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2235 SDValue SrlX = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2236 SDValue SrlY = DAG.getNode(ISD::SRL, DL, MVT::i32, Y, Const31);
2237 SDValue SllY = DAG.getNode(ISD::SHL, DL, MVT::i32, SrlY, Const31);
2238 Res = DAG.getNode(ISD::OR, DL, MVT::i32, SrlX, SllY);
2239 }
2240
2241 if (TyX == MVT::f32)
2242 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Res);
2243
2244 SDValue LowX = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2245 Op.getOperand(0),
2246 DAG.getConstant(0, DL, MVT::i32));
2247 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2248 }
2249
2250 static SDValue lowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG,
2251 bool HasExtractInsert) {
2252 unsigned WidthX = Op.getOperand(0).getValueSizeInBits();
2253 unsigned WidthY = Op.getOperand(1).getValueSizeInBits();
2254 EVT TyX = MVT::getIntegerVT(WidthX), TyY = MVT::getIntegerVT(WidthY);
2255 SDLoc DL(Op);
2256 SDValue Const1 = DAG.getConstant(1, DL, MVT::i32);
2257
2258 // Bitcast to integer nodes.
2259 SDValue X = DAG.getNode(ISD::BITCAST, DL, TyX, Op.getOperand(0));
2260 SDValue Y = DAG.getNode(ISD::BITCAST, DL, TyY, Op.getOperand(1));
2261
2262 if (HasExtractInsert) {
2263 // ext E, Y, width(Y) - 1, 1 ; extract bit width(Y)-1 of Y
2264 // ins X, E, width(X) - 1, 1 ; insert extracted bit at bit width(X)-1 of X
2265 SDValue E = DAG.getNode(MipsISD::Ext, DL, TyY, Y,
2266 DAG.getConstant(WidthY - 1, DL, MVT::i32), Const1);
2267
2268 if (WidthX > WidthY)
2269 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E);
2270 else if (WidthY > WidthX)
2271 E = DAG.getNode(ISD::TRUNCATE, DL, TyX, E);
2272
2273 SDValue I = DAG.getNode(MipsISD::Ins, DL, TyX, E,
2274 DAG.getConstant(WidthX - 1, DL, MVT::i32), Const1,
2275 X);
2276 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), I);
2277 }
2278
2279 // (d)sll SllX, X, 1
2280 // (d)srl SrlX, SllX, 1
2281 // (d)srl SrlY, Y, width(Y)-1
2282 // (d)sll SllY, SrlX, width(Y)-1
2283 // or Or, SrlX, SllY
2284 SDValue SllX = DAG.getNode(ISD::SHL, DL, TyX, X, Const1);
2285 SDValue SrlX = DAG.getNode(ISD::SRL, DL, TyX, SllX, Const1);
2286 SDValue SrlY = DAG.getNode(ISD::SRL, DL, TyY, Y,
2287 DAG.getConstant(WidthY - 1, DL, MVT::i32));
2288
2289 if (WidthX > WidthY)
2290 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY);
2291 else if (WidthY > WidthX)
2292 SrlY = DAG.getNode(ISD::TRUNCATE, DL, TyX, SrlY);
2293
2294 SDValue SllY = DAG.getNode(ISD::SHL, DL, TyX, SrlY,
2295 DAG.getConstant(WidthX - 1, DL, MVT::i32));
2296 SDValue Or = DAG.getNode(ISD::OR, DL, TyX, SrlX, SllY);
2297 return DAG.getNode(ISD::BITCAST, DL, Op.getOperand(0).getValueType(), Or);
2298 }
2299
2300 SDValue
2301 MipsTargetLowering::lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2302 if (Subtarget.isGP64bit())
2303 return lowerFCOPYSIGN64(Op, DAG, Subtarget.hasExtractInsert());
2304
2305 return lowerFCOPYSIGN32(Op, DAG, Subtarget.hasExtractInsert());
2306 }
2307
2308 static SDValue lowerFABS32(SDValue Op, SelectionDAG &DAG,
2309 bool HasExtractInsert) {
2310 SDLoc DL(Op);
2311 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2312
2313 // If operand is of type f64, extract the upper 32-bit. Otherwise, bitcast it
2314 // to i32.
2315 SDValue X = (Op.getValueType() == MVT::f32)
2316 ? DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op.getOperand(0))
2317 : DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
2318 Op.getOperand(0), Const1);
2319
2320 // Clear MSB.
2321 if (HasExtractInsert)
2322 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i32,
2323 DAG.getRegister(Mips::ZERO, MVT::i32),
2324 DAG.getConstant(31, DL, MVT::i32), Const1, X);
2325 else {
2326 // TODO: Provide DAG patterns which transform (and x, cst)
2327 // back to a (shl (srl x (clz cst)) (clz cst)) sequence.
2328 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i32, X, Const1);
2329 Res = DAG.getNode(ISD::SRL, DL, MVT::i32, SllX, Const1);
2330 }
2331
2332 if (Op.getValueType() == MVT::f32)
2333 return DAG.getNode(ISD::BITCAST, DL, MVT::f32, Res);
2334
2335 // FIXME: For mips32r2, the sequence of (BuildPairF64 (ins (ExtractElementF64
2336 // Op 1), $zero, 31 1) (ExtractElementF64 Op 0)) and the Op has one use, we
2337 // should be able to drop the usage of mfc1/mtc1 and rewrite the register in
2338 // place.
2339 SDValue LowX =
2340 DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, Op.getOperand(0),
2341 DAG.getConstant(0, DL, MVT::i32));
2342 return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, LowX, Res);
2343 }
2344
2345 static SDValue lowerFABS64(SDValue Op, SelectionDAG &DAG,
2346 bool HasExtractInsert) {
2347 SDLoc DL(Op);
2348 SDValue Res, Const1 = DAG.getConstant(1, DL, MVT::i32);
2349
2350 // Bitcast to integer node.
2351 SDValue X = DAG.getNode(ISD::BITCAST, DL, MVT::i64, Op.getOperand(0));
2352
2353 // Clear MSB.
2354 if (HasExtractInsert)
2355 Res = DAG.getNode(MipsISD::Ins, DL, MVT::i64,
2356 DAG.getRegister(Mips::ZERO_64, MVT::i64),
2357 DAG.getConstant(63, DL, MVT::i32), Const1, X);
2358 else {
2359 SDValue SllX = DAG.getNode(ISD::SHL, DL, MVT::i64, X, Const1);
2360 Res = DAG.getNode(ISD::SRL, DL, MVT::i64, SllX, Const1);
2361 }
2362
2363 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, Res);
2364 }
2365
2366 SDValue MipsTargetLowering::lowerFABS(SDValue Op, SelectionDAG &DAG) const {
2367 if ((ABI.IsN32() || ABI.IsN64()) && (Op.getValueType() == MVT::f64))
2368 return lowerFABS64(Op, DAG, Subtarget.hasExtractInsert());
2369
2370 return lowerFABS32(Op, DAG, Subtarget.hasExtractInsert());
2371 }
2372
2373 SDValue MipsTargetLowering::
2374 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2375 // check the depth
2376 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
2377 DAG.getContext()->emitError(
2378 "return address can be determined only for current frame");
2379 return SDValue();
2380 }
2381
2382 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2383 MFI.setFrameAddressIsTaken(true);
2384 EVT VT = Op.getValueType();
2385 SDLoc DL(Op);
2386 SDValue FrameAddr = DAG.getCopyFromReg(
2387 DAG.getEntryNode(), DL, ABI.IsN64() ? Mips::FP_64 : Mips::FP, VT);
2388 return FrameAddr;
2389 }
2390
2391 SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op,
2392 SelectionDAG &DAG) const {
2393 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
2394 return SDValue();
2395
2396 // check the depth
2397 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() != 0) {
2398 DAG.getContext()->emitError(
2399 "return address can be determined only for current frame");
2400 return SDValue();
2401 }
2402
2403 MachineFunction &MF = DAG.getMachineFunction();
2404 MachineFrameInfo &MFI = MF.getFrameInfo();
2405 MVT VT = Op.getSimpleValueType();
2406 unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA;
2407 MFI.setReturnAddressIsTaken(true);
2408
2409 // Return RA, which contains the return address. Mark it an implicit live-in.
2410 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT));
2411 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op), Reg, VT);
2412 }
2413
2414 // An EH_RETURN is the result of lowering llvm.eh.return which in turn is
2415 // generated from __builtin_eh_return (offset, handler)
2416 // The effect of this is to adjust the stack pointer by "offset"
2417 // and then branch to "handler".
2418 SDValue MipsTargetLowering::lowerEH_RETURN(SDValue Op, SelectionDAG &DAG)
2419 const {
2420 MachineFunction &MF = DAG.getMachineFunction();
2421 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
2422
2423 MipsFI->setCallsEhReturn();
2424 SDValue Chain = Op.getOperand(0);
2425 SDValue Offset = Op.getOperand(1);
2426 SDValue Handler = Op.getOperand(2);
2427 SDLoc DL(Op);
2428 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2429
2430 // Store stack offset in V1, store jump target in V0. Glue CopyToReg and
2431 // EH_RETURN nodes, so that instructions are emitted back-to-back.
2432 unsigned OffsetReg = ABI.IsN64() ? Mips::V1_64 : Mips::V1;
2433 unsigned AddrReg = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
2434 Chain = DAG.getCopyToReg(Chain, DL, OffsetReg, Offset, SDValue());
2435 Chain = DAG.getCopyToReg(Chain, DL, AddrReg, Handler, Chain.getValue(1));
2436 return DAG.getNode(MipsISD::EH_RETURN, DL, MVT::Other, Chain,
2437 DAG.getRegister(OffsetReg, Ty),
2438 DAG.getRegister(AddrReg, getPointerTy(MF.getDataLayout())),
2439 Chain.getValue(1));
2440 }
2441
2442 SDValue MipsTargetLowering::lowerATOMIC_FENCE(SDValue Op,
2443 SelectionDAG &DAG) const {
2444 // FIXME: Need pseudo-fence for 'singlethread' fences
2445 // FIXME: Set SType for weaker fences where supported/appropriate.
2446 unsigned SType = 0;
2447 SDLoc DL(Op);
2448 return DAG.getNode(MipsISD::Sync, DL, MVT::Other, Op.getOperand(0),
2449 DAG.getConstant(SType, DL, MVT::i32));
2450 }
2451
2452 SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op,
2453 SelectionDAG &DAG) const {
2454 SDLoc DL(Op);
2455 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2456
2457 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2458 SDValue Shamt = Op.getOperand(2);
2459 // if shamt < (VT.bits):
2460 // lo = (shl lo, shamt)
2461 // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt))
2462 // else:
2463 // lo = 0
2464 // hi = (shl lo, shamt[4:0])
2465 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2466 DAG.getConstant(-1, DL, MVT::i32));
2467 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo,
2468 DAG.getConstant(1, DL, VT));
2469 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not);
2470 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
2471 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2472 SDValue ShiftLeftLo = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
2473 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2474 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2475 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2476 DAG.getConstant(0, DL, VT), ShiftLeftLo);
2477 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftLeftLo, Or);
2478
2479 SDValue Ops[2] = {Lo, Hi};
2480 return DAG.getMergeValues(Ops, DL);
2481 }
2482
2483 SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
2484 bool IsSRA) const {
2485 SDLoc DL(Op);
2486 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1);
2487 SDValue Shamt = Op.getOperand(2);
2488 MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32;
2489
2490 // if shamt < (VT.bits):
2491 // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt))
2492 // if isSRA:
2493 // hi = (sra hi, shamt)
2494 // else:
2495 // hi = (srl hi, shamt)
2496 // else:
2497 // if isSRA:
2498 // lo = (sra hi, shamt[4:0])
2499 // hi = (sra hi, 31)
2500 // else:
2501 // lo = (srl hi, shamt[4:0])
2502 // hi = 0
2503 SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt,
2504 DAG.getConstant(-1, DL, MVT::i32));
2505 SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi,
2506 DAG.getConstant(1, DL, VT));
2507 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not);
2508 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
2509 SDValue Or = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
2510 SDValue ShiftRightHi = DAG.getNode(IsSRA ? ISD::SRA : ISD::SRL,
2511 DL, VT, Hi, Shamt);
2512 SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
2513 DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
2514 SDValue Ext = DAG.getNode(ISD::SRA, DL, VT, Hi,
2515 DAG.getConstant(VT.getSizeInBits() - 1, DL, VT));
2516
2517 if (!(Subtarget.hasMips4() || Subtarget.hasMips32())) {
2518 SDVTList VTList = DAG.getVTList(VT, VT);
2519 return DAG.getNode(Subtarget.isGP64bit() ? Mips::PseudoD_SELECT_I64
2520 : Mips::PseudoD_SELECT_I,
2521 DL, VTList, Cond, ShiftRightHi,
2522 IsSRA ? Ext : DAG.getConstant(0, DL, VT), Or,
2523 ShiftRightHi);
2524 }
2525
2526 Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond, ShiftRightHi, Or);
2527 Hi = DAG.getNode(ISD::SELECT, DL, VT, Cond,
2528 IsSRA ? Ext : DAG.getConstant(0, DL, VT), ShiftRightHi);
2529
2530 SDValue Ops[2] = {Lo, Hi};
2531 return DAG.getMergeValues(Ops, DL);
2532 }
2533
2534 static SDValue createLoadLR(unsigned Opc, SelectionDAG &DAG, LoadSDNode *LD,
2535 SDValue Chain, SDValue Src, unsigned Offset) {
2536 SDValue Ptr = LD->getBasePtr();
2537 EVT VT = LD->getValueType(0), MemVT = LD->getMemoryVT();
2538 EVT BasePtrVT = Ptr.getValueType();
2539 SDLoc DL(LD);
2540 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
2541
2542 if (Offset)
2543 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2544 DAG.getConstant(Offset, DL, BasePtrVT));
2545
2546 SDValue Ops[] = { Chain, Ptr, Src };
2547 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2548 LD->getMemOperand());
2549 }
2550
2551 // Expand an unaligned 32 or 64-bit integer load node.
2552 SDValue MipsTargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2553 LoadSDNode *LD = cast<LoadSDNode>(Op);
2554 EVT MemVT = LD->getMemoryVT();
2555
2556 if (Subtarget.systemSupportsUnalignedAccess())
2557 return Op;
2558
2559 // Return if load is aligned or if MemVT is neither i32 nor i64.
2560 if ((LD->getAlignment() >= MemVT.getSizeInBits() / 8) ||
2561 ((MemVT != MVT::i32) && (MemVT != MVT::i64)))
2562 return SDValue();
2563
2564 bool IsLittle = Subtarget.isLittle();
2565 EVT VT = Op.getValueType();
2566 ISD::LoadExtType ExtType = LD->getExtensionType();
2567 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT);
2568
2569 assert((VT == MVT::i32) || (VT == MVT::i64));
2570
2571 // Expand
2572 // (set dst, (i64 (load baseptr)))
2573 // to
2574 // (set tmp, (ldl (add baseptr, 7), undef))
2575 // (set dst, (ldr baseptr, tmp))
2576 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2577 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2578 IsLittle ? 7 : 0);
2579 return createLoadLR(MipsISD::LDR, DAG, LD, LDL.getValue(1), LDL,
2580 IsLittle ? 0 : 7);
2581 }
2582
2583 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
2584 IsLittle ? 3 : 0);
2585 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL,
2586 IsLittle ? 0 : 3);
2587
2588 // Expand
2589 // (set dst, (i32 (load baseptr))) or
2590 // (set dst, (i64 (sextload baseptr))) or
2591 // (set dst, (i64 (extload baseptr)))
2592 // to
2593 // (set tmp, (lwl (add baseptr, 3), undef))
2594 // (set dst, (lwr baseptr, tmp))
2595 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2596 (ExtType == ISD::EXTLOAD))
2597 return LWR;
2598
2599 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
2600
2601 // Expand
2602 // (set dst, (i64 (zextload baseptr)))
2603 // to
2604 // (set tmp0, (lwl (add baseptr, 3), undef))
2605 // (set tmp1, (lwr baseptr, tmp0))
2606 // (set tmp2, (shl tmp1, 32))
2607 // (set dst, (srl tmp2, 32))
2608 SDLoc DL(LD);
2609 SDValue Const32 = DAG.getConstant(32, DL, MVT::i32);
2610 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32);
2611 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
2612 SDValue Ops[] = { SRL, LWR.getValue(1) };
2613 return DAG.getMergeValues(Ops, DL);
2614 }
2615
2616 static SDValue createStoreLR(unsigned Opc, SelectionDAG &DAG, StoreSDNode *SD,
2617 SDValue Chain, unsigned Offset) {
2618 SDValue Ptr = SD->getBasePtr(), Value = SD->getValue();
2619 EVT MemVT = SD->getMemoryVT(), BasePtrVT = Ptr.getValueType();
2620 SDLoc DL(SD);
2621 SDVTList VTList = DAG.getVTList(MVT::Other);
2622
2623 if (Offset)
2624 Ptr = DAG.getNode(ISD::ADD, DL, BasePtrVT, Ptr,
2625 DAG.getConstant(Offset, DL, BasePtrVT));
2626
2627 SDValue Ops[] = { Chain, Value, Ptr };
2628 return DAG.getMemIntrinsicNode(Opc, DL, VTList, Ops, MemVT,
2629 SD->getMemOperand());
2630 }
2631
2632 // Expand an unaligned 32 or 64-bit integer store node.
2633 static SDValue lowerUnalignedIntStore(StoreSDNode *SD, SelectionDAG &DAG,
2634 bool IsLittle) {
2635 SDValue Value = SD->getValue(), Chain = SD->getChain();
2636 EVT VT = Value.getValueType();
2637
2638 // Expand
2639 // (store val, baseptr) or
2640 // (truncstore val, baseptr)
2641 // to
2642 // (swl val, (add baseptr, 3))
2643 // (swr val, baseptr)
2644 if ((VT == MVT::i32) || SD->isTruncatingStore()) {
2645 SDValue SWL = createStoreLR(MipsISD::SWL, DAG, SD, Chain,
2646 IsLittle ? 3 : 0);
2647 return createStoreLR(MipsISD::SWR, DAG, SD, SWL, IsLittle ? 0 : 3);
2648 }
2649
2650 assert(VT == MVT::i64);
2651
2652 // Expand
2653 // (store val, baseptr)
2654 // to
2655 // (sdl val, (add baseptr, 7))
2656 // (sdr val, baseptr)
2657 SDValue SDL = createStoreLR(MipsISD::SDL, DAG, SD, Chain, IsLittle ? 7 : 0);
2658 return createStoreLR(MipsISD::SDR, DAG, SD, SDL, IsLittle ? 0 : 7);
2659 }
2660
2661 // Lower (store (fp_to_sint $fp) $ptr) to (store (TruncIntFP $fp), $ptr).
2662 static SDValue lowerFP_TO_SINT_STORE(StoreSDNode *SD, SelectionDAG &DAG,
2663 bool SingleFloat) {
2664 SDValue Val = SD->getValue();
2665
2666 if (Val.getOpcode() != ISD::FP_TO_SINT ||
2667 (Val.getValueSizeInBits() > 32 && SingleFloat))
2668 return SDValue();
2669
2670 EVT FPTy = EVT::getFloatingPointVT(Val.getValueSizeInBits());
2671 SDValue Tr = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Val), FPTy,
2672 Val.getOperand(0));
2673 return DAG.getStore(SD->getChain(), SDLoc(SD), Tr, SD->getBasePtr(),
2674 SD->getPointerInfo(), SD->getAlignment(),
2675 SD->getMemOperand()->getFlags());
2676 }
2677
2678 SDValue MipsTargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2679 StoreSDNode *SD = cast<StoreSDNode>(Op);
2680 EVT MemVT = SD->getMemoryVT();
2681
2682 // Lower unaligned integer stores.
2683 if (!Subtarget.systemSupportsUnalignedAccess() &&
2684 (SD->getAlignment() < MemVT.getSizeInBits() / 8) &&
2685 ((MemVT == MVT::i32) || (MemVT == MVT::i64)))
2686 return lowerUnalignedIntStore(SD, DAG, Subtarget.isLittle());
2687
2688 return lowerFP_TO_SINT_STORE(SD, DAG, Subtarget.isSingleFloat());
2689 }
2690
2691 SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op,
2692 SelectionDAG &DAG) const {
2693
2694 // Return a fixed StackObject with offset 0 which points to the old stack
2695 // pointer.
2696 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2697 EVT ValTy = Op->getValueType(0);
2698 int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false);
2699 return DAG.getFrameIndex(FI, ValTy);
2700 }
2701
2702 SDValue MipsTargetLowering::lowerFP_TO_SINT(SDValue Op,
2703 SelectionDAG &DAG) const {
2704 if (Op.getValueSizeInBits() > 32 && Subtarget.isSingleFloat())
2705 return SDValue();
2706
2707 EVT FPTy = EVT::getFloatingPointVT(Op.getValueSizeInBits());
2708 SDValue Trunc = DAG.getNode(MipsISD::TruncIntFP, SDLoc(Op), FPTy,
2709 Op.getOperand(0));
2710 return DAG.getNode(ISD::BITCAST, SDLoc(Op), Op.getValueType(), Trunc);
2711 }
2712
2713 //===----------------------------------------------------------------------===//
2714 // Calling Convention Implementation
2715 //===----------------------------------------------------------------------===//
2716
2717 //===----------------------------------------------------------------------===//
2718 // TODO: Implement a generic logic using tblgen that can support this.
2719 // Mips O32 ABI rules:
2720 // ---
2721 // i32 - Passed in A0, A1, A2, A3 and stack
2722 // f32 - Only passed in f32 registers if no int reg has been used yet to hold
2723 // an argument. Otherwise, passed in A1, A2, A3 and stack.
2724 // f64 - Only passed in two aliased f32 registers if no int reg has been used
2725 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
2726 // not used, it must be shadowed. If only A3 is available, shadow it and
2727 // go to stack.
2728 // vXiX - Received as scalarized i32s, passed in A0 - A3 and the stack.
2729 // vXf32 - Passed in either a pair of registers {A0, A1}, {A2, A3} or {A0 - A3}
2730 // with the remainder spilled to the stack.
2731 // vXf64 - Passed in either {A0, A1, A2, A3} or {A2, A3} and in both cases
2732 // spilling the remainder to the stack.
2733 //
2734 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack.
2735 //===----------------------------------------------------------------------===//
2736
2737 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2738 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2739 CCState &State, ArrayRef<MCPhysReg> F64Regs) {
2740 const MipsSubtarget &Subtarget = static_cast<const MipsSubtarget &>(
2741 State.getMachineFunction().getSubtarget());
2742
2743 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2744
2745 const MipsCCState * MipsState = static_cast<MipsCCState *>(&State);
2746
2747 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
2748
2749 static const MCPhysReg FloatVectorIntRegs[] = { Mips::A0, Mips::A2 };
2750
2751 // Do not process byval args here.
2752 if (ArgFlags.isByVal())
2753 return true;
2754
2755 // Promote i8 and i16
2756 if (ArgFlags.isInReg() && !Subtarget.isLittle()) {
2757 if (LocVT == MVT::i8 || LocVT == MVT::i16 || LocVT == MVT::i32) {
2758 LocVT = MVT::i32;
2759 if (ArgFlags.isSExt())
2760 LocInfo = CCValAssign::SExtUpper;
2761 else if (ArgFlags.isZExt())
2762 LocInfo = CCValAssign::ZExtUpper;
2763 else
2764 LocInfo = CCValAssign::AExtUpper;
2765 }
2766 }
2767
2768 // Promote i8 and i16
2769 if (LocVT == MVT::i8 || LocVT == MVT::i16) {
2770 LocVT = MVT::i32;
2771 if (ArgFlags.isSExt())
2772 LocInfo = CCValAssign::SExt;
2773 else if (ArgFlags.isZExt())
2774 LocInfo = CCValAssign::ZExt;
2775 else
2776 LocInfo = CCValAssign::AExt;
2777 }
2778
2779 unsigned Reg;
2780
2781 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following
2782 // is true: function is vararg, argument is 3rd or higher, there is previous
2783 // argument which is not f32 or f64.
2784 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 ||
2785 State.getFirstUnallocated(F32Regs) != ValNo;
2786 unsigned OrigAlign = ArgFlags.getOrigAlign();
2787 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8);
2788 bool isVectorFloat = MipsState->WasOriginalArgVectorFloat(ValNo);
2789
2790 // The MIPS vector ABI for floats passes them in a pair of registers
2791 if (ValVT == MVT::i32 && isVectorFloat) {
2792 // This is the start of an vector that was scalarized into an unknown number
2793 // of components. It doesn't matter how many there are. Allocate one of the
2794 // notional 8 byte aligned registers which map onto the argument stack, and
2795 // shadow the register lost to alignment requirements.
2796 if (ArgFlags.isSplit()) {
2797 Reg = State.AllocateReg(FloatVectorIntRegs);
2798 if (Reg == Mips::A2)
2799 State.AllocateReg(Mips::A1);
2800 else if (Reg == 0)
2801 State.AllocateReg(Mips::A3);
2802 } else {
2803 // If we're an intermediate component of the split, we can just attempt to
2804 // allocate a register directly.
2805 Reg = State.AllocateReg(IntRegs);
2806 }
2807 } else if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) {
2808 Reg = State.AllocateReg(IntRegs);
2809 // If this is the first part of an i64 arg,
2810 // the allocated register must be either A0 or A2.
2811 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3))
2812 Reg = State.AllocateReg(IntRegs);
2813 LocVT = MVT::i32;
2814 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) {
2815 // Allocate int register and shadow next int register. If first
2816 // available register is Mips::A1 or Mips::A3, shadow it too.
2817 Reg = State.AllocateReg(IntRegs);
2818 if (Reg == Mips::A1 || Reg == Mips::A3)
2819 Reg = State.AllocateReg(IntRegs);
2820 State.AllocateReg(IntRegs);
2821 LocVT = MVT::i32;
2822 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) {
2823 // we are guaranteed to find an available float register
2824 if (ValVT == MVT::f32) {
2825 Reg = State.AllocateReg(F32Regs);
2826 // Shadow int register
2827 State.AllocateReg(IntRegs);
2828 } else {
2829 Reg = State.AllocateReg(F64Regs);
2830 // Shadow int registers
2831 unsigned Reg2 = State.AllocateReg(IntRegs);
2832 if (Reg2 == Mips::A1 || Reg2 == Mips::A3)
2833 State.AllocateReg(IntRegs);
2834 State.AllocateReg(IntRegs);
2835 }
2836 } else
2837 llvm_unreachable("Cannot handle this ValVT.");
2838
2839 if (!Reg) {
2840 unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign);
2841 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
2842 } else
2843 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
2844
2845 return false;
2846 }
2847
2848 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
2849 MVT LocVT, CCValAssign::LocInfo LocInfo,
2850 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2851 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
2852
2853 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2854 }
2855
2856 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
2857 MVT LocVT, CCValAssign::LocInfo LocInfo,
2858 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2859 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2860
2861 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
2862 }
2863
2864 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
2865 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2866 CCState &State) LLVM_ATTRIBUTE_UNUSED;
2867
2868 #include "MipsGenCallingConv.inc"
2869
2870 CCAssignFn *MipsTargetLowering::CCAssignFnForCall() const{
2871 return CC_Mips_FixedArg;
2872 }
2873
2874 CCAssignFn *MipsTargetLowering::CCAssignFnForReturn() const{
2875 return RetCC_Mips;
2876 }
2877 //===----------------------------------------------------------------------===//
2878 // Call Calling Convention Implementation
2879 //===----------------------------------------------------------------------===//
2880
2881 // Return next O32 integer argument register.
2882 static unsigned getNextIntArgReg(unsigned Reg) {
2883 assert((Reg == Mips::A0) || (Reg == Mips::A2));
2884 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3;
2885 }
2886
2887 SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset,
2888 SDValue Chain, SDValue Arg,
2889 const SDLoc &DL, bool IsTailCall,
2890 SelectionDAG &DAG) const {
2891 if (!IsTailCall) {
2892 SDValue PtrOff =
2893 DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), StackPtr,
2894 DAG.getIntPtrConstant(Offset, DL));
2895 return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo());
2896 }
2897
2898 MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
2899 int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false);
2900 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2901 return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(),
2902 /* Alignment = */ 0, MachineMemOperand::MOVolatile);
2903 }
2904
2905 void MipsTargetLowering::
2906 getOpndList(SmallVectorImpl<SDValue> &Ops,
2907 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
2908 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
2909 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
2910 SDValue Chain) const {
2911 // Insert node "GP copy globalreg" before call to function.
2912 //
2913 // R_MIPS_CALL* operators (emitted when non-internal functions are called
2914 // in PIC mode) allow symbols to be resolved via lazy binding.
2915 // The lazy binding stub requires GP to point to the GOT.
2916 // Note that we don't need GP to point to the GOT for indirect calls
2917 // (when R_MIPS_CALL* is not used for the call) because Mips linker generates
2918 // lazy binding stub for a function only when R_MIPS_CALL* are the only relocs
2919 // used for the function (that is, Mips linker doesn't generate lazy binding
2920 // stub for a function whose address is taken in the program).
2921 if (IsPICCall && !InternalLinkage && IsCallReloc) {
2922 unsigned GPReg = ABI.IsN64() ? Mips::GP_64 : Mips::GP;
2923 EVT Ty = ABI.IsN64() ? MVT::i64 : MVT::i32;
2924 RegsToPass.push_back(std::make_pair(GPReg, getGlobalReg(CLI.DAG, Ty)));
2925 }
2926
2927 // Build a sequence of copy-to-reg nodes chained together with token
2928 // chain and flag operands which copy the outgoing args into registers.
2929 // The InFlag in necessary since all emitted instructions must be
2930 // stuck together.
2931 SDValue InFlag;
2932
2933 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2934 Chain = CLI.DAG.getCopyToReg(Chain, CLI.DL, RegsToPass[i].first,
2935 RegsToPass[i].second, InFlag);
2936 InFlag = Chain.getValue(1);
2937 }
2938
2939 // Add argument registers to the end of the list so that they are
2940 // known live into the call.
2941 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2942 Ops.push_back(CLI.DAG.getRegister(RegsToPass[i].first,
2943 RegsToPass[i].second.getValueType()));
2944
2945 // Add a register mask operand representing the call-preserved registers.
2946 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2947 const uint32_t *Mask =
2948 TRI->getCallPreservedMask(CLI.DAG.getMachineFunction(), CLI.CallConv);
2949 assert(Mask && "Missing call preserved mask for calling convention");
2950 if (Subtarget.inMips16HardFloat()) {
2951 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(CLI.Callee)) {
2952 StringRef Sym = G->getGlobal()->getName();
2953 Function *F = G->getGlobal()->getParent()->getFunction(Sym);
2954 if (F && F->hasFnAttribute("__Mips16RetHelper")) {
2955 Mask = MipsRegisterInfo::getMips16RetHelperMask();
2956 }
2957 }
2958 }
2959 Ops.push_back(CLI.DAG.getRegisterMask(Mask));
2960
2961 if (InFlag.getNode())
2962 Ops.push_back(InFlag);
2963 }
2964
2965 void MipsTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
2966 SDNode *Node) const {
2967 switch (MI.getOpcode()) {
2968 default:
2969 return;
2970 case Mips::JALR:
2971 case Mips::JALRPseudo:
2972 case Mips::JALR64:
2973 case Mips::JALR64Pseudo:
2974 case Mips::JALR16_MM:
2975 case Mips::JALRC16_MMR6:
2976 case Mips::TAILCALLREG:
2977 case Mips::TAILCALLREG64:
2978 case Mips::TAILCALLR6REG:
2979 case Mips::TAILCALL64R6REG:
2980 case Mips::TAILCALLREG_MM:
2981 case Mips::TAILCALLREG_MMR6: {
2982 if (!EmitJalrReloc ||
2983 Subtarget.inMips16Mode() ||
2984 !isPositionIndependent() ||
2985 Node->getNumOperands() < 1 ||
2986 Node->getOperand(0).getNumOperands() < 2) {
2987 return;
2988 }
2989 // We are after the callee address, set by LowerCall().
2990 // If added to MI, asm printer will emit .reloc R_MIPS_JALR for the
2991 // symbol.
2992 const SDValue TargetAddr = Node->getOperand(0).getOperand(1);
2993 StringRef Sym;
2994 if (const GlobalAddressSDNode *G =
2995 dyn_cast_or_null<const GlobalAddressSDNode>(TargetAddr)) {
2996 Sym = G->getGlobal()->getName();
2997 }
2998 else if (const ExternalSymbolSDNode *ES =
2999 dyn_cast_or_null<const ExternalSymbolSDNode>(TargetAddr)) {
3000 Sym = ES->getSymbol();
3001 }
3002
3003 if (Sym.empty())
3004 return;
3005
3006 MachineFunction *MF = MI.getParent()->getParent();
3007 MCSymbol *S = MF->getContext().getOrCreateSymbol(Sym);
3008 MI.addOperand(MachineOperand::CreateMCSymbol(S, MipsII::MO_JALR));
3009 }
3010 }
3011 }
3012
3013 /// LowerCall - functions arguments are copied from virtual regs to
3014 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
3015 SDValue
3016 MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3017 SmallVectorImpl<SDValue> &InVals) const {
3018 SelectionDAG &DAG = CLI.DAG;
3019 SDLoc DL = CLI.DL;
3020 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3021 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3022 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3023 SDValue Chain = CLI.Chain;
3024 SDValue Callee = CLI.Callee;
3025 bool &IsTailCall = CLI.IsTailCall;
3026 CallingConv::ID CallConv = CLI.CallConv;
3027 bool IsVarArg = CLI.IsVarArg;
3028
3029 MachineFunction &MF = DAG.getMachineFunction();
3030 MachineFrameInfo &MFI = MF.getFrameInfo();
3031 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
3032 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
3033 bool IsPIC = isPositionIndependent();
3034
3035 // Analyze operands of the call, assigning locations to each operand.
3036 SmallVector<CCValAssign, 16> ArgLocs;
3037 MipsCCState CCInfo(
3038 CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, *DAG.getContext(),
3039 MipsCCState::getSpecialCallingConvForCallee(Callee.getNode(), Subtarget));
3040
3041 const ExternalSymbolSDNode *ES =
3042 dyn_cast_or_null<const ExternalSymbolSDNode>(Callee.getNode());
3043
3044 // There is one case where CALLSEQ_START..CALLSEQ_END can be nested, which
3045 // is during the lowering of a call with a byval argument which produces
3046 // a call to memcpy. For the O32 case, this causes the caller to allocate
3047 // stack space for the reserved argument area for the callee, then recursively
3048 // again for the memcpy call. In the NEWABI case, this doesn't occur as those
3049 // ABIs mandate that the callee allocates the reserved argument area. We do
3050 // still produce nested CALLSEQ_START..CALLSEQ_END with zero space though.
3051 //
3052 // If the callee has a byval argument and memcpy is used, we are mandated
3053 // to already have produced a reserved argument area for the callee for O32.
3054 // Therefore, the reserved argument area can be reused for both calls.
3055 //
3056 // Other cases of calling memcpy cannot have a chain with a CALLSEQ_START
3057 // present, as we have yet to hook that node onto the chain.
3058 //
3059 // Hence, the CALLSEQ_START and CALLSEQ_END nodes can be eliminated in this
3060 // case. GCC does a similar trick, in that wherever possible, it calculates
3061 // the maximum out going argument area (including the reserved area), and
3062 // preallocates the stack space on entrance to the caller.
3063 //
3064 // FIXME: We should do the same for efficiency and space.
3065
3066 // Note: The check on the calling convention below must match
3067 // MipsABIInfo::GetCalleeAllocdArgSizeInBytes().
3068 bool MemcpyInByVal = ES &&
3069 StringRef(ES->getSymbol()) == StringRef("memcpy") &&
3070 CallConv != CallingConv::Fast &&
3071 Chain.getOpcode() == ISD::CALLSEQ_START;
3072
3073 // Allocate the reserved argument area. It seems strange to do this from the
3074 // caller side but removing it breaks the frame size calculation.
3075 unsigned ReservedArgArea =
3076 MemcpyInByVal ? 0 : ABI.GetCalleeAllocdArgSizeInBytes(CallConv);
3077 CCInfo.AllocateStack(ReservedArgArea, 1);
3078
3079 CCInfo.AnalyzeCallOperands(Outs, CC_Mips, CLI.getArgs(),
3080 ES ? ES->getSymbol() : nullptr);
3081
3082 // Get a count of how many bytes are to be pushed on the stack.
3083 unsigned NextStackOffset = CCInfo.getNextStackOffset();
3084
3085 // Check if it's really possible to do a tail call. Restrict it to functions
3086 // that are part of this compilation unit.
3087 bool InternalLinkage = false;
3088 if (IsTailCall) {
3089 IsTailCall = isEligibleForTailCallOptimization(
3090 CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>());
3091 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3092 InternalLinkage = G->getGlobal()->hasInternalLinkage();
3093 IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() ||
3094 G->getGlobal()->hasPrivateLinkage() ||
3095 G->getGlobal()->hasHiddenVisibility() ||
3096 G->getGlobal()->hasProtectedVisibility());
3097 }
3098 }
3099 if (!IsTailCall && CLI.CS && CLI.CS.isMustTailCall())
3100 report_fatal_error("failed to perform tail call elimination on a call "
3101 "site marked musttail");
3102
3103 if (IsTailCall)
3104 ++NumTailCalls;
3105
3106 // Chain is the output chain of the last Load/Store or CopyToReg node.
3107 // ByValChain is the output chain of the last Memcpy node created for copying
3108 // byval arguments to the stack.
3109 unsigned StackAlignment = TFL->getStackAlignment();
3110 NextStackOffset = alignTo(NextStackOffset, StackAlignment);
3111 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, DL, true);
3112
3113 if (!(IsTailCall || MemcpyInByVal))
3114 Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL);
3115
3116 SDValue StackPtr =
3117 DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP,
3118 getPointerTy(DAG.getDataLayout()));
3119
3120 std::deque<std::pair<unsigned, SDValue>> RegsToPass;
3121 SmallVector<SDValue, 8> MemOpChains;
3122
3123 CCInfo.rewindByValRegsInfo();
3124
3125 // Walk the register/memloc assignments, inserting copies/loads.
3126 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3127 SDValue Arg = OutVals[i];
3128 CCValAssign &VA = ArgLocs[i];
3129 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT();
3130 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3131 bool UseUpperBits = false;
3132
3133 // ByVal Arg.
3134 if (Flags.isByVal()) {
3135 unsigned FirstByValReg, LastByValReg;
3136 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3137 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3138
3139 assert(Flags.getByValSize() &&
3140 "ByVal args of size 0 should have been ignored by front-end.");
3141 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3142 assert(!IsTailCall &&
3143 "Do not tail-call optimize if there is a byval argument.");
3144 passByValArg(Chain, DL, RegsToPass, MemOpChains, StackPtr, MFI, DAG, Arg,
3145 FirstByValReg, LastByValReg, Flags, Subtarget.isLittle(),
3146 VA);
3147 CCInfo.nextInRegsParam();
3148 continue;
3149 }
3150
3151 // Promote the value if needed.
3152 switch (VA.getLocInfo()) {
3153 default:
3154 llvm_unreachable("Unknown loc info!");
3155 case CCValAssign::Full:
3156 if (VA.isRegLoc()) {
3157 if ((ValVT == MVT::f32 && LocVT == MVT::i32) ||
3158 (ValVT == MVT::f64 && LocVT == MVT::i64) ||
3159 (ValVT == MVT::i64 && LocVT == MVT::f64))
3160 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3161 else if (ValVT == MVT::f64 && LocVT == MVT::i32) {
3162 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3163 Arg, DAG.getConstant(0, DL, MVT::i32));
3164 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
3165 Arg, DAG.getConstant(1, DL, MVT::i32));
3166 if (!Subtarget.isLittle())
3167 std::swap(Lo, Hi);
3168 Register LocRegLo = VA.getLocReg();
3169 unsigned LocRegHigh = getNextIntArgReg(LocRegLo);
3170 RegsToPass.push_back(std::make_pair(LocRegLo, Lo));
3171 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi));
3172 continue;
3173 }
3174 }
3175 break;
3176 case CCValAssign::BCvt:
3177 Arg = DAG.getNode(ISD::BITCAST, DL, LocVT, Arg);
3178 break;
3179 case CCValAssign::SExtUpper:
3180 UseUpperBits = true;
3181 LLVM_FALLTHROUGH;
3182 case CCValAssign::SExt:
3183 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg);
3184 break;
3185 case CCValAssign::ZExtUpper:
3186 UseUpperBits = true;
3187 LLVM_FALLTHROUGH;
3188 case CCValAssign::ZExt:
3189 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg);
3190 break;
3191 case CCValAssign::AExtUpper:
3192 UseUpperBits = true;
3193 LLVM_FALLTHROUGH;
3194 case CCValAssign::AExt:
3195 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg);
3196 break;
3197 }
3198
3199 if (UseUpperBits) {
3200 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3201 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3202 Arg = DAG.getNode(
3203 ISD::SHL, DL, VA.getLocVT(), Arg,
3204 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3205 }
3206
3207 // Arguments that can be passed on register must be kept at
3208 // RegsToPass vector
3209 if (VA.isRegLoc()) {
3210 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3211 continue;
3212 }
3213
3214 // Register can't get to this point...
3215 assert(VA.isMemLoc());
3216
3217 // emit ISD::STORE whichs stores the
3218 // parameter value to a stack Location
3219 MemOpChains.push_back(passArgOnStack(StackPtr, VA.getLocMemOffset(),
3220 Chain, Arg, DL, IsTailCall, DAG));
3221 }
3222
3223 // Transform all store nodes into one single node because all store
3224 // nodes are independent of each other.
3225 if (!MemOpChains.empty())
3226 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
3227
3228 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
3229 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
3230 // node so that legalize doesn't hack it.
3231
3232 EVT Ty = Callee.getValueType();
3233 bool GlobalOrExternal = false, IsCallReloc = false;
3234
3235 // The long-calls feature is ignored in case of PIC.
3236 // While we do not support -mshared / -mno-shared properly,
3237 // ignore long-calls in case of -mabicalls too.
3238 if (!Subtarget.isABICalls() && !IsPIC) {
3239 // If the function should be called using "long call",
3240 // get its address into a register to prevent using
3241 // of the `jal` instruction for the direct call.
3242 if (auto *N = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3243 if (Subtarget.useLongCalls())
3244 Callee = Subtarget.hasSym32()
3245 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3246 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3247 } else if (auto *N = dyn_cast<GlobalAddressSDNode>(Callee)) {
3248 bool UseLongCalls = Subtarget.useLongCalls();
3249 // If the function has long-call/far/near attribute
3250 // it overrides command line switch pased to the backend.
3251 if (auto *F = dyn_cast<Function>(N->getGlobal())) {
3252 if (F->hasFnAttribute("long-call"))
3253 UseLongCalls = true;
3254 else if (F->hasFnAttribute("short-call"))
3255 UseLongCalls = false;
3256 }
3257 if (UseLongCalls)
3258 Callee = Subtarget.hasSym32()
3259 ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
3260 : getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
3261 }
3262 }
3263
3264 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3265 if (IsPIC) {
3266 const GlobalValue *Val = G->getGlobal();
3267 InternalLinkage = Val->hasInternalLinkage();
3268
3269 if (InternalLinkage)
3270 Callee = getAddrLocal(G, DL, Ty, DAG, ABI.IsN32() || ABI.IsN64());
3271 else if (Subtarget.useXGOT()) {
3272 Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3273 MipsII::MO_CALL_LO16, Chain,
3274 FuncInfo->callPtrInfo(Val));
3275 IsCallReloc = true;
3276 } else {
3277 Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3278 FuncInfo->callPtrInfo(Val));
3279 IsCallReloc = true;
3280 }
3281 } else
3282 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL,
3283 getPointerTy(DAG.getDataLayout()), 0,
3284 MipsII::MO_NO_FLAG);
3285 GlobalOrExternal = true;
3286 }
3287 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3288 const char *Sym = S->getSymbol();
3289
3290 if (!IsPIC) // static
3291 Callee = DAG.getTargetExternalSymbol(
3292 Sym, getPointerTy(DAG.getDataLayout()), MipsII::MO_NO_FLAG);
3293 else if (Subtarget.useXGOT()) {
3294 Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16,
3295 MipsII::MO_CALL_LO16, Chain,
3296 FuncInfo->callPtrInfo(Sym));
3297 IsCallReloc = true;
3298 } else { // PIC
3299 Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain,
3300 FuncInfo->callPtrInfo(Sym));
3301 IsCallReloc = true;
3302 }
3303
3304 GlobalOrExternal = true;
3305 }
3306
3307 SmallVector<SDValue, 8> Ops(1, Chain);
3308 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
3309
3310 getOpndList(Ops, RegsToPass, IsPIC, GlobalOrExternal, InternalLinkage,
3311 IsCallReloc, CLI, Callee, Chain);
3312
3313 if (IsTailCall) {
3314 MF.getFrameInfo().setHasTailCall();
3315 return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops);
3316 }
3317
3318 Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops);
3319 SDValue InFlag = Chain.getValue(1);
3320
3321 // Create the CALLSEQ_END node in the case of where it is not a call to
3322 // memcpy.
3323 if (!(MemcpyInByVal)) {
3324 Chain = DAG.getCALLSEQ_END(Chain, NextStackOffsetVal,
3325 DAG.getIntPtrConstant(0, DL, true), InFlag, DL);
3326 InFlag = Chain.getValue(1);
3327 }
3328
3329 // Handle result values, copying them out of physregs into vregs that we
3330 // return.
3331 return LowerCallResult(Chain, InFlag, CallConv, IsVarArg, Ins, DL, DAG,
3332 InVals, CLI);
3333 }
3334
3335 /// LowerCallResult - Lower the result values of a call into the
3336 /// appropriate copies out of appropriate physical registers.
3337 SDValue MipsTargetLowering::LowerCallResult(
3338 SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg,
3339 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3340 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
3341 TargetLowering::CallLoweringInfo &CLI) const {
3342 // Assign locations to each value returned by this call.
3343 SmallVector<CCValAssign, 16> RVLocs;
3344 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
3345 *DAG.getContext());
3346
3347 const ExternalSymbolSDNode *ES =
3348 dyn_cast_or_null<const ExternalSymbolSDNode>(CLI.Callee.getNode());
3349 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips, CLI.RetTy,
3350 ES ? ES->getSymbol() : nullptr);
3351
3352 // Copy all of the result registers out of their specified physreg.
3353 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3354 CCValAssign &VA = RVLocs[i];
3355 assert(VA.isRegLoc() && "Can only return in registers!");
3356
3357 SDValue Val = DAG.getCopyFromReg(Chain, DL, RVLocs[i].getLocReg(),
3358 RVLocs[i].getLocVT(), InFlag);
3359 Chain = Val.getValue(1);
3360 InFlag = Val.getValue(2);
3361
3362 if (VA.isUpperBitsInLoc()) {
3363 unsigned ValSizeInBits = Ins[i].ArgVT.getSizeInBits();
3364 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3365 unsigned Shift =
3366 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3367 Val = DAG.getNode(
3368 Shift, DL, VA.getLocVT(), Val,
3369 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3370 }
3371
3372 switch (VA.getLocInfo()) {
3373 default:
3374 llvm_unreachable("Unknown loc info!");
3375 case CCValAssign::Full:
3376 break;
3377 case CCValAssign::BCvt:
3378 Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);
3379 break;
3380 case CCValAssign::AExt:
3381 case CCValAssign::AExtUpper:
3382 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3383 break;
3384 case CCValAssign::ZExt:
3385 case CCValAssign::ZExtUpper:
3386 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val,
3387 DAG.getValueType(VA.getValVT()));
3388 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3389 break;
3390 case CCValAssign::SExt:
3391 case CCValAssign::SExtUpper:
3392 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val,
3393 DAG.getValueType(VA.getValVT()));
3394 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val);
3395 break;
3396 }
3397
3398 InVals.push_back(Val);
3399 }
3400
3401 return Chain;
3402 }
3403
3404 static SDValue UnpackFromArgumentSlot(SDValue Val, const CCValAssign &VA,
3405 EVT ArgVT, const SDLoc &DL,
3406 SelectionDAG &DAG) {
3407 MVT LocVT = VA.getLocVT();
3408 EVT ValVT = VA.getValVT();
3409
3410 // Shift into the upper bits if necessary.
3411 switch (VA.getLocInfo()) {
3412 default:
3413 break;
3414 case CCValAssign::AExtUpper:
3415 case CCValAssign::SExtUpper:
3416 case CCValAssign::ZExtUpper: {
3417 unsigned ValSizeInBits = ArgVT.getSizeInBits();
3418 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3419 unsigned Opcode =
3420 VA.getLocInfo() == CCValAssign::ZExtUpper ? ISD::SRL : ISD::SRA;
3421 Val = DAG.getNode(
3422 Opcode, DL, VA.getLocVT(), Val,
3423 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3424 break;
3425 }
3426 }
3427
3428 // If this is an value smaller than the argument slot size (32-bit for O32,
3429 // 64-bit for N32/N64), it has been promoted in some way to the argument slot
3430 // size. Extract the value and insert any appropriate assertions regarding
3431 // sign/zero extension.
3432 switch (VA.getLocInfo()) {
3433 default:
3434 llvm_unreachable("Unknown loc info!");
3435 case CCValAssign::Full:
3436 break;
3437 case CCValAssign::AExtUpper:
3438 case CCValAssign::AExt:
3439 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3440 break;
3441 case CCValAssign::SExtUpper:
3442 case CCValAssign::SExt:
3443 Val = DAG.getNode(ISD::AssertSext, DL, LocVT, Val, DAG.getValueType(ValVT));
3444 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3445 break;
3446 case CCValAssign::ZExtUpper:
3447 case CCValAssign::ZExt:
3448 Val = DAG.getNode(ISD::AssertZext, DL, LocVT, Val, DAG.getValueType(ValVT));
3449 Val = DAG.getNode(ISD::TRUNCATE, DL, ValVT, Val);
3450 break;
3451 case CCValAssign::BCvt:
3452 Val = DAG.getNode(ISD::BITCAST, DL, ValVT, Val);
3453 break;
3454 }
3455
3456 return Val;
3457 }
3458
3459 //===----------------------------------------------------------------------===//
3460 // Formal Arguments Calling Convention Implementation
3461 //===----------------------------------------------------------------------===//
3462 /// LowerFormalArguments - transform physical registers into virtual registers
3463 /// and generate load operations for arguments places on the stack.
3464 SDValue MipsTargetLowering::LowerFormalArguments(
3465 SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
3466 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
3467 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
3468 MachineFunction &MF = DAG.getMachineFunction();
3469 MachineFrameInfo &MFI = MF.getFrameInfo();
3470 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3471
3472 MipsFI->setVarArgsFrameIndex(0);
3473
3474 // Used with vargs to acumulate store chains.
3475 std::vector<SDValue> OutChains;
3476
3477 // Assign locations to all of the incoming arguments.
3478 SmallVector<CCValAssign, 16> ArgLocs;
3479 MipsCCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
3480 *DAG.getContext());
3481 CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
3482 const Function &Func = DAG.getMachineFunction().getFunction();
3483 Function::const_arg_iterator FuncArg = Func.arg_begin();
3484
3485 if (Func.hasFnAttribute("interrupt") && !Func.arg_empty())
3486 report_fatal_error(
3487 "Functions with the interrupt attribute cannot have arguments!");
3488
3489 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips_FixedArg);
3490 MipsFI->setFormalArgInfo(CCInfo.getNextStackOffset(),
3491 CCInfo.getInRegsParamsCount() > 0);
3492
3493 unsigned CurArgIdx = 0;
3494 CCInfo.rewindByValRegsInfo();
3495
3496 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3497 CCValAssign &VA = ArgLocs[i];
3498 if (Ins[i].isOrigArg()) {
3499 std::advance(FuncArg, Ins[i].getOrigArgIndex() - CurArgIdx);
3500 CurArgIdx = Ins[i].getOrigArgIndex();
3501 }
3502 EVT ValVT = VA.getValVT();
3503 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3504 bool IsRegLoc = VA.isRegLoc();
3505
3506 if (Flags.isByVal()) {
3507 assert(Ins[i].isOrigArg() && "Byval arguments cannot be implicit");
3508 unsigned FirstByValReg, LastByValReg;
3509 unsigned ByValIdx = CCInfo.getInRegsParamsProcessed();
3510 CCInfo.getInRegsParamInfo(ByValIdx, FirstByValReg, LastByValReg);
3511
3512 assert(Flags.getByValSize() &&
3513 "ByVal args of size 0 should have been ignored by front-end.");
3514 assert(ByValIdx < CCInfo.getInRegsParamsCount());
3515 copyByValRegs(Chain, DL, OutChains, DAG, Flags, InVals, &*FuncArg,
3516 FirstByValReg, LastByValReg, VA, CCInfo);
3517 CCInfo.nextInRegsParam();
3518 continue;
3519 }
3520
3521 // Arguments stored on registers
3522 if (IsRegLoc) {
3523 MVT RegVT = VA.getLocVT();
3524 Register ArgReg = VA.getLocReg();
3525 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3526
3527 // Transform the arguments stored on
3528 // physical registers into virtual ones
3529 unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3530 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT);
3531
3532 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3533
3534 // Handle floating point arguments passed in integer registers and
3535 // long double arguments passed in floating point registers.
3536 if ((RegVT == MVT::i32 && ValVT == MVT::f32) ||
3537 (RegVT == MVT::i64 && ValVT == MVT::f64) ||
3538 (RegVT == MVT::f64 && ValVT == MVT::i64))
3539 ArgValue = DAG.getNode(ISD::BITCAST, DL, ValVT, ArgValue);
3540 else if (ABI.IsO32() && RegVT == MVT::i32 &&
3541 ValVT == MVT::f64) {
3542 unsigned Reg2 = addLiveIn(DAG.getMachineFunction(),
3543 getNextIntArgReg(ArgReg), RC);
3544 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, DL, Reg2, RegVT);
3545 if (!Subtarget.isLittle())
3546 std::swap(ArgValue, ArgValue2);
3547 ArgValue = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64,
3548 ArgValue, ArgValue2);
3549 }
3550
3551 InVals.push_back(ArgValue);
3552 } else { // VA.isRegLoc()
3553 MVT LocVT = VA.getLocVT();
3554
3555 if (ABI.IsO32()) {
3556 // We ought to be able to use LocVT directly but O32 sets it to i32
3557 // when allocating floating point values to integer registers.
3558 // This shouldn't influence how we load the value into registers unless
3559 // we are targeting softfloat.
3560 if (VA.getValVT().isFloatingPoint() && !Subtarget.useSoftFloat())
3561 LocVT = VA.getValVT();
3562 }
3563
3564 // sanity check
3565 assert(VA.isMemLoc());
3566
3567 // The stack pointer offset is relative to the caller stack frame.
3568 int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8,
3569 VA.getLocMemOffset(), true);
3570
3571 // Create load nodes to retrieve arguments from the stack
3572 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3573 SDValue ArgValue = DAG.getLoad(
3574 LocVT, DL, Chain, FIN,
3575 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
3576 OutChains.push_back(ArgValue.getValue(1));
3577
3578 ArgValue = UnpackFromArgumentSlot(ArgValue, VA, Ins[i].ArgVT, DL, DAG);
3579
3580 InVals.push_back(ArgValue);
3581 }
3582 }
3583
3584 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3585 // The mips ABIs for returning structs by value requires that we copy
3586 // the sret argument into $v0 for the return. Save the argument into
3587 // a virtual register so that we can access it from the return points.
3588 if (Ins[i].Flags.isSRet()) {
3589 unsigned Reg = MipsFI->getSRetReturnReg();
3590 if (!Reg) {
3591 Reg = MF.getRegInfo().createVirtualRegister(
3592 getRegClassFor(ABI.IsN64() ? MVT::i64 : MVT::i32));
3593 MipsFI->setSRetReturnReg(Reg);
3594 }
3595 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]);
3596 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain);
3597 break;
3598 }
3599 }
3600
3601 if (IsVarArg)
3602 writeVarArgRegs(OutChains, Chain, DL, DAG, CCInfo);
3603
3604 // All stores are grouped in one node to allow the matching between
3605 // the size of Ins and InVals. This only happens when on varg functions
3606 if (!OutChains.empty()) {
3607 OutChains.push_back(Chain);
3608 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
3609 }
3610
3611 return Chain;
3612 }
3613
3614 //===----------------------------------------------------------------------===//
3615 // Return Value Calling Convention Implementation
3616 //===----------------------------------------------------------------------===//
3617
3618 bool
3619 MipsTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3620 MachineFunction &MF, bool IsVarArg,
3621 const SmallVectorImpl<ISD::OutputArg> &Outs,
3622 LLVMContext &Context) const {
3623 SmallVector<CCValAssign, 16> RVLocs;
3624 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
3625 return CCInfo.CheckReturn(Outs, RetCC_Mips);
3626 }
3627
3628 bool
3629 MipsTargetLowering::shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
3630 if ((ABI.IsN32() || ABI.IsN64()) && Type == MVT::i32)
3631 return true;
3632
3633 return IsSigned;
3634 }
3635
3636 SDValue
3637 MipsTargetLowering::LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
3638 const SDLoc &DL,
3639 SelectionDAG &DAG) const {
3640 MachineFunction &MF = DAG.getMachineFunction();
3641 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3642
3643 MipsFI->setISR();
3644
3645 return DAG.getNode(MipsISD::ERet, DL, MVT::Other, RetOps);
3646 }
3647
3648 SDValue
3649 MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3650 bool IsVarArg,
3651 const SmallVectorImpl<ISD::OutputArg> &Outs,
3652 const SmallVectorImpl<SDValue> &OutVals,
3653 const SDLoc &DL, SelectionDAG &DAG) const {
3654 // CCValAssign - represent the assignment of
3655 // the return value to a location
3656 SmallVector<CCValAssign, 16> RVLocs;
3657 MachineFunction &MF = DAG.getMachineFunction();
3658
3659 // CCState - Info about the registers and stack slot.
3660 MipsCCState CCInfo(CallConv, IsVarArg, MF, RVLocs, *DAG.getContext());
3661
3662 // Analyze return values.
3663 CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
3664
3665 SDValue Flag;
3666 SmallVector<SDValue, 4> RetOps(1, Chain);
3667
3668 // Copy the result values into the output registers.
3669 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3670 SDValue Val = OutVals[i];
3671 CCValAssign &VA = RVLocs[i];
3672 assert(VA.isRegLoc() && "Can only return in registers!");
3673 bool UseUpperBits = false;
3674
3675 switch (VA.getLocInfo()) {
3676 default:
3677 llvm_unreachable("Unknown loc info!");
3678 case CCValAssign::Full:
3679 break;
3680 case CCValAssign::BCvt:
3681 Val = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Val);
3682 break;
3683 case CCValAssign::AExtUpper:
3684 UseUpperBits = true;
3685 LLVM_FALLTHROUGH;
3686 case CCValAssign::AExt:
3687 Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val);
3688 break;
3689 case CCValAssign::ZExtUpper:
3690 UseUpperBits = true;
3691 LLVM_FALLTHROUGH;
3692 case CCValAssign::ZExt:
3693 Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val);
3694 break;
3695 case CCValAssign::SExtUpper:
3696 UseUpperBits = true;
3697 LLVM_FALLTHROUGH;
3698 case CCValAssign::SExt:
3699 Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val);
3700 break;
3701 }
3702
3703 if (UseUpperBits) {
3704 unsigned ValSizeInBits = Outs[i].ArgVT.getSizeInBits();
3705 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits();
3706 Val = DAG.getNode(
3707 ISD::SHL, DL, VA.getLocVT(), Val,
3708 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT()));
3709 }
3710
3711 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Flag);
3712
3713 // Guarantee that all emitted copies are stuck together with flags.
3714 Flag = Chain.getValue(1);
3715 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
3716 }
3717
3718 // The mips ABIs for returning structs by value requires that we copy
3719 // the sret argument into $v0 for the return. We saved the argument into
3720 // a virtual register in the entry block, so now we copy the value out
3721 // and into $v0.
3722 if (MF.getFunction().hasStructRetAttr()) {
3723 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
3724 unsigned Reg = MipsFI->getSRetReturnReg();
3725
3726 if (!Reg)
3727 llvm_unreachable("sret virtual register not created in the entry block");
3728 SDValue Val =
3729 DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy(DAG.getDataLayout()));
3730 unsigned V0 = ABI.IsN64() ? Mips::V0_64 : Mips::V0;
3731
3732 Chain = DAG.getCopyToReg(Chain, DL, V0, Val, Flag);
3733 Flag = Chain.getValue(1);
3734 RetOps.push_back(DAG.getRegister(V0, getPointerTy(DAG.getDataLayout())));
3735 }
3736
3737 RetOps[0] = Chain; // Update chain.
3738
3739 // Add the flag if we have it.
3740 if (Flag.getNode())
3741 RetOps.push_back(Flag);
3742
3743 // ISRs must use "eret".
3744 if (DAG.getMachineFunction().getFunction().hasFnAttribute("interrupt"))
3745 return LowerInterruptReturn(RetOps, DL, DAG);
3746
3747 // Standard return on Mips is a "jr $ra"
3748 return DAG.getNode(MipsISD::Ret, DL, MVT::Other, RetOps);
3749 }
3750
3751 //===----------------------------------------------------------------------===//
3752 // Mips Inline Assembly Support
3753 //===----------------------------------------------------------------------===//
3754
3755 /// getConstraintType - Given a constraint letter, return the type of
3756 /// constraint it is for this target.
3757 MipsTargetLowering::ConstraintType
3758 MipsTargetLowering::getConstraintType(StringRef Constraint) const {
3759 // Mips specific constraints
3760 // GCC config/mips/constraints.md
3761 //
3762 // 'd' : An address register. Equivalent to r
3763 // unless generating MIPS16 code.
3764 // 'y' : Equivalent to r; retained for
3765 // backwards compatibility.
3766 // 'c' : A register suitable for use in an indirect
3767 // jump. This will always be $25 for -mabicalls.
3768 // 'l' : The lo register. 1 word storage.
3769 // 'x' : The hilo register pair. Double word storage.
3770 if (Constraint.size() == 1) {
3771 switch (Constraint[0]) {
3772 default : break;
3773 case 'd':
3774 case 'y':
3775 case 'f':
3776 case 'c':
3777 case 'l':
3778 case 'x':
3779 return C_RegisterClass;
3780 case 'R':
3781 return C_Memory;
3782 }
3783 }
3784
3785 if (Constraint == "ZC")
3786 return C_Memory;
3787
3788 return TargetLowering::getConstraintType(Constraint);
3789 }
3790
3791 /// Examine constraint type and operand type and determine a weight value.
3792 /// This object must already have been set up with the operand type
3793 /// and the current alternative constraint selected.
3794 TargetLowering::ConstraintWeight
3795 MipsTargetLowering::getSingleConstraintMatchWeight(
3796 AsmOperandInfo &info, const char *constraint) const {
3797 ConstraintWeight weight = CW_Invalid;
3798 Value *CallOperandVal = info.CallOperandVal;
3799 // If we don't have a value, we can't do a match,
3800 // but allow it at the lowest weight.
3801 if (!CallOperandVal)
3802 return CW_Default;
3803 Type *type = CallOperandVal->getType();
3804 // Look at the constraint type.
3805 switch (*constraint) {
3806 default:
3807 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3808 break;
3809 case 'd':
3810 case 'y':
3811 if (type->isIntegerTy())
3812 weight = CW_Register;
3813 break;
3814 case 'f': // FPU or MSA register
3815 if (Subtarget.hasMSA() && type->isVectorTy() &&
3816 cast<VectorType>(type)->getBitWidth() == 128)
3817 weight = CW_Register;
3818 else if (type->isFloatTy())
3819 weight = CW_Register;
3820 break;
3821 case 'c': // $25 for indirect jumps
3822 case 'l': // lo register
3823 case 'x': // hilo register pair
3824 if (type->isIntegerTy())
3825 weight = CW_SpecificReg;
3826 break;
3827 case 'I': // signed 16 bit immediate
3828 case 'J': // integer zero
3829 case 'K': // unsigned 16 bit immediate
3830 case 'L': // signed 32 bit immediate where lower 16 bits are 0
3831 case 'N': // immediate in the range of -65535 to -1 (inclusive)
3832 case 'O': // signed 15 bit immediate (+- 16383)
3833 case 'P': // immediate in the range of 65535 to 1 (inclusive)
3834 if (isa<ConstantInt>(CallOperandVal))
3835 weight = CW_Constant;
3836 break;
3837 case 'R':
3838 weight = CW_Memory;
3839 break;
3840 }
3841 return weight;
3842 }
3843
3844 /// This is a helper function to parse a physical register string and split it
3845 /// into non-numeric and numeric parts (Prefix and Reg). The first boolean flag
3846 /// that is returned indicates whether parsing was successful. The second flag
3847 /// is true if the numeric part exists.
3848 static std::pair<bool, bool> parsePhysicalReg(StringRef C, StringRef &Prefix,
3849 unsigned long long &Reg) {
3850 if (C.front() != '{' || C.back() != '}')
3851 return std::make_pair(false, false);
3852
3853 // Search for the first numeric character.
3854 StringRef::const_iterator I, B = C.begin() + 1, E = C.end() - 1;
3855 I = std::find_if(B, E, isdigit);
3856
3857 Prefix = StringRef(B, I - B);
3858
3859 // The second flag is set to false if no numeric characters were found.
3860 if (I == E)
3861 return std::make_pair(true, false);
3862
3863 // Parse the numeric characters.
3864 return std::make_pair(!getAsUnsignedInteger(StringRef(I, E - I), 10, Reg),
3865 true);
3866 }
3867
3868 EVT MipsTargetLowering::getTypeForExtReturn(LLVMContext &Context, EVT VT,
3869 ISD::NodeType) const {
3870 bool Cond = !Subtarget.isABI_O32() && VT.getSizeInBits() == 32;
3871 EVT MinVT = getRegisterType(Context, Cond ? MVT::i64 : MVT::i32);
3872 return VT.bitsLT(MinVT) ? MinVT : VT;
3873 }
3874
3875 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3876 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const {
3877 const TargetRegisterInfo *TRI =
3878 Subtarget.getRegisterInfo();
3879 const TargetRegisterClass *RC;
3880 StringRef Prefix;
3881 unsigned long long Reg;
3882
3883 std::pair<bool, bool> R = parsePhysicalReg(C, Prefix, Reg);
3884
3885 if (!R.first)
3886 return std::make_pair(0U, nullptr);
3887
3888 if ((Prefix == "hi" || Prefix == "lo")) { // Parse hi/lo.
3889 // No numeric characters follow "hi" or "lo".
3890 if (R.second)
3891 return std::make_pair(0U, nullptr);
3892
3893 RC = TRI->getRegClass(Prefix == "hi" ?
3894 Mips::HI32RegClassID : Mips::LO32RegClassID);
3895 return std::make_pair(*(RC->begin()), RC);
3896 } else if (Prefix.startswith("$msa")) {
3897 // Parse $msa(ir|csr|access|save|modify|request|map|unmap)
3898
3899 // No numeric characters follow the name.
3900 if (R.second)
3901 return std::make_pair(0U, nullptr);
3902
3903 Reg = StringSwitch<unsigned long long>(Prefix)
3904 .Case("$msair", Mips::MSAIR)
3905 .Case("$msacsr", Mips::MSACSR)
3906 .Case("$msaaccess", Mips::MSAAccess)
3907 .Case("$msasave", Mips::MSASave)
3908 .Case("$msamodify", Mips::MSAModify)
3909 .Case("$msarequest", Mips::MSARequest)
3910 .Case("$msamap", Mips::MSAMap)
3911 .Case("$msaunmap", Mips::MSAUnmap)
3912 .Default(0);
3913
3914 if (!Reg)
3915 return std::make_pair(0U, nullptr);
3916
3917 RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3918 return std::make_pair(Reg, RC);
3919 }
3920
3921 if (!R.second)
3922 return std::make_pair(0U, nullptr);
3923
3924 if (Prefix == "$f") { // Parse $f0-$f31.
3925 // If the size of FP registers is 64-bit or Reg is an even number, select
3926 // the 64-bit register class. Otherwise, select the 32-bit register class.
3927 if (VT == MVT::Other)
3928 VT = (Subtarget.isFP64bit() || !(Reg % 2)) ? MVT::f64 : MVT::f32;
3929
3930 RC = getRegClassFor(VT);
3931
3932 if (RC == &Mips::AFGR64RegClass) {
3933 assert(Reg % 2 == 0);
3934 Reg >>= 1;
3935 }
3936 } else if (Prefix == "$fcc") // Parse $fcc0-$fcc7.
3937 RC = TRI->getRegClass(Mips::FCCRegClassID);
3938 else if (Prefix == "$w") { // Parse $w0-$w31.
3939 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3940 } else { // Parse $0-$31.
3941 assert(Prefix == "$");
3942 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3943 }
3944
3945 assert(Reg < RC->getNumRegs());
3946 return std::make_pair(*(RC->begin() + Reg), RC);
3947 }
3948
3949 /// Given a register class constraint, like 'r', if this corresponds directly
3950 /// to an LLVM register class, return a register of 0 and the register class
3951 /// pointer.
3952 std::pair<unsigned, const TargetRegisterClass *>
3953 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3954 StringRef Constraint,
3955 MVT VT) const {
3956 if (Constraint.size() == 1) {
3957 switch (Constraint[0]) {
3958 case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
3959 case 'y': // Same as 'r'. Exists for compatibility.
3960 case 'r':
3961 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
3962 if (Subtarget.inMips16Mode())
3963 return std::make_pair(0U, &Mips::CPU16RegsRegClass);
3964 return std::make_pair(0U, &Mips::GPR32RegClass);
3965 }
3966 if (VT == MVT::i64 && !Subtarget.isGP64bit())
3967 return std::make_pair(0U, &Mips::GPR32RegClass);
3968 if (VT == MVT::i64 && Subtarget.isGP64bit())
3969 return std::make_pair(0U, &Mips::GPR64RegClass);
3970 // This will generate an error message
3971 return std::make_pair(0U, nullptr);
3972 case 'f': // FPU or MSA register
3973 if (VT == MVT::v16i8)
3974 return std::make_pair(0U, &Mips::MSA128BRegClass);
3975 else if (VT == MVT::v8i16 || VT == MVT::v8f16)
3976 return std::make_pair(0U, &Mips::MSA128HRegClass);
3977 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
3978 return std::make_pair(0U, &Mips::MSA128WRegClass);
3979 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
3980 return std::make_pair(0U, &Mips::MSA128DRegClass);
3981 else if (VT == MVT::f32)
3982 return std::make_pair(0U, &Mips::FGR32RegClass);
3983 else if ((VT == MVT::f64) && (!Subtarget.isSingleFloat())) {
3984 if (Subtarget.isFP64bit())
3985 return std::make_pair(0U, &Mips::FGR64RegClass);
3986 return std::make_pair(0U, &Mips::AFGR64RegClass);
3987 }
3988 break;
3989 case 'c': // register suitable for indirect jump
3990 if (VT == MVT::i32)
3991 return std::make_pair((unsigned)Mips::T9, &Mips::GPR32RegClass);
3992 if (VT == MVT::i64)
3993 return std::make_pair((unsigned)Mips::T9_64, &Mips::GPR64RegClass);
3994 // This will generate an error message
3995 return std::make_pair(0U, nullptr);
3996 case 'l': // use the `lo` register to store values
3997 // that are no bigger than a word
3998 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
3999 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
4000 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
4001 case 'x': // use the concatenated `hi` and `lo` registers
4002 // to store doubleword values
4003 // Fixme: Not triggering the use of both hi and low
4004 // This will generate an error message
4005 return std::make_pair(0U, nullptr);
4006 }
4007 }
4008
4009 std::pair<unsigned, const TargetRegisterClass *> R;
4010 R = parseRegForInlineAsmConstraint(Constraint, VT);
4011
4012 if (R.second)
4013 return R;
4014
4015 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4016 }
4017
4018 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4019 /// vector. If it is invalid, don't add anything to Ops.
4020 void MipsTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4021 std::string &Constraint,
4022 std::vector<SDValue>&Ops,
4023 SelectionDAG &DAG) const {
4024 SDLoc DL(Op);
4025 SDValue Result;
4026
4027 // Only support length 1 constraints for now.
4028 if (Constraint.length() > 1) return;
4029
4030 char ConstraintLetter = Constraint[0];
4031 switch (ConstraintLetter) {
4032 default: break; // This will fall through to the generic implementation
4033 case 'I': // Signed 16 bit constant
4034 // If this fails, the parent routine will give an error
4035 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4036 EVT Type = Op.getValueType();
4037 int64_t Val = C->getSExtValue();
4038 if (isInt<16>(Val)) {
4039 Result = DAG.getTargetConstant(Val, DL, Type);
4040 break;
4041 }
4042 }
4043 return;
4044 case 'J': // integer zero
4045 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4046 EVT Type = Op.getValueType();
4047 int64_t Val = C->getZExtValue();
4048 if (Val == 0) {
4049 Result = DAG.getTargetConstant(0, DL, Type);
4050 break;
4051 }
4052 }
4053 return;
4054 case 'K': // unsigned 16 bit immediate
4055 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4056 EVT Type = Op.getValueType();
4057 uint64_t Val = (uint64_t)C->getZExtValue();
4058 if (isUInt<16>(Val)) {
4059 Result = DAG.getTargetConstant(Val, DL, Type);
4060 break;
4061 }
4062 }
4063 return;
4064 case 'L': // signed 32 bit immediate where lower 16 bits are 0
4065 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4066 EVT Type = Op.getValueType();
4067 int64_t Val = C->getSExtValue();
4068 if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
4069 Result = DAG.getTargetConstant(Val, DL, Type);
4070 break;
4071 }
4072 }
4073 return;
4074 case 'N': // immediate in the range of -65535 to -1 (inclusive)
4075 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4076 EVT Type = Op.getValueType();
4077 int64_t Val = C->getSExtValue();
4078 if ((Val >= -65535) && (Val <= -1)) {
4079 Result = DAG.getTargetConstant(Val, DL, Type);
4080 break;
4081 }
4082 }
4083 return;
4084 case 'O': // signed 15 bit immediate
4085 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4086 EVT Type = Op.getValueType();
4087 int64_t Val = C->getSExtValue();
4088 if ((isInt<15>(Val))) {
4089 Result = DAG.getTargetConstant(Val, DL, Type);
4090 break;
4091 }
4092 }
4093 return;
4094 case 'P': // immediate in the range of 1 to 65535 (inclusive)
4095 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
4096 EVT Type = Op.getValueType();
4097 int64_t Val = C->getSExtValue();
4098 if ((Val <= 65535) && (Val >= 1)) {
4099 Result = DAG.getTargetConstant(Val, DL, Type);
4100 break;
4101 }
4102 }
4103 return;
4104 }
4105
4106 if (Result.getNode()) {
4107 Ops.push_back(Result);
4108 return;
4109 }
4110
4111 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
4112 }
4113
4114 bool MipsTargetLowering::isLegalAddressingMode(const DataLayout &DL,
4115 const AddrMode &AM, Type *Ty,
4116 unsigned AS, Instruction *I) const {
4117 // No global is ever allowed as a base.
4118 if (AM.BaseGV)
4119 return false;
4120
4121 switch (AM.Scale) {
4122 case 0: // "r+i" or just "i", depending on HasBaseReg.
4123 break;
4124 case 1:
4125 if (!AM.HasBaseReg) // allow "r+i".
4126 break;
4127 return false; // disallow "r+r" or "r+r+i".
4128 default:
4129 return false;
4130 }
4131
4132 return true;
4133 }
4134
4135 bool
4136 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4137 // The Mips target isn't yet aware of offsets.
4138 return false;
4139 }
4140
4141 EVT MipsTargetLowering::getOptimalMemOpType(
4142 uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset,
4143 bool ZeroMemset, bool MemcpyStrSrc,
4144 const AttributeList &FuncAttributes) const {
4145 if (Subtarget.hasMips64())
4146 return MVT::i64;
4147
4148 return MVT::i32;
4149 }
4150
4151 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
4152 bool ForCodeSize) const {
4153 if (VT != MVT::f32 && VT != MVT::f64)
4154 return false;
4155 if (Imm.isNegZero())
4156 return false;
4157 return Imm.isZero();
4158 }
4159
4160 unsigned MipsTargetLowering::getJumpTableEncoding() const {
4161
4162 // FIXME: For space reasons this should be: EK_GPRel32BlockAddress.
4163 if (ABI.IsN64() && isPositionIndependent())
4164 return MachineJumpTableInfo::EK_GPRel64BlockAddress;
4165
4166 return TargetLowering::getJumpTableEncoding();
4167 }
4168
4169 bool MipsTargetLowering::useSoftFloat() const {
4170 return Subtarget.useSoftFloat();
4171 }
4172
4173 void MipsTargetLowering::copyByValRegs(
4174 SDValue Chain, const SDLoc &DL, std::vector<SDValue> &OutChains,
4175 SelectionDAG &DAG, const ISD::ArgFlagsTy &Flags,
4176 SmallVectorImpl<SDValue> &InVals, const Argument *FuncArg,
4177 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA,
4178 MipsCCState &State) const {
4179 MachineFunction &MF = DAG.getMachineFunction();
4180 MachineFrameInfo &MFI = MF.getFrameInfo();
4181 unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes();
4182 unsigned NumRegs = LastReg - FirstReg;
4183 unsigned RegAreaSize = NumRegs * GPRSizeInBytes;
4184 unsigned FrameObjSize = std::max(Flags.getByValSize(), RegAreaSize);
4185 int FrameObjOffset;
4186 ArrayRef<MCPhysReg> ByValArgRegs = ABI.GetByValArgRegs();
4187
4188 if (RegAreaSize)
4189 FrameObjOffset =
4190 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4191 (int)((ByValArgRegs.size() - FirstReg) * GPRSizeInBytes);
4192 else
4193 FrameObjOffset = VA.getLocMemOffset();
4194
4195 // Create frame object.
4196 EVT PtrTy = getPointerTy(DAG.getDataLayout());
4197 // Make the fixed object stored to mutable so that the load instructions
4198 // referencing it have their memory dependencies added.
4199 // Set the frame object as isAliased which clears the underlying objects
4200 // vector in ScheduleDAGInstrs::buildSchedGraph() resulting in addition of all
4201 // stores as dependencies for loads referencing this fixed object.
4202 int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, false, true);
4203 SDValue FIN = DAG.getFrameIndex(FI, PtrTy);
4204 InVals.push_back(FIN);
4205
4206 if (!NumRegs)
4207 return;
4208
4209 // Copy arg registers.
4210 MVT RegTy = MVT::getIntegerVT(GPRSizeInBytes * 8);
4211 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4212
4213 for (unsigned I = 0; I < NumRegs; ++I) {
4214 unsigned ArgReg = ByValArgRegs[FirstReg + I];
4215 unsigned VReg = addLiveIn(MF, ArgReg, RC);
4216 unsigned Offset = I * GPRSizeInBytes;
4217 SDValue StorePtr = DAG.getNode(ISD::ADD, DL, PtrTy, FIN,
4218 DAG.getConstant(Offset, DL, PtrTy));
4219 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
4220 StorePtr, MachinePointerInfo(FuncArg, Offset));
4221 OutChains.push_back(Store);
4222 }
4223 }
4224
4225 // Copy byVal arg to registers and stack.
4226 void MipsTargetLowering::passByValArg(
4227 SDValue Chain, const SDLoc &DL,
4228 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
4229 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
4230 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg,
4231 unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle,
4232 const CCValAssign &VA) const {
4233 unsigned ByValSizeInBytes = Flags.getByValSize();
4234 unsigned OffsetInBytes = 0; // From beginning of struct
4235 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4236 unsigned Alignment = std::min(Flags.getByValAlign(), RegSizeInBytes);
4237 EVT PtrTy = getPointerTy(DAG.getDataLayout()),
4238 RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4239 unsigned NumRegs = LastReg - FirstReg;
4240
4241 if (NumRegs) {
4242 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs();
4243 bool LeftoverBytes = (NumRegs * RegSizeInBytes > ByValSizeInBytes);
4244 unsigned I = 0;
4245
4246 // Copy words to registers.
4247 for (; I < NumRegs - LeftoverBytes; ++I, OffsetInBytes += RegSizeInBytes) {
4248 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4249 DAG.getConstant(OffsetInBytes, DL, PtrTy));
4250 SDValue LoadVal = DAG.getLoad(RegTy, DL, Chain, LoadPtr,
4251 MachinePointerInfo(), Alignment);
4252 MemOpChains.push_back(LoadVal.getValue(1));
4253 unsigned ArgReg = ArgRegs[FirstReg + I];
4254 RegsToPass.push_back(std::make_pair(ArgReg, LoadVal));
4255 }
4256
4257 // Return if the struct has been fully copied.
4258 if (ByValSizeInBytes == OffsetInBytes)
4259 return;
4260
4261 // Copy the remainder of the byval argument with sub-word loads and shifts.
4262 if (LeftoverBytes) {
4263 SDValue Val;
4264
4265 for (unsigned LoadSizeInBytes = RegSizeInBytes / 2, TotalBytesLoaded = 0;
4266 OffsetInBytes < ByValSizeInBytes; LoadSizeInBytes /= 2) {
4267 unsigned RemainingSizeInBytes = ByValSizeInBytes - OffsetInBytes;
4268
4269 if (RemainingSizeInBytes < LoadSizeInBytes)
4270 continue;
4271
4272 // Load subword.
4273 SDValue LoadPtr = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4274 DAG.getConstant(OffsetInBytes, DL,
4275 PtrTy));
4276 SDValue LoadVal = DAG.getExtLoad(
4277 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
4278 MVT::getIntegerVT(LoadSizeInBytes * 8), Alignment);
4279 MemOpChains.push_back(LoadVal.getValue(1));
4280
4281 // Shift the loaded value.
4282 unsigned Shamt;
4283
4284 if (isLittle)
4285 Shamt = TotalBytesLoaded * 8;
4286 else
4287 Shamt = (RegSizeInBytes - (TotalBytesLoaded + LoadSizeInBytes)) * 8;
4288
4289 SDValue Shift = DAG.getNode(ISD::SHL, DL, RegTy, LoadVal,
4290 DAG.getConstant(Shamt, DL, MVT::i32));
4291
4292 if (Val.getNode())
4293 Val = DAG.getNode(ISD::OR, DL, RegTy, Val, Shift);
4294 else
4295 Val = Shift;
4296
4297 OffsetInBytes += LoadSizeInBytes;
4298 TotalBytesLoaded += LoadSizeInBytes;
4299 Alignment = std::min(Alignment, LoadSizeInBytes);
4300 }
4301
4302 unsigned ArgReg = ArgRegs[FirstReg + I];
4303 RegsToPass.push_back(std::make_pair(ArgReg, Val));
4304 return;
4305 }
4306 }
4307
4308 // Copy remainder of byval arg to it with memcpy.
4309 unsigned MemCpySize = ByValSizeInBytes - OffsetInBytes;
4310 SDValue Src = DAG.getNode(ISD::ADD, DL, PtrTy, Arg,
4311 DAG.getConstant(OffsetInBytes, DL, PtrTy));
4312 SDValue Dst = DAG.getNode(ISD::ADD, DL, PtrTy, StackPtr,
4313 DAG.getIntPtrConstant(VA.getLocMemOffset(), DL));
4314 Chain = DAG.getMemcpy(Chain, DL, Dst, Src,
4315 DAG.getConstant(MemCpySize, DL, PtrTy),
4316 Alignment, /*isVolatile=*/false, /*AlwaysInline=*/false,
4317 /*isTailCall=*/false,
4318 MachinePointerInfo(), MachinePointerInfo());
4319 MemOpChains.push_back(Chain);
4320 }
4321
4322 void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
4323 SDValue Chain, const SDLoc &DL,
4324 SelectionDAG &DAG,
4325 CCState &State) const {
4326 ArrayRef<MCPhysReg> ArgRegs = ABI.GetVarArgRegs();
4327 unsigned Idx = State.getFirstUnallocated(ArgRegs);
4328 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4329 MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
4330 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4331 MachineFunction &MF = DAG.getMachineFunction();
4332 MachineFrameInfo &MFI = MF.getFrameInfo();
4333 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
4334
4335 // Offset of the first variable argument from stack pointer.
4336 int VaArgOffset;
4337
4338 if (ArgRegs.size() == Idx)
4339 VaArgOffset = alignTo(State.getNextStackOffset(), RegSizeInBytes);
4340 else {
4341 VaArgOffset =
4342 (int)ABI.GetCalleeAllocdArgSizeInBytes(State.getCallingConv()) -
4343 (int)(RegSizeInBytes * (ArgRegs.size() - Idx));
4344 }
4345
4346 // Record the frame index of the first variable argument
4347 // which is a value necessary to VASTART.
4348 int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4349 MipsFI->setVarArgsFrameIndex(FI);
4350
4351 // Copy the integer registers that have not been used for argument passing
4352 // to the argument register save area. For O32, the save area is allocated
4353 // in the caller's stack frame, while for N32/64, it is allocated in the
4354 // callee's stack frame.
4355 for (unsigned I = Idx; I < ArgRegs.size();
4356 ++I, VaArgOffset += RegSizeInBytes) {
4357 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
4358 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
4359 FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true);
4360 SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
4361 SDValue Store =
4362 DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo());
4363 cast<StoreSDNode>(Store.getNode())->getMemOperand()->setValue(
4364 (Value *)nullptr);
4365 OutChains.push_back(Store);
4366 }
4367 }
4368
4369 void MipsTargetLowering::HandleByVal(CCState *State, unsigned &Size,
4370 unsigned Align) const {
4371 const TargetFrameLowering *TFL = Subtarget.getFrameLowering();
4372
4373 assert(Size && "Byval argument's size shouldn't be 0.");
4374
4375 Align = std::min(Align, TFL->getStackAlignment());
4376
4377 unsigned FirstReg = 0;
4378 unsigned NumRegs = 0;
4379
4380 if (State->getCallingConv() != CallingConv::Fast) {
4381 unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
4382 ArrayRef<MCPhysReg> IntArgRegs = ABI.GetByValArgRegs();
4383 // FIXME: The O32 case actually describes no shadow registers.
4384 const MCPhysReg *ShadowRegs =
4385 ABI.IsO32() ? IntArgRegs.data() : Mips64DPRegs;
4386
4387 // We used to check the size as well but we can't do that anymore since
4388 // CCState::HandleByVal() rounds up the size after calling this function.
4389 assert(!(Align % RegSizeInBytes) &&
4390 "Byval argument's alignment should be a multiple of"
4391 "RegSizeInBytes.");
4392
4393 FirstReg = State->getFirstUnallocated(IntArgRegs);
4394
4395 // If Align > RegSizeInBytes, the first arg register must be even.
4396 // FIXME: This condition happens to do the right thing but it's not the
4397 // right way to test it. We want to check that the stack frame offset
4398 // of the register is aligned.
4399 if ((Align > RegSizeInBytes) && (FirstReg % 2)) {
4400 State->AllocateReg(IntArgRegs[FirstReg], ShadowRegs[FirstReg]);
4401 ++FirstReg;
4402 }
4403
4404 // Mark the registers allocated.
4405 Size = alignTo(Size, RegSizeInBytes);
4406 for (unsigned I = FirstReg; Size > 0 && (I < IntArgRegs.size());
4407 Size -= RegSizeInBytes, ++I, ++NumRegs)
4408 State->AllocateReg(IntArgRegs[I], ShadowRegs[I]);
4409 }
4410
4411 State->addInRegsParamInfo(FirstReg, FirstReg + NumRegs);
4412 }
4413
4414 MachineBasicBlock *MipsTargetLowering::emitPseudoSELECT(MachineInstr &MI,
4415 MachineBasicBlock *BB,
4416 bool isFPCmp,
4417 unsigned Opc) const {
4418 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4419 "Subtarget already supports SELECT nodes with the use of"
4420 "conditional-move instructions.");
4421
4422 const TargetInstrInfo *TII =
4423 Subtarget.getInstrInfo();
4424 DebugLoc DL = MI.getDebugLoc();
4425
4426 // To "insert" a SELECT instruction, we actually have to insert the
4427 // diamond control-flow pattern. The incoming instruction knows the
4428 // destination vreg to set, the condition code register to branch on, the
4429 // true/false values to select between, and a branch opcode to use.
4430 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4431 MachineFunction::iterator It = ++BB->getIterator();
4432
4433 // thisMBB:
4434 // ...
4435 // TrueVal = ...
4436 // setcc r1, r2, r3
4437 // bNE r1, r0, copy1MBB
4438 // fallthrough --> copy0MBB
4439 MachineBasicBlock *thisMBB = BB;
4440 MachineFunction *F = BB->getParent();
4441 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4442 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4443 F->insert(It, copy0MBB);
4444 F->insert(It, sinkMBB);
4445
4446 // Transfer the remainder of BB and its successor edges to sinkMBB.
4447 sinkMBB->splice(sinkMBB->begin(), BB,
4448 std::next(MachineBasicBlock::iterator(MI)), BB->end());
4449 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4450
4451 // Next, add the true and fallthrough blocks as its successors.
4452 BB->addSuccessor(copy0MBB);
4453 BB->addSuccessor(sinkMBB);
4454
4455 if (isFPCmp) {
4456 // bc1[tf] cc, sinkMBB
4457 BuildMI(BB, DL, TII->get(Opc))
4458 .addReg(MI.getOperand(1).getReg())
4459 .addMBB(sinkMBB);
4460 } else {
4461 // bne rs, $0, sinkMBB
4462 BuildMI(BB, DL, TII->get(Opc))
4463 .addReg(MI.getOperand(1).getReg())
4464 .addReg(Mips::ZERO)
4465 .addMBB(sinkMBB);
4466 }
4467
4468 // copy0MBB:
4469 // %FalseValue = ...
4470 // # fallthrough to sinkMBB
4471 BB = copy0MBB;
4472
4473 // Update machine-CFG edges
4474 BB->addSuccessor(sinkMBB);
4475
4476 // sinkMBB:
4477 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4478 // ...
4479 BB = sinkMBB;
4480
4481 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4482 .addReg(MI.getOperand(2).getReg())
4483 .addMBB(thisMBB)
4484 .addReg(MI.getOperand(3).getReg())
4485 .addMBB(copy0MBB);
4486
4487 MI.eraseFromParent(); // The pseudo instruction is gone now.
4488
4489 return BB;
4490 }
4491
4492 MachineBasicBlock *MipsTargetLowering::emitPseudoD_SELECT(MachineInstr &MI,
4493 MachineBasicBlock *BB) const {
4494 assert(!(Subtarget.hasMips4() || Subtarget.hasMips32()) &&
4495 "Subtarget already supports SELECT nodes with the use of"
4496 "conditional-move instructions.");
4497
4498 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
4499 DebugLoc DL = MI.getDebugLoc();
4500
4501 // D_SELECT substitutes two SELECT nodes that goes one after another and
4502 // have the same condition operand. On machines which don't have
4503 // conditional-move instruction, it reduces unnecessary branch instructions
4504 // which are result of using two diamond patterns that are result of two
4505 // SELECT pseudo instructions.
4506 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4507 MachineFunction::iterator It = ++BB->getIterator();
4508
4509 // thisMBB:
4510 // ...
4511 // TrueVal = ...
4512 // setcc r1, r2, r3
4513 // bNE r1, r0, copy1MBB
4514 // fallthrough --> copy0MBB
4515 MachineBasicBlock *thisMBB = BB;
4516 MachineFunction *F = BB->getParent();
4517 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4518 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4519 F->insert(It, copy0MBB);
4520 F->insert(It, sinkMBB);
4521
4522 // Transfer the remainder of BB and its successor edges to sinkMBB.
4523 sinkMBB->splice(sinkMBB->begin(), BB,
4524 std::next(MachineBasicBlock::iterator(MI)), BB->end());
4525 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4526
4527 // Next, add the true and fallthrough blocks as its successors.
4528 BB->addSuccessor(copy0MBB);
4529 BB->addSuccessor(sinkMBB);
4530
4531 // bne rs, $0, sinkMBB
4532 BuildMI(BB, DL, TII->get(Mips::BNE))
4533 .addReg(MI.getOperand(2).getReg())
4534 .addReg(Mips::ZERO)
4535 .addMBB(sinkMBB);
4536
4537 // copy0MBB:
4538 // %FalseValue = ...
4539 // # fallthrough to sinkMBB
4540 BB = copy0MBB;
4541
4542 // Update machine-CFG edges
4543 BB->addSuccessor(sinkMBB);
4544
4545 // sinkMBB:
4546 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
4547 // ...
4548 BB = sinkMBB;
4549
4550 // Use two PHI nodes to select two reults
4551 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4552 .addReg(MI.getOperand(3).getReg())
4553 .addMBB(thisMBB)
4554 .addReg(MI.getOperand(5).getReg())
4555 .addMBB(copy0MBB);
4556 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
4557 .addReg(MI.getOperand(4).getReg())
4558 .addMBB(thisMBB)
4559 .addReg(MI.getOperand(6).getReg())
4560 .addMBB(copy0MBB);
4561
4562 MI.eraseFromParent(); // The pseudo instruction is gone now.
4563
4564 return BB;
4565 }
4566
4567 // FIXME? Maybe this could be a TableGen attribute on some registers and
4568 // this table could be generated automatically from RegInfo.
4569 Register MipsTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4570 const MachineFunction &MF) const {
4571 // Named registers is expected to be fairly rare. For now, just support $28
4572 // since the linux kernel uses it.
4573 if (Subtarget.isGP64bit()) {
4574 Register Reg = StringSwitch<Register>(RegName)
4575 .Case("$28", Mips::GP_64)
4576 .Default(Register());
4577 if (Reg)
4578 return Reg;
4579 } else {
4580 Register Reg = StringSwitch<Register>(RegName)
4581 .Case("$28", Mips::GP)
4582 .Default(Register());
4583 if (Reg)
4584 return Reg;
4585 }
4586 report_fatal_error("Invalid register name global variable");
4587 }
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