1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
11 //===----------------------------------------------------------------------===//
13 #include "MipsSEISelDAGToDAG.h"
14 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsRegisterInfo.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 #include "llvm/IR/CFG.h"
26 #include "llvm/IR/Dominators.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
37 #define DEBUG_TYPE "mips-isel"
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction
&MF
) {
40 Subtarget
= &static_cast<const MipsSubtarget
&>(MF
.getSubtarget());
41 if (Subtarget
->inMips16Mode())
43 return MipsDAGToDAGISel::runOnMachineFunction(MF
);
46 void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage
&AU
) const {
47 AU
.addRequired
<DominatorTreeWrapperPass
>();
48 SelectionDAGISel::getAnalysisUsage(AU
);
51 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef
, MachineInstr
&MI
,
52 MachineFunction
&MF
) {
53 MachineInstrBuilder
MIB(MF
, &MI
);
54 unsigned Mask
= MI
.getOperand(1).getImm();
56 IsDef
? RegState::ImplicitDefine
: RegState::Implicit
| RegState::Undef
;
59 MIB
.addReg(Mips::DSPPos
, Flag
);
62 MIB
.addReg(Mips::DSPSCount
, Flag
);
65 MIB
.addReg(Mips::DSPCarry
, Flag
);
68 MIB
.addReg(Mips::DSPOutFlag
, Flag
);
71 MIB
.addReg(Mips::DSPCCond
, Flag
);
74 MIB
.addReg(Mips::DSPEFI
, Flag
);
77 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx
) const {
78 uint64_t RegNum
= cast
<ConstantSDNode
>(RegIdx
)->getZExtValue();
79 return Mips::MSACtrlRegClass
.getRegister(RegNum
);
82 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo
*MRI
,
83 const MachineInstr
& MI
) {
84 unsigned DstReg
= 0, ZeroReg
= 0;
86 // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
87 if ((MI
.getOpcode() == Mips::ADDiu
) &&
88 (MI
.getOperand(1).getReg() == Mips::ZERO
) &&
89 (MI
.getOperand(2).isImm()) &&
90 (MI
.getOperand(2).getImm() == 0)) {
91 DstReg
= MI
.getOperand(0).getReg();
93 } else if ((MI
.getOpcode() == Mips::DADDiu
) &&
94 (MI
.getOperand(1).getReg() == Mips::ZERO_64
) &&
95 (MI
.getOperand(2).isImm()) &&
96 (MI
.getOperand(2).getImm() == 0)) {
97 DstReg
= MI
.getOperand(0).getReg();
98 ZeroReg
= Mips::ZERO_64
;
104 // Replace uses with ZeroReg.
105 for (MachineRegisterInfo::use_iterator U
= MRI
->use_begin(DstReg
),
106 E
= MRI
->use_end(); U
!= E
;) {
107 MachineOperand
&MO
= *U
;
108 unsigned OpNo
= U
.getOperandNo();
109 MachineInstr
*MI
= MO
.getParent();
112 // Do not replace if it is a phi's operand or is tied to def operand.
113 if (MI
->isPHI() || MI
->isRegTiedToDefOperand(OpNo
) || MI
->isPseudo())
116 // Also, we have to check that the register class of the operand
117 // contains the zero register.
118 if (!MRI
->getRegClass(MO
.getReg())->contains(ZeroReg
))
127 void MipsSEDAGToDAGISel::emitMCountABI(MachineInstr
&MI
, MachineBasicBlock
&MBB
,
128 MachineFunction
&MF
) {
129 MachineInstrBuilder
MIB(MF
, &MI
);
130 if (!Subtarget
->isABI_O32()) { // N32, N64
131 // Save current return address.
132 BuildMI(MBB
, &MI
, MI
.getDebugLoc(), TII
->get(Mips::OR64
))
134 .addUse(Mips::RA_64
, RegState::Undef
)
135 .addUse(Mips::ZERO_64
);
136 // Stops instruction above from being removed later on.
137 MIB
.addUse(Mips::AT_64
, RegState::Implicit
);
139 // Save current return address.
140 BuildMI(MBB
, &MI
, MI
.getDebugLoc(), TII
->get(Mips::OR
))
142 .addUse(Mips::RA
, RegState::Undef
)
144 // _mcount pops 2 words from stack.
145 BuildMI(MBB
, &MI
, MI
.getDebugLoc(), TII
->get(Mips::ADDiu
))
149 // Stops first instruction above from being removed later on.
150 MIB
.addUse(Mips::AT
, RegState::Implicit
);
154 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction
&MF
) {
155 MF
.getInfo
<MipsFunctionInfo
>()->initGlobalBaseReg();
157 MachineRegisterInfo
*MRI
= &MF
.getRegInfo();
159 for (auto &MBB
: MF
) {
160 for (auto &MI
: MBB
) {
161 switch (MI
.getOpcode()) {
163 addDSPCtrlRegOperands(false, MI
, MF
);
166 addDSPCtrlRegOperands(true, MI
, MF
);
168 case Mips::BuildPairF64_64
:
169 case Mips::ExtractElementF64_64
:
170 if (!Subtarget
->useOddSPReg()) {
171 MI
.addOperand(MachineOperand::CreateReg(Mips::SP
, false, true));
175 case Mips::BuildPairF64
:
176 case Mips::ExtractElementF64
:
177 if (Subtarget
->isABI_FPXX() && !Subtarget
->hasMTHC1())
178 MI
.addOperand(MachineOperand::CreateReg(Mips::SP
, false, true));
182 if (MI
.getOperand(0).isGlobal() &&
183 MI
.getOperand(0).getGlobal()->getGlobalIdentifier() == "_mcount")
184 emitMCountABI(MI
, MBB
, MF
);
186 case Mips::JALRPseudo
:
187 case Mips::JALR64Pseudo
:
188 case Mips::JALR16_MM
:
189 if (MI
.getOperand(2).isMCSymbol() &&
190 MI
.getOperand(2).getMCSymbol()->getName() == "_mcount")
191 emitMCountABI(MI
, MBB
, MF
);
194 if (MI
.getOperand(3).isMCSymbol() &&
195 MI
.getOperand(3).getMCSymbol()->getName() == "_mcount")
196 emitMCountABI(MI
, MBB
, MF
);
199 replaceUsesWithZeroReg(MRI
, MI
);
205 void MipsSEDAGToDAGISel::selectAddE(SDNode
*Node
, const SDLoc
&DL
) const {
206 SDValue InFlag
= Node
->getOperand(2);
207 unsigned Opc
= InFlag
.getOpcode();
208 SDValue LHS
= Node
->getOperand(0), RHS
= Node
->getOperand(1);
209 EVT VT
= LHS
.getValueType();
211 // In the base case, we can rely on the carry bit from the addsc
213 if (Opc
== ISD::ADDC
) {
214 SDValue Ops
[3] = {LHS
, RHS
, InFlag
};
215 CurDAG
->SelectNodeTo(Node
, Mips::ADDWC
, VT
, MVT::Glue
, Ops
);
219 assert(Opc
== ISD::ADDE
&& "ISD::ADDE not in a chain of ADDE nodes!");
221 // The more complex case is when there is a chain of ISD::ADDE nodes like:
222 // (adde (adde (adde (addc a b) c) d) e).
224 // The addwc instruction does not write to the carry bit, instead it writes
225 // to bit 20 of the dsp control register. To match this series of nodes, each
226 // intermediate adde node must be expanded to write the carry bit before the
229 // Start by reading the overflow field for addsc and moving the value to the
230 // carry field. The usage of 1 here with MipsISD::RDDSP / Mips::WRDSP
231 // corresponds to reading/writing the entire control register to/from a GPR.
233 SDValue CstOne
= CurDAG
->getTargetConstant(1, DL
, MVT::i32
);
235 SDValue OuFlag
= CurDAG
->getTargetConstant(20, DL
, MVT::i32
);
237 SDNode
*DSPCtrlField
=
238 CurDAG
->getMachineNode(Mips::RDDSP
, DL
, MVT::i32
, MVT::Glue
, CstOne
, InFlag
);
240 SDNode
*Carry
= CurDAG
->getMachineNode(
241 Mips::EXT
, DL
, MVT::i32
, SDValue(DSPCtrlField
, 0), OuFlag
, CstOne
);
243 SDValue Ops
[4] = {SDValue(DSPCtrlField
, 0),
244 CurDAG
->getTargetConstant(6, DL
, MVT::i32
), CstOne
,
246 SDNode
*DSPCFWithCarry
= CurDAG
->getMachineNode(Mips::INS
, DL
, MVT::i32
, Ops
);
248 // My reading of the MIPS DSP 3.01 specification isn't as clear as I
249 // would like about whether bit 20 always gets overwritten by addwc.
250 // Hence take an extremely conservative view and presume it's sticky. We
251 // therefore need to clear it.
253 SDValue Zero
= CurDAG
->getRegister(Mips::ZERO
, MVT::i32
);
255 SDValue InsOps
[4] = {Zero
, OuFlag
, CstOne
, SDValue(DSPCFWithCarry
, 0)};
256 SDNode
*DSPCtrlFinal
= CurDAG
->getMachineNode(Mips::INS
, DL
, MVT::i32
, InsOps
);
258 SDNode
*WrDSP
= CurDAG
->getMachineNode(Mips::WRDSP
, DL
, MVT::Glue
,
259 SDValue(DSPCtrlFinal
, 0), CstOne
);
261 SDValue Operands
[3] = {LHS
, RHS
, SDValue(WrDSP
, 0)};
262 CurDAG
->SelectNodeTo(Node
, Mips::ADDWC
, VT
, MVT::Glue
, Operands
);
266 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr
, SDValue
&Base
,
267 SDValue
&Offset
) const {
268 if (FrameIndexSDNode
*FIN
= dyn_cast
<FrameIndexSDNode
>(Addr
)) {
269 EVT ValTy
= Addr
.getValueType();
271 Base
= CurDAG
->getTargetFrameIndex(FIN
->getIndex(), ValTy
);
272 Offset
= CurDAG
->getTargetConstant(0, SDLoc(Addr
), ValTy
);
278 /// Match frameindex+offset and frameindex|offset
279 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(
280 SDValue Addr
, SDValue
&Base
, SDValue
&Offset
, unsigned OffsetBits
,
281 unsigned ShiftAmount
= 0) const {
282 if (CurDAG
->isBaseWithConstantOffset(Addr
)) {
283 ConstantSDNode
*CN
= dyn_cast
<ConstantSDNode
>(Addr
.getOperand(1));
284 if (isIntN(OffsetBits
+ ShiftAmount
, CN
->getSExtValue())) {
285 EVT ValTy
= Addr
.getValueType();
287 // If the first operand is a FI, get the TargetFI Node
288 if (FrameIndexSDNode
*FIN
=
289 dyn_cast
<FrameIndexSDNode
>(Addr
.getOperand(0)))
290 Base
= CurDAG
->getTargetFrameIndex(FIN
->getIndex(), ValTy
);
292 Base
= Addr
.getOperand(0);
293 // If base is a FI, additional offset calculation is done in
294 // eliminateFrameIndex, otherwise we need to check the alignment
295 const Align
Alignment(1ULL << ShiftAmount
);
296 if (!isAligned(Alignment
, CN
->getZExtValue()))
300 Offset
= CurDAG
->getTargetConstant(CN
->getZExtValue(), SDLoc(Addr
),
308 /// ComplexPattern used on MipsInstrInfo
309 /// Used on Mips Load/Store instructions
310 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr
, SDValue
&Base
,
311 SDValue
&Offset
) const {
312 // if Address is FI, get the TargetFrameIndex.
313 if (selectAddrFrameIndex(Addr
, Base
, Offset
))
316 // on PIC code Load GA
317 if (Addr
.getOpcode() == MipsISD::Wrapper
) {
318 Base
= Addr
.getOperand(0);
319 Offset
= Addr
.getOperand(1);
323 if (!TM
.isPositionIndependent()) {
324 if ((Addr
.getOpcode() == ISD::TargetExternalSymbol
||
325 Addr
.getOpcode() == ISD::TargetGlobalAddress
))
329 // Addresses of the form FI+const or FI|const
330 if (selectAddrFrameIndexOffset(Addr
, Base
, Offset
, 16))
333 // Operand is a result from an ADD.
334 if (Addr
.getOpcode() == ISD::ADD
) {
335 // When loading from constant pools, load the lower address part in
336 // the instruction itself. Example, instead of:
337 // lui $2, %hi($CPI1_0)
338 // addiu $2, $2, %lo($CPI1_0)
341 // lui $2, %hi($CPI1_0)
342 // lwc1 $f0, %lo($CPI1_0)($2)
343 if (Addr
.getOperand(1).getOpcode() == MipsISD::Lo
||
344 Addr
.getOperand(1).getOpcode() == MipsISD::GPRel
) {
345 SDValue Opnd0
= Addr
.getOperand(1).getOperand(0);
346 if (isa
<ConstantPoolSDNode
>(Opnd0
) || isa
<GlobalAddressSDNode
>(Opnd0
) ||
347 isa
<JumpTableSDNode
>(Opnd0
)) {
348 Base
= Addr
.getOperand(0);
358 /// ComplexPattern used on MipsInstrInfo
359 /// Used on Mips Load/Store instructions
360 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr
, SDValue
&Base
,
361 SDValue
&Offset
) const {
363 Offset
= CurDAG
->getTargetConstant(0, SDLoc(Addr
), Addr
.getValueType());
367 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr
, SDValue
&Base
,
368 SDValue
&Offset
) const {
369 return selectAddrRegImm(Addr
, Base
, Offset
) ||
370 selectAddrDefault(Addr
, Base
, Offset
);
373 bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr
, SDValue
&Base
,
374 SDValue
&Offset
) const {
375 if (selectAddrFrameIndex(Addr
, Base
, Offset
))
378 if (selectAddrFrameIndexOffset(Addr
, Base
, Offset
, 9))
384 /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset)
385 bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr
, SDValue
&Base
,
386 SDValue
&Offset
) const {
387 if (selectAddrFrameIndex(Addr
, Base
, Offset
))
390 if (selectAddrFrameIndexOffset(Addr
, Base
, Offset
, 11))
396 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
397 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr
, SDValue
&Base
,
398 SDValue
&Offset
) const {
399 if (selectAddrFrameIndex(Addr
, Base
, Offset
))
402 if (selectAddrFrameIndexOffset(Addr
, Base
, Offset
, 12))
408 bool MipsSEDAGToDAGISel::selectAddrRegImm16(SDValue Addr
, SDValue
&Base
,
409 SDValue
&Offset
) const {
410 if (selectAddrFrameIndex(Addr
, Base
, Offset
))
413 if (selectAddrFrameIndexOffset(Addr
, Base
, Offset
, 16))
419 bool MipsSEDAGToDAGISel::selectIntAddr11MM(SDValue Addr
, SDValue
&Base
,
420 SDValue
&Offset
) const {
421 return selectAddrRegImm11(Addr
, Base
, Offset
) ||
422 selectAddrDefault(Addr
, Base
, Offset
);
425 bool MipsSEDAGToDAGISel::selectIntAddr12MM(SDValue Addr
, SDValue
&Base
,
426 SDValue
&Offset
) const {
427 return selectAddrRegImm12(Addr
, Base
, Offset
) ||
428 selectAddrDefault(Addr
, Base
, Offset
);
431 bool MipsSEDAGToDAGISel::selectIntAddr16MM(SDValue Addr
, SDValue
&Base
,
432 SDValue
&Offset
) const {
433 return selectAddrRegImm16(Addr
, Base
, Offset
) ||
434 selectAddrDefault(Addr
, Base
, Offset
);
437 bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr
, SDValue
&Base
,
438 SDValue
&Offset
) const {
439 if (selectAddrFrameIndexOffset(Addr
, Base
, Offset
, 7)) {
440 if (isa
<FrameIndexSDNode
>(Base
))
443 if (ConstantSDNode
*CN
= dyn_cast
<ConstantSDNode
>(Offset
)) {
444 unsigned CnstOff
= CN
->getZExtValue();
445 return (CnstOff
== (CnstOff
& 0x3c));
451 // For all other cases where "lw" would be selected, don't select "lw16"
452 // because it would result in additional instructions to prepare operands.
453 if (selectAddrRegImm(Addr
, Base
, Offset
))
456 return selectAddrDefault(Addr
, Base
, Offset
);
459 bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr
, SDValue
&Base
,
460 SDValue
&Offset
) const {
462 if (selectAddrFrameIndex(Addr
, Base
, Offset
))
465 if (selectAddrFrameIndexOffset(Addr
, Base
, Offset
, 10))
468 return selectAddrDefault(Addr
, Base
, Offset
);
471 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr
, SDValue
&Base
,
472 SDValue
&Offset
) const {
473 if (selectAddrFrameIndex(Addr
, Base
, Offset
))
476 if (selectAddrFrameIndexOffset(Addr
, Base
, Offset
, 10, 1))
479 return selectAddrDefault(Addr
, Base
, Offset
);
482 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr
, SDValue
&Base
,
483 SDValue
&Offset
) const {
484 if (selectAddrFrameIndex(Addr
, Base
, Offset
))
487 if (selectAddrFrameIndexOffset(Addr
, Base
, Offset
, 10, 2))
490 return selectAddrDefault(Addr
, Base
, Offset
);
493 bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr
, SDValue
&Base
,
494 SDValue
&Offset
) const {
495 if (selectAddrFrameIndex(Addr
, Base
, Offset
))
498 if (selectAddrFrameIndexOffset(Addr
, Base
, Offset
, 10, 3))
501 return selectAddrDefault(Addr
, Base
, Offset
);
504 // Select constant vector splats.
506 // Returns true and sets Imm if:
508 // * N is a ISD::BUILD_VECTOR representing a constant splat
509 bool MipsSEDAGToDAGISel::selectVSplat(SDNode
*N
, APInt
&Imm
,
510 unsigned MinSizeInBits
) const {
511 if (!Subtarget
->hasMSA())
514 BuildVectorSDNode
*Node
= dyn_cast
<BuildVectorSDNode
>(N
);
519 APInt SplatValue
, SplatUndef
;
520 unsigned SplatBitSize
;
523 if (!Node
->isConstantSplat(SplatValue
, SplatUndef
, SplatBitSize
, HasAnyUndefs
,
524 MinSizeInBits
, !Subtarget
->isLittle()))
532 // Select constant vector splats.
534 // In addition to the requirements of selectVSplat(), this function returns
535 // true and sets Imm if:
536 // * The splat value is the same width as the elements of the vector
537 // * The splat value fits in an integer with the specified signed-ness and
540 // This function looks through ISD::BITCAST nodes.
541 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
542 // sometimes a shuffle in big-endian mode.
544 // It's worth noting that this function is not used as part of the selection
545 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
546 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
547 // MipsSEDAGToDAGISel::selectNode.
548 bool MipsSEDAGToDAGISel::
549 selectVSplatCommon(SDValue N
, SDValue
&Imm
, bool Signed
,
550 unsigned ImmBitSize
) const {
552 EVT EltTy
= N
->getValueType(0).getVectorElementType();
554 if (N
->getOpcode() == ISD::BITCAST
)
555 N
= N
->getOperand(0);
557 if (selectVSplat(N
.getNode(), ImmValue
, EltTy
.getSizeInBits()) &&
558 ImmValue
.getBitWidth() == EltTy
.getSizeInBits()) {
560 if (( Signed
&& ImmValue
.isSignedIntN(ImmBitSize
)) ||
561 (!Signed
&& ImmValue
.isIntN(ImmBitSize
))) {
562 Imm
= CurDAG
->getTargetConstant(ImmValue
, SDLoc(N
), EltTy
);
570 // Select constant vector splats.
571 bool MipsSEDAGToDAGISel::
572 selectVSplatUimm1(SDValue N
, SDValue
&Imm
) const {
573 return selectVSplatCommon(N
, Imm
, false, 1);
576 bool MipsSEDAGToDAGISel::
577 selectVSplatUimm2(SDValue N
, SDValue
&Imm
) const {
578 return selectVSplatCommon(N
, Imm
, false, 2);
581 bool MipsSEDAGToDAGISel::
582 selectVSplatUimm3(SDValue N
, SDValue
&Imm
) const {
583 return selectVSplatCommon(N
, Imm
, false, 3);
586 // Select constant vector splats.
587 bool MipsSEDAGToDAGISel::
588 selectVSplatUimm4(SDValue N
, SDValue
&Imm
) const {
589 return selectVSplatCommon(N
, Imm
, false, 4);
592 // Select constant vector splats.
593 bool MipsSEDAGToDAGISel::
594 selectVSplatUimm5(SDValue N
, SDValue
&Imm
) const {
595 return selectVSplatCommon(N
, Imm
, false, 5);
598 // Select constant vector splats.
599 bool MipsSEDAGToDAGISel::
600 selectVSplatUimm6(SDValue N
, SDValue
&Imm
) const {
601 return selectVSplatCommon(N
, Imm
, false, 6);
604 // Select constant vector splats.
605 bool MipsSEDAGToDAGISel::
606 selectVSplatUimm8(SDValue N
, SDValue
&Imm
) const {
607 return selectVSplatCommon(N
, Imm
, false, 8);
610 // Select constant vector splats.
611 bool MipsSEDAGToDAGISel::
612 selectVSplatSimm5(SDValue N
, SDValue
&Imm
) const {
613 return selectVSplatCommon(N
, Imm
, true, 5);
616 // Select constant vector splats whose value is a power of 2.
618 // In addition to the requirements of selectVSplat(), this function returns
619 // true and sets Imm if:
620 // * The splat value is the same width as the elements of the vector
621 // * The splat value is a power of two.
623 // This function looks through ISD::BITCAST nodes.
624 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
625 // sometimes a shuffle in big-endian mode.
626 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N
, SDValue
&Imm
) const {
628 EVT EltTy
= N
->getValueType(0).getVectorElementType();
630 if (N
->getOpcode() == ISD::BITCAST
)
631 N
= N
->getOperand(0);
633 if (selectVSplat(N
.getNode(), ImmValue
, EltTy
.getSizeInBits()) &&
634 ImmValue
.getBitWidth() == EltTy
.getSizeInBits()) {
635 int32_t Log2
= ImmValue
.exactLogBase2();
638 Imm
= CurDAG
->getTargetConstant(Log2
, SDLoc(N
), EltTy
);
646 // Select constant vector splats whose value only has a consecutive sequence
647 // of left-most bits set (e.g. 0b11...1100...00).
649 // In addition to the requirements of selectVSplat(), this function returns
650 // true and sets Imm if:
651 // * The splat value is the same width as the elements of the vector
652 // * The splat value is a consecutive sequence of left-most bits.
654 // This function looks through ISD::BITCAST nodes.
655 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
656 // sometimes a shuffle in big-endian mode.
657 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N
, SDValue
&Imm
) const {
659 EVT EltTy
= N
->getValueType(0).getVectorElementType();
661 if (N
->getOpcode() == ISD::BITCAST
)
662 N
= N
->getOperand(0);
664 if (selectVSplat(N
.getNode(), ImmValue
, EltTy
.getSizeInBits()) &&
665 ImmValue
.getBitWidth() == EltTy
.getSizeInBits()) {
666 // Extract the run of set bits starting with bit zero from the bitwise
667 // inverse of ImmValue, and test that the inverse of this is the same
668 // as the original value.
669 if (ImmValue
== ~(~ImmValue
& ~(~ImmValue
+ 1))) {
671 Imm
= CurDAG
->getTargetConstant(ImmValue
.countPopulation() - 1, SDLoc(N
),
680 // Select constant vector splats whose value only has a consecutive sequence
681 // of right-most bits set (e.g. 0b00...0011...11).
683 // In addition to the requirements of selectVSplat(), this function returns
684 // true and sets Imm if:
685 // * The splat value is the same width as the elements of the vector
686 // * The splat value is a consecutive sequence of right-most bits.
688 // This function looks through ISD::BITCAST nodes.
689 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
690 // sometimes a shuffle in big-endian mode.
691 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N
, SDValue
&Imm
) const {
693 EVT EltTy
= N
->getValueType(0).getVectorElementType();
695 if (N
->getOpcode() == ISD::BITCAST
)
696 N
= N
->getOperand(0);
698 if (selectVSplat(N
.getNode(), ImmValue
, EltTy
.getSizeInBits()) &&
699 ImmValue
.getBitWidth() == EltTy
.getSizeInBits()) {
700 // Extract the run of set bits starting with bit zero, and test that the
701 // result is the same as the original value
702 if (ImmValue
== (ImmValue
& ~(ImmValue
+ 1))) {
703 Imm
= CurDAG
->getTargetConstant(ImmValue
.countPopulation() - 1, SDLoc(N
),
712 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N
,
713 SDValue
&Imm
) const {
715 EVT EltTy
= N
->getValueType(0).getVectorElementType();
717 if (N
->getOpcode() == ISD::BITCAST
)
718 N
= N
->getOperand(0);
720 if (selectVSplat(N
.getNode(), ImmValue
, EltTy
.getSizeInBits()) &&
721 ImmValue
.getBitWidth() == EltTy
.getSizeInBits()) {
722 int32_t Log2
= (~ImmValue
).exactLogBase2();
725 Imm
= CurDAG
->getTargetConstant(Log2
, SDLoc(N
), EltTy
);
733 bool MipsSEDAGToDAGISel::trySelect(SDNode
*Node
) {
734 unsigned Opcode
= Node
->getOpcode();
738 // Instruction Selection not handled by the auto-generated
739 // tablegen selection should be handled here.
744 case Mips::PseudoD_SELECT_I
:
745 case Mips::PseudoD_SELECT_I64
: {
746 MVT VT
= Subtarget
->isGP64bit() ? MVT::i64
: MVT::i32
;
747 SDValue cond
= Node
->getOperand(0);
748 SDValue Hi1
= Node
->getOperand(1);
749 SDValue Lo1
= Node
->getOperand(2);
750 SDValue Hi2
= Node
->getOperand(3);
751 SDValue Lo2
= Node
->getOperand(4);
753 SDValue ops
[] = {cond
, Hi1
, Lo1
, Hi2
, Lo2
};
754 EVT NodeTys
[] = {VT
, VT
};
755 ReplaceNode(Node
, CurDAG
->getMachineNode(Subtarget
->isGP64bit()
756 ? Mips::PseudoD_SELECT_I64
757 : Mips::PseudoD_SELECT_I
,
763 selectAddE(Node
, DL
);
767 case ISD::ConstantFP
: {
768 auto *CN
= cast
<ConstantFPSDNode
>(Node
);
769 if (Node
->getValueType(0) == MVT::f64
&& CN
->isExactlyValue(+0.0)) {
770 if (Subtarget
->isGP64bit()) {
771 SDValue Zero
= CurDAG
->getCopyFromReg(CurDAG
->getEntryNode(), DL
,
772 Mips::ZERO_64
, MVT::i64
);
774 CurDAG
->getMachineNode(Mips::DMTC1
, DL
, MVT::f64
, Zero
));
775 } else if (Subtarget
->isFP64bit()) {
776 SDValue Zero
= CurDAG
->getCopyFromReg(CurDAG
->getEntryNode(), DL
,
777 Mips::ZERO
, MVT::i32
);
778 ReplaceNode(Node
, CurDAG
->getMachineNode(Mips::BuildPairF64_64
, DL
,
779 MVT::f64
, Zero
, Zero
));
781 SDValue Zero
= CurDAG
->getCopyFromReg(CurDAG
->getEntryNode(), DL
,
782 Mips::ZERO
, MVT::i32
);
783 ReplaceNode(Node
, CurDAG
->getMachineNode(Mips::BuildPairF64
, DL
,
784 MVT::f64
, Zero
, Zero
));
791 case ISD::Constant
: {
792 auto *CN
= cast
<ConstantSDNode
>(Node
);
793 int64_t Imm
= CN
->getSExtValue();
794 unsigned Size
= CN
->getValueSizeInBits(0);
799 MipsAnalyzeImmediate AnalyzeImm
;
801 const MipsAnalyzeImmediate::InstSeq
&Seq
=
802 AnalyzeImm
.Analyze(Imm
, Size
, false);
804 MipsAnalyzeImmediate::InstSeq::const_iterator Inst
= Seq
.begin();
807 SDValue ImmOpnd
= CurDAG
->getTargetConstant(SignExtend64
<16>(Inst
->ImmOpnd
),
810 // The first instruction can be a LUi which is different from other
811 // instructions (ADDiu, ORI and SLL) in that it does not have a register
813 if (Inst
->Opc
== Mips::LUi64
)
814 RegOpnd
= CurDAG
->getMachineNode(Inst
->Opc
, DL
, MVT::i64
, ImmOpnd
);
817 CurDAG
->getMachineNode(Inst
->Opc
, DL
, MVT::i64
,
818 CurDAG
->getRegister(Mips::ZERO_64
, MVT::i64
),
821 // The remaining instructions in the sequence are handled here.
822 for (++Inst
; Inst
!= Seq
.end(); ++Inst
) {
823 ImmOpnd
= CurDAG
->getTargetConstant(SignExtend64
<16>(Inst
->ImmOpnd
), DL
,
825 RegOpnd
= CurDAG
->getMachineNode(Inst
->Opc
, DL
, MVT::i64
,
826 SDValue(RegOpnd
, 0), ImmOpnd
);
829 ReplaceNode(Node
, RegOpnd
);
833 case ISD::INTRINSIC_W_CHAIN
: {
834 switch (cast
<ConstantSDNode
>(Node
->getOperand(1))->getZExtValue()) {
838 case Intrinsic::mips_cfcmsa
: {
839 SDValue ChainIn
= Node
->getOperand(0);
840 SDValue RegIdx
= Node
->getOperand(2);
841 SDValue Reg
= CurDAG
->getCopyFromReg(ChainIn
, DL
,
842 getMSACtrlReg(RegIdx
), MVT::i32
);
843 ReplaceNode(Node
, Reg
.getNode());
850 case ISD::INTRINSIC_WO_CHAIN
: {
851 switch (cast
<ConstantSDNode
>(Node
->getOperand(0))->getZExtValue()) {
855 case Intrinsic::mips_move_v
:
856 // Like an assignment but will always produce a move.v even if
858 ReplaceNode(Node
, CurDAG
->getMachineNode(Mips::MOVE_V
, DL
,
859 Node
->getValueType(0),
860 Node
->getOperand(1)));
866 case ISD::INTRINSIC_VOID
: {
867 switch (cast
<ConstantSDNode
>(Node
->getOperand(1))->getZExtValue()) {
871 case Intrinsic::mips_ctcmsa
: {
872 SDValue ChainIn
= Node
->getOperand(0);
873 SDValue RegIdx
= Node
->getOperand(2);
874 SDValue Value
= Node
->getOperand(3);
875 SDValue ChainOut
= CurDAG
->getCopyToReg(ChainIn
, DL
,
876 getMSACtrlReg(RegIdx
), Value
);
877 ReplaceNode(Node
, ChainOut
.getNode());
884 // Manually match MipsISD::Ins nodes to get the correct instruction. It has
885 // to be done in this fashion so that we respect the differences between
886 // dins and dinsm, as the difference is that the size operand has the range
887 // 0 < size <= 32 for dins while dinsm has the range 2 <= size <= 64 which
888 // means SelectionDAGISel would have to test all the operands at once to
889 // match the instruction.
892 // Sanity checking for the node operands.
893 if (Node
->getValueType(0) != MVT::i32
&& Node
->getValueType(0) != MVT::i64
)
896 if (Node
->getNumOperands() != 4)
899 if (Node
->getOperand(1)->getOpcode() != ISD::Constant
||
900 Node
->getOperand(2)->getOpcode() != ISD::Constant
)
903 MVT ResTy
= Node
->getSimpleValueType(0);
904 uint64_t Pos
= Node
->getConstantOperandVal(1);
905 uint64_t Size
= Node
->getConstantOperandVal(2);
907 // Size has to be >0 for 'ins', 'dins' and 'dinsu'.
914 if (ResTy
!= MVT::i32
&& ResTy
!= MVT::i64
)
918 if (ResTy
== MVT::i32
) {
919 if (Pos
+ Size
<= 32)
922 if (Pos
+ Size
<= 32)
924 else if (Pos
< 32 && 1 < Size
)
925 Opcode
= Mips::DINSM
;
927 Opcode
= Mips::DINSU
;
932 Node
->getOperand(0), CurDAG
->getTargetConstant(Pos
, DL
, MVT::i32
),
933 CurDAG
->getTargetConstant(Size
, DL
, MVT::i32
), Node
->getOperand(3)};
935 ReplaceNode(Node
, CurDAG
->getMachineNode(Opcode
, DL
, ResTy
, Ops
));
942 case MipsISD::ThreadPointer
: {
943 EVT PtrVT
= getTargetLowering()->getPointerTy(CurDAG
->getDataLayout());
944 unsigned RdhwrOpc
, DestReg
;
946 if (PtrVT
== MVT::i32
) {
947 RdhwrOpc
= Mips::RDHWR
;
950 RdhwrOpc
= Mips::RDHWR64
;
951 DestReg
= Mips::V1_64
;
955 CurDAG
->getMachineNode(RdhwrOpc
, DL
, Node
->getValueType(0),
956 CurDAG
->getRegister(Mips::HWR29
, MVT::i32
),
957 CurDAG
->getTargetConstant(0, DL
, MVT::i32
));
958 SDValue Chain
= CurDAG
->getCopyToReg(CurDAG
->getEntryNode(), DL
, DestReg
,
960 SDValue ResNode
= CurDAG
->getCopyFromReg(Chain
, DL
, DestReg
, PtrVT
);
961 ReplaceNode(Node
, ResNode
.getNode());
965 case ISD::BUILD_VECTOR
: {
966 // Select appropriate ldi.[bhwd] instructions for constant splats of
967 // 128-bit when MSA is enabled. Fixup any register class mismatches that
968 // occur as a result.
970 // This allows the compiler to use a wider range of immediates than would
971 // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
972 // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
973 // 0x01010101 } without using a constant pool. This would be sub-optimal
974 // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
975 // same set/ of registers. Similarly, ldi.h isn't capable of producing {
976 // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
978 const MipsABIInfo
&ABI
=
979 static_cast<const MipsTargetMachine
&>(TM
).getABI();
981 BuildVectorSDNode
*BVN
= cast
<BuildVectorSDNode
>(Node
);
982 APInt SplatValue
, SplatUndef
;
983 unsigned SplatBitSize
;
986 EVT ResVecTy
= BVN
->getValueType(0);
989 if (!Subtarget
->hasMSA() || !BVN
->getValueType(0).is128BitVector())
992 if (!BVN
->isConstantSplat(SplatValue
, SplatUndef
, SplatBitSize
,
994 !Subtarget
->isLittle()))
997 switch (SplatBitSize
) {
1001 LdiOp
= Mips::LDI_B
;
1002 ViaVecTy
= MVT::v16i8
;
1005 LdiOp
= Mips::LDI_H
;
1006 ViaVecTy
= MVT::v8i16
;
1009 LdiOp
= Mips::LDI_W
;
1010 ViaVecTy
= MVT::v4i32
;
1013 LdiOp
= Mips::LDI_D
;
1014 ViaVecTy
= MVT::v2i64
;
1018 SDNode
*Res
= nullptr;
1020 // If we have a signed 10 bit integer, we can splat it directly.
1022 // If we have something bigger we can synthesize the value into a GPR and
1023 // splat from there.
1024 if (SplatValue
.isSignedIntN(10)) {
1025 SDValue Imm
= CurDAG
->getTargetConstant(SplatValue
, DL
,
1026 ViaVecTy
.getVectorElementType());
1028 Res
= CurDAG
->getMachineNode(LdiOp
, DL
, ViaVecTy
, Imm
);
1029 } else if (SplatValue
.isSignedIntN(16) &&
1030 ((ABI
.IsO32() && SplatBitSize
< 64) ||
1031 (ABI
.IsN32() || ABI
.IsN64()))) {
1032 // Only handle signed 16 bit values when the element size is GPR width.
1033 // MIPS64 can handle all the cases but MIPS32 would need to handle
1034 // negative cases specifically here. Instead, handle those cases as
1037 bool Is32BitSplat
= ABI
.IsO32() || SplatBitSize
< 64;
1038 const unsigned ADDiuOp
= Is32BitSplat
? Mips::ADDiu
: Mips::DADDiu
;
1039 const MVT SplatMVT
= Is32BitSplat
? MVT::i32
: MVT::i64
;
1040 SDValue ZeroVal
= CurDAG
->getRegister(
1041 Is32BitSplat
? Mips::ZERO
: Mips::ZERO_64
, SplatMVT
);
1043 const unsigned FILLOp
=
1046 : (SplatBitSize
== 32 ? Mips::FILL_W
1047 : (SplatBitSize
== 64 ? Mips::FILL_D
: 0));
1049 assert(FILLOp
!= 0 && "Unknown FILL Op for splat synthesis!");
1050 assert((!ABI
.IsO32() || (FILLOp
!= Mips::FILL_D
)) &&
1051 "Attempting to use fill.d on MIPS32!");
1053 const unsigned Lo
= SplatValue
.getLoBits(16).getZExtValue();
1054 SDValue LoVal
= CurDAG
->getTargetConstant(Lo
, DL
, SplatMVT
);
1056 Res
= CurDAG
->getMachineNode(ADDiuOp
, DL
, SplatMVT
, ZeroVal
, LoVal
);
1057 Res
= CurDAG
->getMachineNode(FILLOp
, DL
, ViaVecTy
, SDValue(Res
, 0));
1059 } else if (SplatValue
.isSignedIntN(32) && SplatBitSize
== 32) {
1060 // Only handle the cases where the splat size agrees with the size
1061 // of the SplatValue here.
1062 const unsigned Lo
= SplatValue
.getLoBits(16).getZExtValue();
1063 const unsigned Hi
= SplatValue
.lshr(16).getLoBits(16).getZExtValue();
1064 SDValue ZeroVal
= CurDAG
->getRegister(Mips::ZERO
, MVT::i32
);
1066 SDValue LoVal
= CurDAG
->getTargetConstant(Lo
, DL
, MVT::i32
);
1067 SDValue HiVal
= CurDAG
->getTargetConstant(Hi
, DL
, MVT::i32
);
1070 Res
= CurDAG
->getMachineNode(Mips::LUi
, DL
, MVT::i32
, HiVal
);
1073 Res
= CurDAG
->getMachineNode(Mips::ORi
, DL
, MVT::i32
,
1074 Hi
? SDValue(Res
, 0) : ZeroVal
, LoVal
);
1076 assert((Hi
|| Lo
) && "Zero case reached 32 bit case splat synthesis!");
1077 Res
= CurDAG
->getMachineNode(Mips::FILL_W
, DL
, MVT::v4i32
, SDValue(Res
, 0));
1079 } else if (SplatValue
.isSignedIntN(32) && SplatBitSize
== 64 &&
1080 (ABI
.IsN32() || ABI
.IsN64())) {
1081 // N32 and N64 can perform some tricks that O32 can't for signed 32 bit
1082 // integers due to having 64bit registers. lui will cause the necessary
1083 // zero/sign extension.
1084 const unsigned Lo
= SplatValue
.getLoBits(16).getZExtValue();
1085 const unsigned Hi
= SplatValue
.lshr(16).getLoBits(16).getZExtValue();
1086 SDValue ZeroVal
= CurDAG
->getRegister(Mips::ZERO
, MVT::i32
);
1088 SDValue LoVal
= CurDAG
->getTargetConstant(Lo
, DL
, MVT::i32
);
1089 SDValue HiVal
= CurDAG
->getTargetConstant(Hi
, DL
, MVT::i32
);
1092 Res
= CurDAG
->getMachineNode(Mips::LUi
, DL
, MVT::i32
, HiVal
);
1095 Res
= CurDAG
->getMachineNode(Mips::ORi
, DL
, MVT::i32
,
1096 Hi
? SDValue(Res
, 0) : ZeroVal
, LoVal
);
1098 Res
= CurDAG
->getMachineNode(
1099 Mips::SUBREG_TO_REG
, DL
, MVT::i64
,
1100 CurDAG
->getTargetConstant(((Hi
>> 15) & 0x1), DL
, MVT::i64
),
1102 CurDAG
->getTargetConstant(Mips::sub_32
, DL
, MVT::i64
));
1105 CurDAG
->getMachineNode(Mips::FILL_D
, DL
, MVT::v2i64
, SDValue(Res
, 0));
1107 } else if (SplatValue
.isSignedIntN(64)) {
1108 // If we have a 64 bit Splat value, we perform a similar sequence to the
1112 // lui $res, %highest(val) lui $res, %highest(val)
1113 // ori $res, $res, %higher(val) ori $res, $res, %higher(val)
1114 // lui $res2, %hi(val) lui $res2, %hi(val)
1115 // ori $res2, %res2, %lo(val) ori $res2, %res2, %lo(val)
1116 // $res3 = fill $res2 dinsu $res, $res2, 0, 32
1117 // $res4 = insert.w $res3[1], $res fill.d $res
1120 // The ability to use dinsu is guaranteed as MSA requires MIPSR5. This saves
1121 // having to materialize the value by shifts and ors.
1123 // FIXME: Implement the preferred sequence for MIPS64R6:
1126 // ori $res, $zero, %lo(val)
1127 // daui $res, $res, %hi(val)
1128 // dahi $res, $res, %higher(val)
1129 // dati $res, $res, %highest(cal)
1133 const unsigned Lo
= SplatValue
.getLoBits(16).getZExtValue();
1134 const unsigned Hi
= SplatValue
.lshr(16).getLoBits(16).getZExtValue();
1135 const unsigned Higher
= SplatValue
.lshr(32).getLoBits(16).getZExtValue();
1136 const unsigned Highest
= SplatValue
.lshr(48).getLoBits(16).getZExtValue();
1138 SDValue LoVal
= CurDAG
->getTargetConstant(Lo
, DL
, MVT::i32
);
1139 SDValue HiVal
= CurDAG
->getTargetConstant(Hi
, DL
, MVT::i32
);
1140 SDValue HigherVal
= CurDAG
->getTargetConstant(Higher
, DL
, MVT::i32
);
1141 SDValue HighestVal
= CurDAG
->getTargetConstant(Highest
, DL
, MVT::i32
);
1142 SDValue ZeroVal
= CurDAG
->getRegister(Mips::ZERO
, MVT::i32
);
1144 // Independent of whether we're targeting MIPS64 or not, the basic
1145 // operations are the same. Also, directly use the $zero register if
1146 // the 16 bit chunk is zero.
1148 // For optimization purposes we always synthesize the splat value as
1149 // an i32 value, then if we're targetting MIPS64, use SUBREG_TO_REG
1150 // just before combining the values with dinsu to produce an i64. This
1151 // enables SelectionDAG to aggressively share components of splat values
1154 // FIXME: This is the general constant synthesis problem. This code
1155 // should be factored out into a class shared between all the
1156 // classes that need it. Specifically, for a splat size of 64
1157 // bits that's a negative number we can do better than LUi/ORi
1158 // for the upper 32bits.
1161 Res
= CurDAG
->getMachineNode(Mips::LUi
, DL
, MVT::i32
, HiVal
);
1164 Res
= CurDAG
->getMachineNode(Mips::ORi
, DL
, MVT::i32
,
1165 Hi
? SDValue(Res
, 0) : ZeroVal
, LoVal
);
1169 HiRes
= CurDAG
->getMachineNode(Mips::LUi
, DL
, MVT::i32
, HighestVal
);
1172 HiRes
= CurDAG
->getMachineNode(Mips::ORi
, DL
, MVT::i32
,
1173 Highest
? SDValue(HiRes
, 0) : ZeroVal
,
1178 Res
= CurDAG
->getMachineNode(Mips::FILL_W
, DL
, MVT::v4i32
,
1179 (Hi
|| Lo
) ? SDValue(Res
, 0) : ZeroVal
);
1181 Res
= CurDAG
->getMachineNode(
1182 Mips::INSERT_W
, DL
, MVT::v4i32
, SDValue(Res
, 0),
1183 (Highest
|| Higher
) ? SDValue(HiRes
, 0) : ZeroVal
,
1184 CurDAG
->getTargetConstant(1, DL
, MVT::i32
));
1186 const TargetLowering
*TLI
= getTargetLowering();
1187 const TargetRegisterClass
*RC
=
1188 TLI
->getRegClassFor(ViaVecTy
.getSimpleVT());
1190 Res
= CurDAG
->getMachineNode(
1191 Mips::COPY_TO_REGCLASS
, DL
, ViaVecTy
, SDValue(Res
, 0),
1192 CurDAG
->getTargetConstant(RC
->getID(), DL
, MVT::i32
));
1194 Res
= CurDAG
->getMachineNode(
1195 Mips::SPLATI_D
, DL
, MVT::v2i64
, SDValue(Res
, 0),
1196 CurDAG
->getTargetConstant(0, DL
, MVT::i32
));
1197 } else if (ABI
.IsN64() || ABI
.IsN32()) {
1199 SDValue Zero64Val
= CurDAG
->getRegister(Mips::ZERO_64
, MVT::i64
);
1200 const bool HiResNonZero
= Highest
|| Higher
;
1201 const bool ResNonZero
= Hi
|| Lo
;
1204 HiRes
= CurDAG
->getMachineNode(
1205 Mips::SUBREG_TO_REG
, DL
, MVT::i64
,
1206 CurDAG
->getTargetConstant(((Highest
>> 15) & 0x1), DL
, MVT::i64
),
1208 CurDAG
->getTargetConstant(Mips::sub_32
, DL
, MVT::i64
));
1211 Res
= CurDAG
->getMachineNode(
1212 Mips::SUBREG_TO_REG
, DL
, MVT::i64
,
1213 CurDAG
->getTargetConstant(((Hi
>> 15) & 0x1), DL
, MVT::i64
),
1215 CurDAG
->getTargetConstant(Mips::sub_32
, DL
, MVT::i64
));
1218 // The HiRes is nonzero but Res is $zero => dsll32 HiRes, 0
1219 // The Res is nonzero but HiRes is $zero => dinsu Res, $zero, 32, 32
1220 // Both are non zero => dinsu Res, HiRes, 32, 32
1222 // The obvious "missing" case is when both are zero, but that case is
1223 // handled by the ldi case.
1225 IntegerType
*Int32Ty
=
1226 IntegerType::get(MF
->getFunction().getContext(), 32);
1227 const ConstantInt
*Const32
= ConstantInt::get(Int32Ty
, 32);
1228 SDValue Ops
[4] = {HiResNonZero
? SDValue(HiRes
, 0) : Zero64Val
,
1229 CurDAG
->getConstant(*Const32
, DL
, MVT::i32
),
1230 CurDAG
->getConstant(*Const32
, DL
, MVT::i32
),
1233 Res
= CurDAG
->getMachineNode(Mips::DINSU
, DL
, MVT::i64
, Ops
);
1234 } else if (HiResNonZero
) {
1235 Res
= CurDAG
->getMachineNode(
1236 Mips::DSLL32
, DL
, MVT::i64
, SDValue(HiRes
, 0),
1237 CurDAG
->getTargetConstant(0, DL
, MVT::i32
));
1240 "Zero splat value handled by non-zero 64bit splat synthesis!");
1242 Res
= CurDAG
->getMachineNode(Mips::FILL_D
, DL
, MVT::v2i64
, SDValue(Res
, 0));
1244 llvm_unreachable("Unknown ABI in MipsISelDAGToDAG!");
1249 if (ResVecTy
!= ViaVecTy
) {
1250 // If LdiOp is writing to a different register class to ResVecTy, then
1251 // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
1252 // since the source and destination register sets contain the same
1254 const TargetLowering
*TLI
= getTargetLowering();
1255 MVT ResVecTySimple
= ResVecTy
.getSimpleVT();
1256 const TargetRegisterClass
*RC
= TLI
->getRegClassFor(ResVecTySimple
);
1257 Res
= CurDAG
->getMachineNode(Mips::COPY_TO_REGCLASS
, DL
,
1258 ResVecTy
, SDValue(Res
, 0),
1259 CurDAG
->getTargetConstant(RC
->getID(), DL
,
1263 ReplaceNode(Node
, Res
);
1272 bool MipsSEDAGToDAGISel::
1273 SelectInlineAsmMemoryOperand(const SDValue
&Op
, unsigned ConstraintID
,
1274 std::vector
<SDValue
> &OutOps
) {
1275 SDValue Base
, Offset
;
1277 switch(ConstraintID
) {
1279 llvm_unreachable("Unexpected asm memory constraint");
1280 // All memory constraints can at least accept raw pointers.
1281 case InlineAsm::Constraint_i
:
1282 OutOps
.push_back(Op
);
1283 OutOps
.push_back(CurDAG
->getTargetConstant(0, SDLoc(Op
), MVT::i32
));
1285 case InlineAsm::Constraint_m
:
1286 case InlineAsm::Constraint_o
:
1287 if (selectAddrRegImm16(Op
, Base
, Offset
)) {
1288 OutOps
.push_back(Base
);
1289 OutOps
.push_back(Offset
);
1292 OutOps
.push_back(Op
);
1293 OutOps
.push_back(CurDAG
->getTargetConstant(0, SDLoc(Op
), MVT::i32
));
1295 case InlineAsm::Constraint_R
:
1296 // The 'R' constraint is supposed to be much more complicated than this.
1297 // However, it's becoming less useful due to architectural changes and
1298 // ought to be replaced by other constraints such as 'ZC'.
1299 // For now, support 9-bit signed offsets which is supportable by all
1300 // subtargets for all instructions.
1301 if (selectAddrRegImm9(Op
, Base
, Offset
)) {
1302 OutOps
.push_back(Base
);
1303 OutOps
.push_back(Offset
);
1306 OutOps
.push_back(Op
);
1307 OutOps
.push_back(CurDAG
->getTargetConstant(0, SDLoc(Op
), MVT::i32
));
1309 case InlineAsm::Constraint_ZC
:
1310 // ZC matches whatever the pref, ll, and sc instructions can handle for the
1312 if (Subtarget
->inMicroMipsMode()) {
1313 // On microMIPS, they can handle 12-bit offsets.
1314 if (selectAddrRegImm12(Op
, Base
, Offset
)) {
1315 OutOps
.push_back(Base
);
1316 OutOps
.push_back(Offset
);
1319 } else if (Subtarget
->hasMips32r6()) {
1320 // On MIPS32r6/MIPS64r6, they can only handle 9-bit offsets.
1321 if (selectAddrRegImm9(Op
, Base
, Offset
)) {
1322 OutOps
.push_back(Base
);
1323 OutOps
.push_back(Offset
);
1326 } else if (selectAddrRegImm16(Op
, Base
, Offset
)) {
1327 // Prior to MIPS32r6/MIPS64r6, they can handle 16-bit offsets.
1328 OutOps
.push_back(Base
);
1329 OutOps
.push_back(Offset
);
1332 // In all cases, 0-bit offsets are acceptable.
1333 OutOps
.push_back(Op
);
1334 OutOps
.push_back(CurDAG
->getTargetConstant(0, SDLoc(Op
), MVT::i32
));
1340 FunctionPass
*llvm::createMipsSEISelDag(MipsTargetMachine
&TM
,
1341 CodeGenOpt::Level OptLevel
) {
1342 return new MipsSEDAGToDAGISel(TM
, OptLevel
);