lib/Target/Mips/MipsSEInstrInfo.cpp

   1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "MipsSEInstrInfo.h"
  14 #include "MCTargetDesc/MipsInstPrinter.h"
  15 #include "MipsAnalyzeImmediate.h"
  16 #include "MipsMachineFunction.h"
  17 #include "MipsTargetMachine.h"
  18 #include "llvm/ADT/STLExtras.h"
  19 #include "llvm/CodeGen/MachineInstrBuilder.h"
  20 #include "llvm/CodeGen/MachineRegisterInfo.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "llvm/Support/MathExtras.h"
  23 #include "llvm/Support/TargetRegistry.h"
  24
  25 using namespace llvm;
  26
  27 static unsigned getUnconditionalBranch(const MipsSubtarget &STI) {
  28   if (STI.inMicroMipsMode())
  29     return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
  30   return STI.isPositionIndependent() ? Mips::B : Mips::J;
  31 }
  32
  33 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
  34     : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {}
  35
  36 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
  37   return RI;
  38 }
  39
  40 /// isLoadFromStackSlot - If the specified machine instruction is a direct
  41 /// load from a stack slot, return the virtual or physical register number of
  42 /// the destination along with the FrameIndex of the loaded stack slot.  If
  43 /// not, return 0.  This predicate must return 0 if the instruction has
  44 /// any side effects other than loading from the stack slot.
  45 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
  46                                               int &FrameIndex) const {
  47   unsigned Opc = MI.getOpcode();
  48
  49   if ((Opc == Mips::LW)   || (Opc == Mips::LD)   ||
  50       (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
  51     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
  52         (MI.getOperand(2).isImm()) && // the imm is zero
  53         (isZeroImm(MI.getOperand(2)))) {
  54       FrameIndex = MI.getOperand(1).getIndex();
  55       return MI.getOperand(0).getReg();
  56     }
  57   }
  58
  59   return 0;
  60 }
  61
  62 /// isStoreToStackSlot - If the specified machine instruction is a direct
  63 /// store to a stack slot, return the virtual or physical register number of
  64 /// the source reg along with the FrameIndex of the loaded stack slot.  If
  65 /// not, return 0.  This predicate must return 0 if the instruction has
  66 /// any side effects other than storing to the stack slot.
  67 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
  68                                              int &FrameIndex) const {
  69   unsigned Opc = MI.getOpcode();
  70
  71   if ((Opc == Mips::SW)   || (Opc == Mips::SD)   ||
  72       (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
  73     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
  74         (MI.getOperand(2).isImm()) && // the imm is zero
  75         (isZeroImm(MI.getOperand(2)))) {
  76       FrameIndex = MI.getOperand(1).getIndex();
  77       return MI.getOperand(0).getReg();
  78     }
  79   }
  80   return 0;
  81 }
  82
  83 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  84                                   MachineBasicBlock::iterator I,
  85                                   const DebugLoc &DL, unsigned DestReg,
  86                                   unsigned SrcReg, bool KillSrc) const {
  87   unsigned Opc = 0, ZeroReg = 0;
  88   bool isMicroMips = Subtarget.inMicroMipsMode();
  89
  90   if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
  91     if (Mips::GPR32RegClass.contains(SrcReg)) {
  92       if (isMicroMips)
  93         Opc = Mips::MOVE16_MM;
  94       else
  95         Opc = Mips::OR, ZeroReg = Mips::ZERO;
  96     } else if (Mips::CCRRegClass.contains(SrcReg))
  97       Opc = Mips::CFC1;
  98     else if (Mips::FGR32RegClass.contains(SrcReg))
  99       Opc = Mips::MFC1;
 100     else if (Mips::HI32RegClass.contains(SrcReg)) {
 101       Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
 102       SrcReg = 0;
 103     } else if (Mips::LO32RegClass.contains(SrcReg)) {
 104       Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
 105       SrcReg = 0;
 106     } else if (Mips::HI32DSPRegClass.contains(SrcReg))
 107       Opc = Mips::MFHI_DSP;
 108     else if (Mips::LO32DSPRegClass.contains(SrcReg))
 109       Opc = Mips::MFLO_DSP;
 110     else if (Mips::DSPCCRegClass.contains(SrcReg)) {
 111       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
 112         .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
 113       return;
 114     }
 115     else if (Mips::MSACtrlRegClass.contains(SrcReg))
 116       Opc = Mips::CFCMSA;
 117   }
 118   else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
 119     if (Mips::CCRRegClass.contains(DestReg))
 120       Opc = Mips::CTC1;
 121     else if (Mips::FGR32RegClass.contains(DestReg))
 122       Opc = Mips::MTC1;
 123     else if (Mips::HI32RegClass.contains(DestReg))
 124       Opc = Mips::MTHI, DestReg = 0;
 125     else if (Mips::LO32RegClass.contains(DestReg))
 126       Opc = Mips::MTLO, DestReg = 0;
 127     else if (Mips::HI32DSPRegClass.contains(DestReg))
 128       Opc = Mips::MTHI_DSP;
 129     else if (Mips::LO32DSPRegClass.contains(DestReg))
 130       Opc = Mips::MTLO_DSP;
 131     else if (Mips::DSPCCRegClass.contains(DestReg)) {
 132       BuildMI(MBB, I, DL, get(Mips::WRDSP))
 133         .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
 134         .addReg(DestReg, RegState::ImplicitDefine);
 135       return;
 136     } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
 137       BuildMI(MBB, I, DL, get(Mips::CTCMSA))
 138           .addReg(DestReg)
 139           .addReg(SrcReg, getKillRegState(KillSrc));
 140       return;
 141     }
 142   }
 143   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
 144     Opc = Mips::FMOV_S;
 145   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
 146     Opc = Mips::FMOV_D32;
 147   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
 148     Opc = Mips::FMOV_D64;
 149   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
 150     if (Mips::GPR64RegClass.contains(SrcReg))
 151       Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
 152     else if (Mips::HI64RegClass.contains(SrcReg))
 153       Opc = Mips::MFHI64, SrcReg = 0;
 154     else if (Mips::LO64RegClass.contains(SrcReg))
 155       Opc = Mips::MFLO64, SrcReg = 0;
 156     else if (Mips::FGR64RegClass.contains(SrcReg))
 157       Opc = Mips::DMFC1;
 158   }
 159   else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
 160     if (Mips::HI64RegClass.contains(DestReg))
 161       Opc = Mips::MTHI64, DestReg = 0;
 162     else if (Mips::LO64RegClass.contains(DestReg))
 163       Opc = Mips::MTLO64, DestReg = 0;
 164     else if (Mips::FGR64RegClass.contains(DestReg))
 165       Opc = Mips::DMTC1;
 166   }
 167   else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
 168     if (Mips::MSA128BRegClass.contains(SrcReg))
 169       Opc = Mips::MOVE_V;
 170   }
 171
 172   assert(Opc && "Cannot copy registers");
 173
 174   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
 175
 176   if (DestReg)
 177     MIB.addReg(DestReg, RegState::Define);
 178
 179   if (SrcReg)
 180     MIB.addReg(SrcReg, getKillRegState(KillSrc));
 181
 182   if (ZeroReg)
 183     MIB.addReg(ZeroReg);
 184 }
 185
 186 static bool isORCopyInst(const MachineInstr &MI) {
 187   switch (MI.getOpcode()) {
 188   default:
 189     break;
 190   case Mips::OR_MM:
 191   case Mips::OR:
 192     if (MI.getOperand(2).getReg() == Mips::ZERO)
 193       return true;
 194     break;
 195   case Mips::OR64:
 196     if (MI.getOperand(2).getReg() == Mips::ZERO_64)
 197       return true;
 198     break;
 199   }
 200   return false;
 201 }
 202
 203 /// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true
 204 /// if it is WRDSP instruction.
 205 static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) {
 206   switch (MI.getOpcode()) {
 207   default:
 208    return false;
 209   case Mips::WRDSP:
 210   case Mips::WRDSP_MM:
 211     isWrite = true;
 212     break;
 213   case Mips::RDDSP:
 214   case Mips::RDDSP_MM:
 215     isWrite = false;
 216     break;
 217   }
 218   return true;
 219 }
 220
 221 /// We check for the common case of 'or', as it's MIPS' preferred instruction
 222 /// for GPRs but we have to check the operands to ensure that is the case.
 223 /// Other move instructions for MIPS are directly identifiable.
 224 bool MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI,
 225                                       const MachineOperand *&Src,
 226                                       const MachineOperand *&Dest) const {
 227   bool isDSPControlWrite = false;
 228   // Condition is made to match the creation of WRDSP/RDDSP copy instruction
 229   // from copyPhysReg function.
 230   if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) {
 231     if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4))
 232       return false;
 233     else if (isDSPControlWrite) {
 234       Src = &MI.getOperand(0);
 235       Dest = &MI.getOperand(2);
 236     } else {
 237       Dest = &MI.getOperand(0);
 238       Src = &MI.getOperand(2);
 239     }
 240     return true;
 241   } else if (MI.isMoveReg() || isORCopyInst(MI)) {
 242     Dest = &MI.getOperand(0);
 243     Src = &MI.getOperand(1);
 244     return true;
 245   }
 246   return false;
 247 }
 248
 249 void MipsSEInstrInfo::
 250 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 251                 unsigned SrcReg, bool isKill, int FI,
 252                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
 253                 int64_t Offset) const {
 254   DebugLoc DL;
 255   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
 256
 257   unsigned Opc = 0;
 258
 259   if (Mips::GPR32RegClass.hasSubClassEq(RC))
 260     Opc = Mips::SW;
 261   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
 262     Opc = Mips::SD;
 263   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
 264     Opc = Mips::STORE_ACC64;
 265   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
 266     Opc = Mips::STORE_ACC64DSP;
 267   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
 268     Opc = Mips::STORE_ACC128;
 269   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
 270     Opc = Mips::STORE_CCOND_DSP;
 271   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
 272     Opc = Mips::SWC1;
 273   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
 274     Opc = Mips::SDC1;
 275   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
 276     Opc = Mips::SDC164;
 277   else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
 278     Opc = Mips::ST_B;
 279   else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
 280            TRI->isTypeLegalForClass(*RC, MVT::v8f16))
 281     Opc = Mips::ST_H;
 282   else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
 283            TRI->isTypeLegalForClass(*RC, MVT::v4f32))
 284     Opc = Mips::ST_W;
 285   else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
 286            TRI->isTypeLegalForClass(*RC, MVT::v2f64))
 287     Opc = Mips::ST_D;
 288   else if (Mips::LO32RegClass.hasSubClassEq(RC))
 289     Opc = Mips::SW;
 290   else if (Mips::LO64RegClass.hasSubClassEq(RC))
 291     Opc = Mips::SD;
 292   else if (Mips::HI32RegClass.hasSubClassEq(RC))
 293     Opc = Mips::SW;
 294   else if (Mips::HI64RegClass.hasSubClassEq(RC))
 295     Opc = Mips::SD;
 296   else if (Mips::DSPRRegClass.hasSubClassEq(RC))
 297     Opc = Mips::SWDSP;
 298
 299   // Hi, Lo are normally caller save but they are callee save
 300   // for interrupt handling.
 301   const Function &Func = MBB.getParent()->getFunction();
 302   if (Func.hasFnAttribute("interrupt")) {
 303     if (Mips::HI32RegClass.hasSubClassEq(RC)) {
 304       BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
 305       SrcReg = Mips::K0;
 306     } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
 307       BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
 308       SrcReg = Mips::K0_64;
 309     } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
 310       BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
 311       SrcReg = Mips::K0;
 312     } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
 313       BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
 314       SrcReg = Mips::K0_64;
 315     }
 316   }
 317
 318   assert(Opc && "Register class not handled!");
 319   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
 320     .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
 321 }
 322
 323 void MipsSEInstrInfo::
 324 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
 325                  unsigned DestReg, int FI, const TargetRegisterClass *RC,
 326                  const TargetRegisterInfo *TRI, int64_t Offset) const {
 327   DebugLoc DL;
 328   if (I != MBB.end()) DL = I->getDebugLoc();
 329   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
 330   unsigned Opc = 0;
 331
 332   const Function &Func = MBB.getParent()->getFunction();
 333   bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") &&
 334                          (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
 335                           DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
 336
 337   if (Mips::GPR32RegClass.hasSubClassEq(RC))
 338     Opc = Mips::LW;
 339   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
 340     Opc = Mips::LD;
 341   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
 342     Opc = Mips::LOAD_ACC64;
 343   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
 344     Opc = Mips::LOAD_ACC64DSP;
 345   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
 346     Opc = Mips::LOAD_ACC128;
 347   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
 348     Opc = Mips::LOAD_CCOND_DSP;
 349   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
 350     Opc = Mips::LWC1;
 351   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
 352     Opc = Mips::LDC1;
 353   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
 354     Opc = Mips::LDC164;
 355   else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
 356     Opc = Mips::LD_B;
 357   else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
 358            TRI->isTypeLegalForClass(*RC, MVT::v8f16))
 359     Opc = Mips::LD_H;
 360   else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
 361            TRI->isTypeLegalForClass(*RC, MVT::v4f32))
 362     Opc = Mips::LD_W;
 363   else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
 364            TRI->isTypeLegalForClass(*RC, MVT::v2f64))
 365     Opc = Mips::LD_D;
 366   else if (Mips::HI32RegClass.hasSubClassEq(RC))
 367     Opc = Mips::LW;
 368   else if (Mips::HI64RegClass.hasSubClassEq(RC))
 369     Opc = Mips::LD;
 370   else if (Mips::LO32RegClass.hasSubClassEq(RC))
 371     Opc = Mips::LW;
 372   else if (Mips::LO64RegClass.hasSubClassEq(RC))
 373     Opc = Mips::LD;
 374   else if (Mips::DSPRRegClass.hasSubClassEq(RC))
 375     Opc = Mips::LWDSP;
 376
 377   assert(Opc && "Register class not handled!");
 378
 379   if (!ReqIndirectLoad)
 380     BuildMI(MBB, I, DL, get(Opc), DestReg)
 381         .addFrameIndex(FI)
 382         .addImm(Offset)
 383         .addMemOperand(MMO);
 384   else {
 385     // Load HI/LO through K0. Notably the DestReg is encoded into the
 386     // instruction itself.
 387     unsigned Reg = Mips::K0;
 388     unsigned LdOp = Mips::MTLO;
 389     if (DestReg == Mips::HI0)
 390       LdOp = Mips::MTHI;
 391
 392     if (Subtarget.getABI().ArePtrs64bit()) {
 393       Reg = Mips::K0_64;
 394       if (DestReg == Mips::HI0_64)
 395         LdOp = Mips::MTHI64;
 396       else
 397         LdOp = Mips::MTLO64;
 398     }
 399
 400     BuildMI(MBB, I, DL, get(Opc), Reg)
 401         .addFrameIndex(FI)
 402         .addImm(Offset)
 403         .addMemOperand(MMO);
 404     BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
 405   }
 406 }
 407
 408 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
 409   MachineBasicBlock &MBB = *MI.getParent();
 410   bool isMicroMips = Subtarget.inMicroMipsMode();
 411   unsigned Opc;
 412
 413   switch (MI.getDesc().getOpcode()) {
 414   default:
 415     return false;
 416   case Mips::RetRA:
 417     expandRetRA(MBB, MI);
 418     break;
 419   case Mips::ERet:
 420     expandERet(MBB, MI);
 421     break;
 422   case Mips::PseudoMFHI:
 423     expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
 424     break;
 425   case Mips::PseudoMFHI_MM:
 426     expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);
 427     break;
 428   case Mips::PseudoMFLO:
 429     expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
 430     break;
 431   case Mips::PseudoMFLO_MM:
 432     expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);
 433     break;
 434   case Mips::PseudoMFHI64:
 435     expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
 436     break;
 437   case Mips::PseudoMFLO64:
 438     expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
 439     break;
 440   case Mips::PseudoMTLOHI:
 441     expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
 442     break;
 443   case Mips::PseudoMTLOHI64:
 444     expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
 445     break;
 446   case Mips::PseudoMTLOHI_DSP:
 447     expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
 448     break;
 449   case Mips::PseudoMTLOHI_MM:
 450     expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);
 451     break;
 452   case Mips::PseudoCVT_S_W:
 453     expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
 454     break;
 455   case Mips::PseudoCVT_D32_W:
 456     Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
 457     expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
 458     break;
 459   case Mips::PseudoCVT_S_L:
 460     expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
 461     break;
 462   case Mips::PseudoCVT_D64_W:
 463     Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
 464     expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
 465     break;
 466   case Mips::PseudoCVT_D64_L:
 467     expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
 468     break;
 469   case Mips::BuildPairF64:
 470     expandBuildPairF64(MBB, MI, isMicroMips, false);
 471     break;
 472   case Mips::BuildPairF64_64:
 473     expandBuildPairF64(MBB, MI, isMicroMips, true);
 474     break;
 475   case Mips::ExtractElementF64:
 476     expandExtractElementF64(MBB, MI, isMicroMips, false);
 477     break;
 478   case Mips::ExtractElementF64_64:
 479     expandExtractElementF64(MBB, MI, isMicroMips, true);
 480     break;
 481   case Mips::MIPSeh_return32:
 482   case Mips::MIPSeh_return64:
 483     expandEhReturn(MBB, MI);
 484     break;
 485   }
 486
 487   MBB.erase(MI);
 488   return true;
 489 }
 490
 491 /// getOppositeBranchOpc - Return the inverse of the specified
 492 /// opcode, e.g. turning BEQ to BNE.
 493 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
 494   switch (Opc) {
 495   default:           llvm_unreachable("Illegal opcode!");
 496   case Mips::BEQ:    return Mips::BNE;
 497   case Mips::BEQ_MM: return Mips::BNE_MM;
 498   case Mips::BNE:    return Mips::BEQ;
 499   case Mips::BNE_MM: return Mips::BEQ_MM;
 500   case Mips::BGTZ:   return Mips::BLEZ;
 501   case Mips::BGEZ:   return Mips::BLTZ;
 502   case Mips::BLTZ:   return Mips::BGEZ;
 503   case Mips::BLEZ:   return Mips::BGTZ;
 504   case Mips::BGTZ_MM:   return Mips::BLEZ_MM;
 505   case Mips::BGEZ_MM:   return Mips::BLTZ_MM;
 506   case Mips::BLTZ_MM:   return Mips::BGEZ_MM;
 507   case Mips::BLEZ_MM:   return Mips::BGTZ_MM;
 508   case Mips::BEQ64:  return Mips::BNE64;
 509   case Mips::BNE64:  return Mips::BEQ64;
 510   case Mips::BGTZ64: return Mips::BLEZ64;
 511   case Mips::BGEZ64: return Mips::BLTZ64;
 512   case Mips::BLTZ64: return Mips::BGEZ64;
 513   case Mips::BLEZ64: return Mips::BGTZ64;
 514   case Mips::BC1T:   return Mips::BC1F;
 515   case Mips::BC1F:   return Mips::BC1T;
 516   case Mips::BC1T_MM:   return Mips::BC1F_MM;
 517   case Mips::BC1F_MM:   return Mips::BC1T_MM;
 518   case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
 519   case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
 520   case Mips::BEQZC_MM:  return Mips::BNEZC_MM;
 521   case Mips::BNEZC_MM:  return Mips::BEQZC_MM;
 522   case Mips::BEQZC:  return Mips::BNEZC;
 523   case Mips::BNEZC:  return Mips::BEQZC;
 524   case Mips::BLEZC:  return Mips::BGTZC;
 525   case Mips::BGEZC:  return Mips::BLTZC;
 526   case Mips::BGEC:   return Mips::BLTC;
 527   case Mips::BGTZC:  return Mips::BLEZC;
 528   case Mips::BLTZC:  return Mips::BGEZC;
 529   case Mips::BLTC:   return Mips::BGEC;
 530   case Mips::BGEUC:  return Mips::BLTUC;
 531   case Mips::BLTUC:  return Mips::BGEUC;
 532   case Mips::BEQC:   return Mips::BNEC;
 533   case Mips::BNEC:   return Mips::BEQC;
 534   case Mips::BC1EQZ: return Mips::BC1NEZ;
 535   case Mips::BC1NEZ: return Mips::BC1EQZ;
 536   case Mips::BEQZC_MMR6:  return Mips::BNEZC_MMR6;
 537   case Mips::BNEZC_MMR6:  return Mips::BEQZC_MMR6;
 538   case Mips::BLEZC_MMR6:  return Mips::BGTZC_MMR6;
 539   case Mips::BGEZC_MMR6:  return Mips::BLTZC_MMR6;
 540   case Mips::BGEC_MMR6:   return Mips::BLTC_MMR6;
 541   case Mips::BGTZC_MMR6:  return Mips::BLEZC_MMR6;
 542   case Mips::BLTZC_MMR6:  return Mips::BGEZC_MMR6;
 543   case Mips::BLTC_MMR6:   return Mips::BGEC_MMR6;
 544   case Mips::BGEUC_MMR6:  return Mips::BLTUC_MMR6;
 545   case Mips::BLTUC_MMR6:  return Mips::BGEUC_MMR6;
 546   case Mips::BEQC_MMR6:   return Mips::BNEC_MMR6;
 547   case Mips::BNEC_MMR6:   return Mips::BEQC_MMR6;
 548   case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
 549   case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
 550   case Mips::BEQZC64:  return Mips::BNEZC64;
 551   case Mips::BNEZC64:  return Mips::BEQZC64;
 552   case Mips::BEQC64:   return Mips::BNEC64;
 553   case Mips::BNEC64:   return Mips::BEQC64;
 554   case Mips::BGEC64:   return Mips::BLTC64;
 555   case Mips::BGEUC64:  return Mips::BLTUC64;
 556   case Mips::BLTC64:   return Mips::BGEC64;
 557   case Mips::BLTUC64:  return Mips::BGEUC64;
 558   case Mips::BGTZC64:  return Mips::BLEZC64;
 559   case Mips::BGEZC64:  return Mips::BLTZC64;
 560   case Mips::BLTZC64:  return Mips::BGEZC64;
 561   case Mips::BLEZC64:  return Mips::BGTZC64;
 562   case Mips::BBIT0:  return Mips::BBIT1;
 563   case Mips::BBIT1:  return Mips::BBIT0;
 564   case Mips::BBIT032:  return Mips::BBIT132;
 565   case Mips::BBIT132:  return Mips::BBIT032;
 566   case Mips::BZ_B:   return Mips::BNZ_B;
 567   case Mips::BZ_H:   return Mips::BNZ_H;
 568   case Mips::BZ_W:   return Mips::BNZ_W;
 569   case Mips::BZ_D:   return Mips::BNZ_D;
 570   case Mips::BZ_V:   return Mips::BNZ_V;
 571   case Mips::BNZ_B:  return Mips::BZ_B;
 572   case Mips::BNZ_H:  return Mips::BZ_H;
 573   case Mips::BNZ_W:  return Mips::BZ_W;
 574   case Mips::BNZ_D:  return Mips::BZ_D;
 575   case Mips::BNZ_V:  return Mips::BZ_V;
 576   }
 577 }
 578
 579 /// Adjust SP by Amount bytes.
 580 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
 581                                      MachineBasicBlock &MBB,
 582                                      MachineBasicBlock::iterator I) const {
 583   MipsABIInfo ABI = Subtarget.getABI();
 584   DebugLoc DL;
 585   unsigned ADDiu = ABI.GetPtrAddiuOp();
 586
 587   if (Amount == 0)
 588     return;
 589
 590   if (isInt<16>(Amount)) {
 591     // addi sp, sp, amount
 592     BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
 593   } else {
 594     // For numbers which are not 16bit integers we synthesize Amount inline
 595     // then add or subtract it from sp.
 596     unsigned Opc = ABI.GetPtrAdduOp();
 597     if (Amount < 0) {
 598       Opc = ABI.GetPtrSubuOp();
 599       Amount = -Amount;
 600     }
 601     unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
 602     BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
 603   }
 604 }
 605
 606 /// This function generates the sequence of instructions needed to get the
 607 /// result of adding register REG and immediate IMM.
 608 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
 609                                         MachineBasicBlock::iterator II,
 610                                         const DebugLoc &DL,
 611                                         unsigned *NewImm) const {
 612   MipsAnalyzeImmediate AnalyzeImm;
 613   const MipsSubtarget &STI = Subtarget;
 614   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
 615   unsigned Size = STI.isABI_N64() ? 64 : 32;
 616   unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
 617   unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
 618   const TargetRegisterClass *RC = STI.isABI_N64() ?
 619     &Mips::GPR64RegClass : &Mips::GPR32RegClass;
 620   bool LastInstrIsADDiu = NewImm;
 621
 622   const MipsAnalyzeImmediate::InstSeq &Seq =
 623     AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
 624   MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
 625
 626   assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
 627
 628   // The first instruction can be a LUi, which is different from other
 629   // instructions (ADDiu, ORI and SLL) in that it does not have a register
 630   // operand.
 631   Register Reg = RegInfo.createVirtualRegister(RC);
 632
 633   if (Inst->Opc == LUi)
 634     BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
 635   else
 636     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
 637       .addImm(SignExtend64<16>(Inst->ImmOpnd));
 638
 639   // Build the remaining instructions in Seq.
 640   for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
 641     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
 642       .addImm(SignExtend64<16>(Inst->ImmOpnd));
 643
 644   if (LastInstrIsADDiu)
 645     *NewImm = Inst->ImmOpnd;
 646
 647   return Reg;
 648 }
 649
 650 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
 651   return (Opc == Mips::BEQ    || Opc == Mips::BEQ_MM || Opc == Mips::BNE    ||
 652           Opc == Mips::BNE_MM || Opc == Mips::BGTZ   || Opc == Mips::BGEZ   ||
 653           Opc == Mips::BLTZ   || Opc == Mips::BLEZ   || Opc == Mips::BEQ64  ||
 654           Opc == Mips::BNE64  || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
 655           Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T   ||
 656           Opc == Mips::BC1F   || Opc == Mips::B      || Opc == Mips::J      ||
 657           Opc == Mips::J_MM   || Opc == Mips::B_MM   || Opc == Mips::BEQZC_MM ||
 658           Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC   ||
 659           Opc == Mips::BLTC   || Opc == Mips::BGEC   || Opc == Mips::BLTUC  ||
 660           Opc == Mips::BGEUC  || Opc == Mips::BGTZC  || Opc == Mips::BLEZC  ||
 661           Opc == Mips::BGEZC  || Opc == Mips::BLTZC  || Opc == Mips::BEQZC  ||
 662           Opc == Mips::BNEZC  || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
 663           Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
 664           Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
 665           Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
 666           Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
 667           Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
 668           Opc == Mips::BBIT132 ||  Opc == Mips::BC_MMR6 ||
 669           Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||
 670           Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||
 671           Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||
 672           Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||
 673           Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||
 674           Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;
 675 }
 676
 677 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
 678                                   MachineBasicBlock::iterator I) const {
 679
 680   MachineInstrBuilder MIB;
 681   if (Subtarget.isGP64bit())
 682     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
 683               .addReg(Mips::RA_64, RegState::Undef);
 684   else
 685     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
 686               .addReg(Mips::RA, RegState::Undef);
 687
 688   // Retain any imp-use flags.
 689   for (auto & MO : I->operands()) {
 690     if (MO.isImplicit())
 691       MIB.add(MO);
 692   }
 693 }
 694
 695 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
 696                                  MachineBasicBlock::iterator I) const {
 697   BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
 698 }
 699
 700 std::pair<bool, bool>
 701 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
 702                                  const MachineFunction &MF) const {
 703   const MCInstrDesc &Desc = get(Opc);
 704   assert(Desc.NumOperands == 2 && "Unary instruction expected.");
 705   const MipsRegisterInfo *RI = &getRegisterInfo();
 706   unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
 707   unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
 708
 709   return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
 710 }
 711
 712 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
 713                                          MachineBasicBlock::iterator I,
 714                                          unsigned NewOpc) const {
 715   BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
 716 }
 717
 718 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
 719                                          MachineBasicBlock::iterator I,
 720                                          unsigned LoOpc,
 721                                          unsigned HiOpc,
 722                                          bool HasExplicitDef) const {
 723   // Expand
 724   //  lo_hi pseudomtlohi $gpr0, $gpr1
 725   // to these two instructions:
 726   //  mtlo $gpr0
 727   //  mthi $gpr1
 728
 729   DebugLoc DL = I->getDebugLoc();
 730   const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
 731   MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
 732   MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
 733
 734   // Add lo/hi registers if the mtlo/hi instructions created have explicit
 735   // def registers.
 736   if (HasExplicitDef) {
 737     Register DstReg = I->getOperand(0).getReg();
 738     Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
 739     Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
 740     LoInst.addReg(DstLo, RegState::Define);
 741     HiInst.addReg(DstHi, RegState::Define);
 742   }
 743
 744   LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
 745   HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
 746 }
 747
 748 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
 749                                      MachineBasicBlock::iterator I,
 750                                      unsigned CvtOpc, unsigned MovOpc,
 751                                      bool IsI64) const {
 752   const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
 753   const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
 754   unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
 755   unsigned KillSrc =  getKillRegState(Src.isKill());
 756   DebugLoc DL = I->getDebugLoc();
 757   bool DstIsLarger, SrcIsLarger;
 758
 759   std::tie(DstIsLarger, SrcIsLarger) =
 760       compareOpndSize(CvtOpc, *MBB.getParent());
 761
 762   if (DstIsLarger)
 763     TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
 764
 765   if (SrcIsLarger)
 766     DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
 767
 768   BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
 769   BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
 770 }
 771
 772 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
 773                                               MachineBasicBlock::iterator I,
 774                                               bool isMicroMips,
 775                                               bool FP64) const {
 776   Register DstReg = I->getOperand(0).getReg();
 777   Register SrcReg = I->getOperand(1).getReg();
 778   unsigned N = I->getOperand(2).getImm();
 779   DebugLoc dl = I->getDebugLoc();
 780
 781   assert(N < 2 && "Invalid immediate");
 782   unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
 783   Register SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
 784
 785   // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
 786   // in MipsSEFrameLowering.cpp.
 787   assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
 788
 789   // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
 790   // in MipsSEFrameLowering.cpp.
 791   assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
 792
 793   if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
 794     // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
 795     //        claim to read the whole 64-bits as part of a white lie used to
 796     //        temporarily work around a widespread bug in the -mfp64 support.
 797     //        The problem is that none of the 32-bit fpu ops mention the fact
 798     //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
 799     //        requires a major overhaul of the FPU implementation which can't
 800     //        be done right now due to time constraints.
 801     //        MFHC1 is one of two instructions that are affected since they are
 802     //        the only instructions that don't read the lower 32-bits.
 803     //        We therefore pretend that it reads the bottom 32-bits to
 804     //        artificially create a dependency and prevent the scheduler
 805     //        changing the behaviour of the code.
 806     BuildMI(MBB, I, dl,
 807             get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
 808                             : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
 809             DstReg)
 810         .addReg(SrcReg);
 811   } else
 812     BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
 813 }
 814
 815 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
 816                                          MachineBasicBlock::iterator I,
 817                                          bool isMicroMips, bool FP64) const {
 818   Register DstReg = I->getOperand(0).getReg();
 819   unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
 820   const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
 821   DebugLoc dl = I->getDebugLoc();
 822   const TargetRegisterInfo &TRI = getRegisterInfo();
 823
 824   // When mthc1 is available, use:
 825   //   mtc1 Lo, $fp
 826   //   mthc1 Hi, $fp
 827   //
 828   // Otherwise, for O32 FPXX ABI:
 829   //   spill + reload via ldc1
 830   // This case is handled by the frame lowering code.
 831   //
 832   // Otherwise, for FP32:
 833   //   mtc1 Lo, $fp
 834   //   mtc1 Hi, $fp + 1
 835   //
 836   // The case where dmtc1 is available doesn't need to be handled here
 837   // because it never creates a BuildPairF64 node.
 838
 839   // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
 840   // in MipsSEFrameLowering.cpp.
 841   assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
 842
 843   // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
 844   // in MipsSEFrameLowering.cpp.
 845   assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
 846
 847   BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
 848     .addReg(LoReg);
 849
 850   if (Subtarget.hasMTHC1()) {
 851     // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
 852     //        around a widespread bug in the -mfp64 support.
 853     //        The problem is that none of the 32-bit fpu ops mention the fact
 854     //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
 855     //        requires a major overhaul of the FPU implementation which can't
 856     //        be done right now due to time constraints.
 857     //        MTHC1 is one of two instructions that are affected since they are
 858     //        the only instructions that don't read the lower 32-bits.
 859     //        We therefore pretend that it reads the bottom 32-bits to
 860     //        artificially create a dependency and prevent the scheduler
 861     //        changing the behaviour of the code.
 862     BuildMI(MBB, I, dl,
 863             get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
 864                             : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
 865             DstReg)
 866         .addReg(DstReg)
 867         .addReg(HiReg);
 868   } else if (Subtarget.isABI_FPXX())
 869     llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
 870   else
 871     BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
 872       .addReg(HiReg);
 873 }
 874
 875 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
 876                                      MachineBasicBlock::iterator I) const {
 877   // This pseudo instruction is generated as part of the lowering of
 878   // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
 879   // indirect jump to TargetReg
 880   MipsABIInfo ABI = Subtarget.getABI();
 881   unsigned ADDU = ABI.GetPtrAdduOp();
 882   unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
 883   unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
 884   unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
 885   unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
 886   Register OffsetReg = I->getOperand(0).getReg();
 887   Register TargetReg = I->getOperand(1).getReg();
 888
 889   // addu $ra, $v0, $zero
 890   // addu $sp, $sp, $v1
 891   // jr   $ra (via RetRA)
 892   const TargetMachine &TM = MBB.getParent()->getTarget();
 893   if (TM.isPositionIndependent())
 894     BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
 895         .addReg(TargetReg)
 896         .addReg(ZERO);
 897   BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
 898       .addReg(TargetReg)
 899       .addReg(ZERO);
 900   BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
 901   expandRetRA(MBB, I);
 902 }
 903
 904 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
 905   return new MipsSEInstrInfo(STI);
 906 }