lib/Target/Mips/MipsTargetMachine.cpp

   1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // Implements the info about Mips target spec.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #include "MipsTargetMachine.h"
  14 #include "MCTargetDesc/MipsABIInfo.h"
  15 #include "MCTargetDesc/MipsMCTargetDesc.h"
  16 #include "Mips.h"
  17 #include "Mips16ISelDAGToDAG.h"
  18 #include "MipsSEISelDAGToDAG.h"
  19 #include "MipsSubtarget.h"
  20 #include "MipsTargetObjectFile.h"
  21 #include "TargetInfo/MipsTargetInfo.h"
  22 #include "llvm/ADT/Optional.h"
  23 #include "llvm/ADT/STLExtras.h"
  24 #include "llvm/ADT/StringRef.h"
  25 #include "llvm/Analysis/TargetTransformInfo.h"
  26 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
  27 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
  28 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
  29 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
  30 #include "llvm/CodeGen/BasicTTIImpl.h"
  31 #include "llvm/CodeGen/MachineFunction.h"
  32 #include "llvm/CodeGen/Passes.h"
  33 #include "llvm/CodeGen/TargetPassConfig.h"
  34 #include "llvm/IR/Attributes.h"
  35 #include "llvm/IR/Function.h"
  36 #include "llvm/Support/CodeGen.h"
  37 #include "llvm/Support/Debug.h"
  38 #include "llvm/Support/TargetRegistry.h"
  39 #include "llvm/Support/raw_ostream.h"
  40 #include "llvm/Target/TargetOptions.h"
  41 #include <string>
  42
  43 using namespace llvm;
  44
  45 #define DEBUG_TYPE "mips"
  46
  47 extern "C" void LLVMInitializeMipsTarget() {
  48   // Register the target.
  49   RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget());
  50   RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget());
  51   RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target());
  52   RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget());
  53
  54   PassRegistry *PR = PassRegistry::getPassRegistry();
  55   initializeGlobalISel(*PR);
  56   initializeMipsDelaySlotFillerPass(*PR);
  57   initializeMipsBranchExpansionPass(*PR);
  58   initializeMicroMipsSizeReducePass(*PR);
  59   initializeMipsPreLegalizerCombinerPass(*PR);
  60 }
  61
  62 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
  63                                      const TargetOptions &Options,
  64                                      bool isLittle) {
  65   std::string Ret;
  66   MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
  67
  68   // There are both little and big endian mips.
  69   if (isLittle)
  70     Ret += "e";
  71   else
  72     Ret += "E";
  73
  74   if (ABI.IsO32())
  75     Ret += "-m:m";
  76   else
  77     Ret += "-m:e";
  78
  79   // Pointers are 32 bit on some ABIs.
  80   if (!ABI.IsN64())
  81     Ret += "-p:32:32";
  82
  83   // 8 and 16 bit integers only need to have natural alignment, but try to
  84   // align them to 32 bits. 64 bit integers have natural alignment.
  85   Ret += "-i8:8:32-i16:16:32-i64:64";
  86
  87   // 32 bit registers are always available and the stack is at least 64 bit
  88   // aligned. On N64 64 bit registers are also available and the stack is
  89   // 128 bit aligned.
  90   if (ABI.IsN64() || ABI.IsN32())
  91     Ret += "-n32:64-S128";
  92   else
  93     Ret += "-n32-S64";
  94
  95   return Ret;
  96 }
  97
  98 static Reloc::Model getEffectiveRelocModel(bool JIT,
  99                                            Optional<Reloc::Model> RM) {
 100   if (!RM.hasValue() || JIT)
 101     return Reloc::Static;
 102   return *RM;
 103 }
 104
 105 // On function prologue, the stack is created by decrementing
 106 // its pointer. Once decremented, all references are done with positive
 107 // offset from the stack/frame pointer, using StackGrowsUp enables
 108 // an easier handling.
 109 // Using CodeModel::Large enables different CALL behavior.
 110 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
 111                                      StringRef CPU, StringRef FS,
 112                                      const TargetOptions &Options,
 113                                      Optional<Reloc::Model> RM,
 114                                      Optional<CodeModel::Model> CM,
 115                                      CodeGenOpt::Level OL, bool JIT,
 116                                      bool isLittle)
 117     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
 118                         CPU, FS, Options, getEffectiveRelocModel(JIT, RM),
 119                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
 120       isLittle(isLittle), TLOF(std::make_unique<MipsTargetObjectFile>()),
 121       ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
 122       Subtarget(nullptr),
 123       DefaultSubtarget(TT, CPU, FS, isLittle, *this,
 124                        MaybeAlign(Options.StackAlignmentOverride)),
 125       NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
 126                         isLittle, *this,
 127                         MaybeAlign(Options.StackAlignmentOverride)),
 128       Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
 129                       isLittle, *this,
 130                       MaybeAlign(Options.StackAlignmentOverride)) {
 131   Subtarget = &DefaultSubtarget;
 132   initAsmInfo();
 133 }
 134
 135 MipsTargetMachine::~MipsTargetMachine() = default;
 136
 137 void MipsebTargetMachine::anchor() {}
 138
 139 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
 140                                          StringRef CPU, StringRef FS,
 141                                          const TargetOptions &Options,
 142                                          Optional<Reloc::Model> RM,
 143                                          Optional<CodeModel::Model> CM,
 144                                          CodeGenOpt::Level OL, bool JIT)
 145     : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {}
 146
 147 void MipselTargetMachine::anchor() {}
 148
 149 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
 150                                          StringRef CPU, StringRef FS,
 151                                          const TargetOptions &Options,
 152                                          Optional<Reloc::Model> RM,
 153                                          Optional<CodeModel::Model> CM,
 154                                          CodeGenOpt::Level OL, bool JIT)
 155     : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {}
 156
 157 const MipsSubtarget *
 158 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
 159   Attribute CPUAttr = F.getFnAttribute("target-cpu");
 160   Attribute FSAttr = F.getFnAttribute("target-features");
 161
 162   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
 163                         ? CPUAttr.getValueAsString().str()
 164                         : TargetCPU;
 165   std::string FS = !FSAttr.hasAttribute(Attribute::None)
 166                        ? FSAttr.getValueAsString().str()
 167                        : TargetFS;
 168   bool hasMips16Attr =
 169       !F.getFnAttribute("mips16").hasAttribute(Attribute::None);
 170   bool hasNoMips16Attr =
 171       !F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
 172
 173   bool HasMicroMipsAttr =
 174       !F.getFnAttribute("micromips").hasAttribute(Attribute::None);
 175   bool HasNoMicroMipsAttr =
 176       !F.getFnAttribute("nomicromips").hasAttribute(Attribute::None);
 177
 178   // FIXME: This is related to the code below to reset the target options,
 179   // we need to know whether or not the soft float flag is set on the
 180   // function, so we can enable it as a subtarget feature.
 181   bool softFloat =
 182       F.hasFnAttribute("use-soft-float") &&
 183       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
 184
 185   if (hasMips16Attr)
 186     FS += FS.empty() ? "+mips16" : ",+mips16";
 187   else if (hasNoMips16Attr)
 188     FS += FS.empty() ? "-mips16" : ",-mips16";
 189   if (HasMicroMipsAttr)
 190     FS += FS.empty() ? "+micromips" : ",+micromips";
 191   else if (HasNoMicroMipsAttr)
 192     FS += FS.empty() ? "-micromips" : ",-micromips";
 193   if (softFloat)
 194     FS += FS.empty() ? "+soft-float" : ",+soft-float";
 195
 196   auto &I = SubtargetMap[CPU + FS];
 197   if (!I) {
 198     // This needs to be done before we create a new subtarget since any
 199     // creation will depend on the TM and the code generation flags on the
 200     // function that reside in TargetOptions.
 201     resetTargetOptions(F);
 202     I = std::make_unique<MipsSubtarget>(
 203         TargetTriple, CPU, FS, isLittle, *this,
 204         MaybeAlign(Options.StackAlignmentOverride));
 205   }
 206   return I.get();
 207 }
 208
 209 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
 210   LLVM_DEBUG(dbgs() << "resetSubtarget\n");
 211
 212   Subtarget = &MF->getSubtarget<MipsSubtarget>();
 213 }
 214
 215 namespace {
 216
 217 /// Mips Code Generator Pass Configuration Options.
 218 class MipsPassConfig : public TargetPassConfig {
 219 public:
 220   MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
 221       : TargetPassConfig(TM, PM) {
 222     // The current implementation of long branch pass requires a scratch
 223     // register ($at) to be available before branch instructions. Tail merging
 224     // can break this requirement, so disable it when long branch pass is
 225     // enabled.
 226     EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
 227   }
 228
 229   MipsTargetMachine &getMipsTargetMachine() const {
 230     return getTM<MipsTargetMachine>();
 231   }
 232
 233   const MipsSubtarget &getMipsSubtarget() const {
 234     return *getMipsTargetMachine().getSubtargetImpl();
 235   }
 236
 237   void addIRPasses() override;
 238   bool addInstSelector() override;
 239   void addPreEmitPass() override;
 240   void addPreRegAlloc() override;
 241   bool addIRTranslator() override;
 242   void addPreLegalizeMachineIR() override;
 243   bool addLegalizeMachineIR() override;
 244   bool addRegBankSelect() override;
 245   bool addGlobalInstructionSelect() override;
 246
 247   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
 248 };
 249
 250 } // end anonymous namespace
 251
 252 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
 253   return new MipsPassConfig(*this, PM);
 254 }
 255
 256 std::unique_ptr<CSEConfigBase> MipsPassConfig::getCSEConfig() const {
 257   return getStandardCSEConfigForOpt(TM->getOptLevel());
 258 }
 259
 260 void MipsPassConfig::addIRPasses() {
 261   TargetPassConfig::addIRPasses();
 262   addPass(createAtomicExpandPass());
 263   if (getMipsSubtarget().os16())
 264     addPass(createMipsOs16Pass());
 265   if (getMipsSubtarget().inMips16HardFloat())
 266     addPass(createMips16HardFloatPass());
 267 }
 268 // Install an instruction selector pass using
 269 // the ISelDag to gen Mips code.
 270 bool MipsPassConfig::addInstSelector() {
 271   addPass(createMipsModuleISelDagPass());
 272   addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel()));
 273   addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel()));
 274   return false;
 275 }
 276
 277 void MipsPassConfig::addPreRegAlloc() {
 278   addPass(createMipsOptimizePICCallPass());
 279 }
 280
 281 TargetTransformInfo
 282 MipsTargetMachine::getTargetTransformInfo(const Function &F) {
 283   if (Subtarget->allowMixed16_32()) {
 284     LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n");
 285     // FIXME: This is no longer necessary as the TTI returned is per-function.
 286     return TargetTransformInfo(F.getParent()->getDataLayout());
 287   }
 288
 289   LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
 290   return TargetTransformInfo(BasicTTIImpl(this, F));
 291 }
 292
 293 // Implemented by targets that want to run passes immediately before
 294 // machine code is emitted. return true if -print-machineinstrs should
 295 // print out the code after the passes.
 296 void MipsPassConfig::addPreEmitPass() {
 297   // Expand pseudo instructions that are sensitive to register allocation.
 298   addPass(createMipsExpandPseudoPass());
 299
 300   // The microMIPS size reduction pass performs instruction reselection for
 301   // instructions which can be remapped to a 16 bit instruction.
 302   addPass(createMicroMipsSizeReducePass());
 303
 304   // The delay slot filler pass can potientially create forbidden slot hazards
 305   // for MIPSR6 and therefore it should go before MipsBranchExpansion pass.
 306   addPass(createMipsDelaySlotFillerPass());
 307
 308   // This pass expands branches and takes care about the forbidden slot hazards.
 309   // Expanding branches may potentially create forbidden slot hazards for
 310   // MIPSR6, and fixing such hazard may potentially break a branch by extending
 311   // its offset out of range. That's why this pass combine these two tasks, and
 312   // runs them alternately until one of them finishes without any changes. Only
 313   // then we can be sure that all branches are expanded properly and no hazards
 314   // exists.
 315   // Any new pass should go before this pass.
 316   addPass(createMipsBranchExpansion());
 317
 318   addPass(createMipsConstantIslandPass());
 319 }
 320
 321 bool MipsPassConfig::addIRTranslator() {
 322   addPass(new IRTranslator());
 323   return false;
 324 }
 325
 326 void MipsPassConfig::addPreLegalizeMachineIR() {
 327   addPass(createMipsPreLegalizeCombiner());
 328 }
 329
 330 bool MipsPassConfig::addLegalizeMachineIR() {
 331   addPass(new Legalizer());
 332   return false;
 333 }
 334
 335 bool MipsPassConfig::addRegBankSelect() {
 336   addPass(new RegBankSelect());
 337   return false;
 338 }
 339
 340 bool MipsPassConfig::addGlobalInstructionSelect() {
 341   addPass(new InstructionSelect());
 342   return false;
 343 }