lib/Target/RISCV/Utils/RISCVBaseInfo.h

   1 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains small standalone enum definitions for the RISCV target
  10 // useful for the compiler back-end and the MC libraries.
  11 //
  12 //===----------------------------------------------------------------------===//
  13 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
  14 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
  15
  16 #include "MCTargetDesc/RISCVMCTargetDesc.h"
  17 #include "llvm/ADT/StringRef.h"
  18 #include "llvm/ADT/StringSwitch.h"
  19 #include "llvm/MC/MCInstrDesc.h"
  20 #include "llvm/MC/SubtargetFeature.h"
  21
  22 namespace llvm {
  23
  24 // RISCVII - This namespace holds all of the target specific flags that
  25 // instruction info tracks. All definitions must match RISCVInstrFormats.td.
  26 namespace RISCVII {
  27 enum {
  28   InstFormatPseudo = 0,
  29   InstFormatR = 1,
  30   InstFormatR4 = 2,
  31   InstFormatI = 3,
  32   InstFormatS = 4,
  33   InstFormatB = 5,
  34   InstFormatU = 6,
  35   InstFormatJ = 7,
  36   InstFormatCR = 8,
  37   InstFormatCI = 9,
  38   InstFormatCSS = 10,
  39   InstFormatCIW = 11,
  40   InstFormatCL = 12,
  41   InstFormatCS = 13,
  42   InstFormatCA = 14,
  43   InstFormatCB = 15,
  44   InstFormatCJ = 16,
  45   InstFormatOther = 17,
  46
  47   InstFormatMask = 31
  48 };
  49
  50 enum {
  51   MO_None,
  52   MO_CALL,
  53   MO_PLT,
  54   MO_LO,
  55   MO_HI,
  56   MO_PCREL_LO,
  57   MO_PCREL_HI,
  58   MO_GOT_HI,
  59   MO_TPREL_LO,
  60   MO_TPREL_HI,
  61   MO_TPREL_ADD,
  62   MO_TLS_GOT_HI,
  63   MO_TLS_GD_HI,
  64 };
  65 } // namespace RISCVII
  66
  67 namespace RISCVOp {
  68 enum OperandType : unsigned {
  69   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
  70   OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM,
  71   OPERAND_UIMM5,
  72   OPERAND_UIMM12,
  73   OPERAND_SIMM12,
  74   OPERAND_SIMM13_LSB0,
  75   OPERAND_UIMM20,
  76   OPERAND_SIMM21_LSB0,
  77   OPERAND_UIMMLOG2XLEN,
  78   OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN
  79 };
  80 } // namespace RISCVOp
  81
  82 // Describes the predecessor/successor bits used in the FENCE instruction.
  83 namespace RISCVFenceField {
  84 enum FenceField {
  85   I = 8,
  86   O = 4,
  87   R = 2,
  88   W = 1
  89 };
  90 }
  91
  92 // Describes the supported floating point rounding mode encodings.
  93 namespace RISCVFPRndMode {
  94 enum RoundingMode {
  95   RNE = 0,
  96   RTZ = 1,
  97   RDN = 2,
  98   RUP = 3,
  99   RMM = 4,
 100   DYN = 7,
 101   Invalid
 102 };
 103
 104 inline static StringRef roundingModeToString(RoundingMode RndMode) {
 105   switch (RndMode) {
 106   default:
 107     llvm_unreachable("Unknown floating point rounding mode");
 108   case RISCVFPRndMode::RNE:
 109     return "rne";
 110   case RISCVFPRndMode::RTZ:
 111     return "rtz";
 112   case RISCVFPRndMode::RDN:
 113     return "rdn";
 114   case RISCVFPRndMode::RUP:
 115     return "rup";
 116   case RISCVFPRndMode::RMM:
 117     return "rmm";
 118   case RISCVFPRndMode::DYN:
 119     return "dyn";
 120   }
 121 }
 122
 123 inline static RoundingMode stringToRoundingMode(StringRef Str) {
 124   return StringSwitch<RoundingMode>(Str)
 125       .Case("rne", RISCVFPRndMode::RNE)
 126       .Case("rtz", RISCVFPRndMode::RTZ)
 127       .Case("rdn", RISCVFPRndMode::RDN)
 128       .Case("rup", RISCVFPRndMode::RUP)
 129       .Case("rmm", RISCVFPRndMode::RMM)
 130       .Case("dyn", RISCVFPRndMode::DYN)
 131       .Default(RISCVFPRndMode::Invalid);
 132 }
 133
 134 inline static bool isValidRoundingMode(unsigned Mode) {
 135   switch (Mode) {
 136   default:
 137     return false;
 138   case RISCVFPRndMode::RNE:
 139   case RISCVFPRndMode::RTZ:
 140   case RISCVFPRndMode::RDN:
 141   case RISCVFPRndMode::RUP:
 142   case RISCVFPRndMode::RMM:
 143   case RISCVFPRndMode::DYN:
 144     return true;
 145   }
 146 }
 147 } // namespace RISCVFPRndMode
 148
 149 namespace RISCVSysReg {
 150 struct SysReg {
 151   const char *Name;
 152   unsigned Encoding;
 153   // FIXME: add these additional fields when needed.
 154   // Privilege Access: Read, Write, Read-Only.
 155   // unsigned ReadWrite;
 156   // Privilege Mode: User, System or Machine.
 157   // unsigned Mode;
 158   // Check field name.
 159   // unsigned Extra;
 160   // Register number without the privilege bits.
 161   // unsigned Number;
 162   FeatureBitset FeaturesRequired;
 163   bool isRV32Only;
 164
 165   bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
 166     // Not in 32-bit mode.
 167     if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
 168       return false;
 169     // No required feature associated with the system register.
 170     if (FeaturesRequired.none())
 171       return true;
 172     return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
 173   }
 174 };
 175
 176 #define GET_SysRegsList_DECL
 177 #include "RISCVGenSystemOperands.inc"
 178 } // end namespace RISCVSysReg
 179
 180 namespace RISCVABI {
 181
 182 enum ABI {
 183   ABI_ILP32,
 184   ABI_ILP32F,
 185   ABI_ILP32D,
 186   ABI_ILP32E,
 187   ABI_LP64,
 188   ABI_LP64F,
 189   ABI_LP64D,
 190   ABI_Unknown
 191 };
 192
 193 // Returns the target ABI, or else a StringError if the requested ABIName is
 194 // not supported for the given TT and FeatureBits combination.
 195 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
 196                      StringRef ABIName);
 197
 198 } // namespace RISCVABI
 199
 200 namespace RISCVFeatures {
 201
 202 // Validates if the given combination of features are valid for the target
 203 // triple. Exits with report_fatal_error if not.
 204 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
 205
 206 } // namespace RISCVFeatures
 207
 208 } // namespace llvm
 209
 210 #endif