lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp

   1 //===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 ///
   9 /// \file
  10 /// This file defines the WebAssembly-specific TargetTransformInfo
  11 /// implementation.
  12 ///
  13 //===----------------------------------------------------------------------===//
  14
  15 #include "WebAssemblyTargetTransformInfo.h"
  16 #include "llvm/CodeGen/CostTable.h"
  17 #include "llvm/Support/Debug.h"
  18 using namespace llvm;
  19
  20 #define DEBUG_TYPE "wasmtti"
  21
  22 TargetTransformInfo::PopcntSupportKind
  23 WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
  24   assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
  25   return TargetTransformInfo::PSK_FastHardware;
  26 }
  27
  28 unsigned WebAssemblyTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
  29   unsigned Result = BaseT::getNumberOfRegisters(ClassID);
  30
  31   // For SIMD, use at least 16 registers, as a rough guess.
  32   bool Vector = (ClassID == 1);
  33   if (Vector)
  34     Result = std::max(Result, 16u);
  35
  36   return Result;
  37 }
  38
  39 unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const {
  40   if (Vector && getST()->hasSIMD128())
  41     return 128;
  42
  43   return 64;
  44 }
  45
  46 unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
  47     unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
  48     TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
  49     TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) {
  50
  51   unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
  52       Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
  53
  54   if (auto *VTy = dyn_cast<VectorType>(Ty)) {
  55     switch (Opcode) {
  56     case Instruction::LShr:
  57     case Instruction::AShr:
  58     case Instruction::Shl:
  59       // SIMD128's shifts currently only accept a scalar shift count. For each
  60       // element, we'll need to extract, op, insert. The following is a rough
  61       // approxmation.
  62       if (Opd2Info != TTI::OK_UniformValue &&
  63           Opd2Info != TTI::OK_UniformConstantValue)
  64         Cost = VTy->getNumElements() *
  65                (TargetTransformInfo::TCC_Basic +
  66                 getArithmeticInstrCost(Opcode, VTy->getElementType()) +
  67                 TargetTransformInfo::TCC_Basic);
  68       break;
  69     }
  70   }
  71   return Cost;
  72 }
  73
  74 unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
  75                                                 unsigned Index) {
  76   unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
  77
  78   // SIMD128's insert/extract currently only take constant indices.
  79   if (Index == -1u)
  80     return Cost + 25 * TargetTransformInfo::TCC_Expensive;
  81
  82   return Cost;
  83 }