1 //===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file contains the X86 implementation of the TargetInstrInfo class.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_X86_X86INSTRINFO_H
14 #define LLVM_LIB_TARGET_X86_X86INSTRINFO_H
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "X86InstrFMA3Info.h"
18 #include "X86RegisterInfo.h"
19 #include "llvm/CodeGen/ISDOpcodes.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #define GET_INSTRINFO_HEADER
24 #include "X86GenInstrInfo.inc"
27 class MachineInstrBuilder
;
28 class X86RegisterInfo
;
34 // For instr that was compressed from EVEX to VEX.
35 AC_EVEX_2_VEX
= MachineInstr::TAsmComments
38 /// Return a pair of condition code for the given predicate and whether
39 /// the instruction operands should be swaped to match the condition code.
40 std::pair
<CondCode
, bool> getX86ConditionCode(CmpInst::Predicate Predicate
);
42 /// Return a setcc opcode based on whether it has a memory operand.
43 unsigned getSETOpc(bool HasMemoryOperand
= false);
45 /// Return a cmov opcode for the given register size in bytes, and operand type.
46 unsigned getCMovOpcode(unsigned RegBytes
, bool HasMemoryOperand
= false);
48 // Turn jCC instruction into condition code.
49 CondCode
getCondFromBranch(const MachineInstr
&MI
);
51 // Turn setCC instruction into condition code.
52 CondCode
getCondFromSETCC(const MachineInstr
&MI
);
54 // Turn CMov instruction into condition code.
55 CondCode
getCondFromCMov(const MachineInstr
&MI
);
57 /// GetOppositeBranchCondition - Return the inverse of the specified cond,
58 /// e.g. turning COND_E to COND_NE.
59 CondCode
GetOppositeBranchCondition(CondCode CC
);
61 /// Get the VPCMP immediate for the given condition.
62 unsigned getVPCMPImmForCond(ISD::CondCode CC
);
64 /// Get the VPCMP immediate if the opcodes are swapped.
65 unsigned getSwappedVPCMPImm(unsigned Imm
);
67 /// Get the VPCOM immediate if the opcodes are swapped.
68 unsigned getSwappedVPCOMImm(unsigned Imm
);
70 /// Get the VCMP immediate if the opcodes are swapped.
71 unsigned getSwappedVCMPImm(unsigned Imm
);
75 /// isGlobalStubReference - Return true if the specified TargetFlag operand is
76 /// a reference to a stub for a global, not the global itself.
77 inline static bool isGlobalStubReference(unsigned char TargetFlag
) {
79 case X86II::MO_DLLIMPORT
: // dllimport stub.
80 case X86II::MO_GOTPCREL
: // rip-relative GOT reference.
81 case X86II::MO_GOT
: // normal GOT reference.
82 case X86II::MO_DARWIN_NONLAZY_PIC_BASE
: // Normal $non_lazy_ptr ref.
83 case X86II::MO_DARWIN_NONLAZY
: // Normal $non_lazy_ptr ref.
84 case X86II::MO_COFFSTUB
: // COFF .refptr stub.
91 /// isGlobalRelativeToPICBase - Return true if the specified global value
92 /// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
93 /// is true, the addressing mode has the PIC base register added in (e.g. EBX).
94 inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag
) {
96 case X86II::MO_GOTOFF
: // isPICStyleGOT: local global.
97 case X86II::MO_GOT
: // isPICStyleGOT: other global.
98 case X86II::MO_PIC_BASE_OFFSET
: // Darwin local global.
99 case X86II::MO_DARWIN_NONLAZY_PIC_BASE
: // Darwin/32 external global.
100 case X86II::MO_TLVP
: // ??? Pretty sure..
107 inline static bool isScale(const MachineOperand
&MO
) {
108 return MO
.isImm() && (MO
.getImm() == 1 || MO
.getImm() == 2 ||
109 MO
.getImm() == 4 || MO
.getImm() == 8);
112 inline static bool isLeaMem(const MachineInstr
&MI
, unsigned Op
) {
113 if (MI
.getOperand(Op
).isFI())
115 return Op
+ X86::AddrSegmentReg
<= MI
.getNumOperands() &&
116 MI
.getOperand(Op
+ X86::AddrBaseReg
).isReg() &&
117 isScale(MI
.getOperand(Op
+ X86::AddrScaleAmt
)) &&
118 MI
.getOperand(Op
+ X86::AddrIndexReg
).isReg() &&
119 (MI
.getOperand(Op
+ X86::AddrDisp
).isImm() ||
120 MI
.getOperand(Op
+ X86::AddrDisp
).isGlobal() ||
121 MI
.getOperand(Op
+ X86::AddrDisp
).isCPI() ||
122 MI
.getOperand(Op
+ X86::AddrDisp
).isJTI());
125 inline static bool isMem(const MachineInstr
&MI
, unsigned Op
) {
126 if (MI
.getOperand(Op
).isFI())
128 return Op
+ X86::AddrNumOperands
<= MI
.getNumOperands() &&
129 MI
.getOperand(Op
+ X86::AddrSegmentReg
).isReg() && isLeaMem(MI
, Op
);
132 class X86InstrInfo final
: public X86GenInstrInfo
{
133 X86Subtarget
&Subtarget
;
134 const X86RegisterInfo RI
;
136 virtual void anchor();
138 bool AnalyzeBranchImpl(MachineBasicBlock
&MBB
, MachineBasicBlock
*&TBB
,
139 MachineBasicBlock
*&FBB
,
140 SmallVectorImpl
<MachineOperand
> &Cond
,
141 SmallVectorImpl
<MachineInstr
*> &CondBranches
,
142 bool AllowModify
) const;
145 explicit X86InstrInfo(X86Subtarget
&STI
);
147 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
148 /// such, whenever a client has an instance of instruction info, it should
149 /// always be able to get register info as well (through this method).
151 const X86RegisterInfo
&getRegisterInfo() const { return RI
; }
153 /// Returns the stack pointer adjustment that happens inside the frame
154 /// setup..destroy sequence (e.g. by pushes, or inside the callee).
155 int64_t getFrameAdjustment(const MachineInstr
&I
) const {
156 assert(isFrameInstr(I
));
158 return I
.getOperand(2).getImm();
159 return I
.getOperand(1).getImm();
162 /// Sets the stack pointer adjustment made inside the frame made up by this
164 void setFrameAdjustment(MachineInstr
&I
, int64_t V
) const {
165 assert(isFrameInstr(I
));
167 I
.getOperand(2).setImm(V
);
169 I
.getOperand(1).setImm(V
);
172 /// getSPAdjust - This returns the stack pointer adjustment made by
173 /// this instruction. For x86, we need to handle more complex call
174 /// sequences involving PUSHes.
175 int getSPAdjust(const MachineInstr
&MI
) const override
;
177 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
178 /// extension instruction. That is, it's like a copy where it's legal for the
179 /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
180 /// true, then it's expected the pre-extension value is available as a subreg
181 /// of the result register. This also returns the sub-register index in
183 bool isCoalescableExtInstr(const MachineInstr
&MI
, unsigned &SrcReg
,
184 unsigned &DstReg
, unsigned &SubIdx
) const override
;
186 unsigned isLoadFromStackSlot(const MachineInstr
&MI
,
187 int &FrameIndex
) const override
;
188 unsigned isLoadFromStackSlot(const MachineInstr
&MI
,
190 unsigned &MemBytes
) const override
;
191 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
192 /// stack locations as well. This uses a heuristic so it isn't
193 /// reliable for correctness.
194 unsigned isLoadFromStackSlotPostFE(const MachineInstr
&MI
,
195 int &FrameIndex
) const override
;
197 unsigned isStoreToStackSlot(const MachineInstr
&MI
,
198 int &FrameIndex
) const override
;
199 unsigned isStoreToStackSlot(const MachineInstr
&MI
,
201 unsigned &MemBytes
) const override
;
202 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
203 /// stack locations as well. This uses a heuristic so it isn't
204 /// reliable for correctness.
205 unsigned isStoreToStackSlotPostFE(const MachineInstr
&MI
,
206 int &FrameIndex
) const override
;
208 bool isReallyTriviallyReMaterializable(const MachineInstr
&MI
,
209 AAResults
*AA
) const override
;
210 void reMaterialize(MachineBasicBlock
&MBB
, MachineBasicBlock::iterator MI
,
211 unsigned DestReg
, unsigned SubIdx
,
212 const MachineInstr
&Orig
,
213 const TargetRegisterInfo
&TRI
) const override
;
215 /// Given an operand within a MachineInstr, insert preceding code to put it
216 /// into the right format for a particular kind of LEA instruction. This may
217 /// involve using an appropriate super-register instead (with an implicit use
218 /// of the original) or creating a new virtual register and inserting COPY
219 /// instructions to get the data into the right class.
221 /// Reference parameters are set to indicate how caller should add this
222 /// operand to the LEA instruction.
223 bool classifyLEAReg(MachineInstr
&MI
, const MachineOperand
&Src
,
224 unsigned LEAOpcode
, bool AllowSP
, Register
&NewSrc
,
225 bool &isKill
, MachineOperand
&ImplicitOp
,
226 LiveVariables
*LV
) const;
228 /// convertToThreeAddress - This method must be implemented by targets that
229 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
230 /// may be able to convert a two-address instruction into a true
231 /// three-address instruction on demand. This allows the X86 target (for
232 /// example) to convert ADD and SHL instructions into LEA instructions if they
233 /// would require register copies due to two-addressness.
235 /// This method returns a null pointer if the transformation cannot be
236 /// performed, otherwise it returns the new instruction.
238 MachineInstr
*convertToThreeAddress(MachineFunction::iterator
&MFI
,
240 LiveVariables
*LV
) const override
;
242 /// Returns true iff the routine could find two commutable operands in the
243 /// given machine instruction.
244 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
245 /// input values can be re-defined in this method only if the input values
246 /// are not pre-defined, which is designated by the special value
247 /// 'CommuteAnyOperandIndex' assigned to it.
248 /// If both of indices are pre-defined and refer to some operands, then the
249 /// method simply returns true if the corresponding operands are commutable
250 /// and returns false otherwise.
252 /// For example, calling this method this way:
253 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
254 /// findCommutedOpIndices(MI, Op1, Op2);
255 /// can be interpreted as a query asking to find an operand that would be
256 /// commutable with the operand#1.
257 bool findCommutedOpIndices(const MachineInstr
&MI
, unsigned &SrcOpIdx1
,
258 unsigned &SrcOpIdx2
) const override
;
260 /// Returns an adjusted FMA opcode that must be used in FMA instruction that
261 /// performs the same computations as the given \p MI but which has the
262 /// operands \p SrcOpIdx1 and \p SrcOpIdx2 commuted.
263 /// It may return 0 if it is unsafe to commute the operands.
264 /// Note that a machine instruction (instead of its opcode) is passed as the
265 /// first parameter to make it possible to analyze the instruction's uses and
266 /// commute the first operand of FMA even when it seems unsafe when you look
267 /// at the opcode. For example, it is Ok to commute the first operand of
268 /// VFMADD*SD_Int, if ONLY the lowest 64-bit element of the result is used.
270 /// The returned FMA opcode may differ from the opcode in the given \p MI.
271 /// For example, commuting the operands #1 and #3 in the following FMA
272 /// FMA213 #1, #2, #3
273 /// results into instruction with adjusted opcode:
274 /// FMA231 #3, #2, #1
276 getFMA3OpcodeToCommuteOperands(const MachineInstr
&MI
, unsigned SrcOpIdx1
,
278 const X86InstrFMA3Group
&FMA3Group
) const;
281 bool isUnpredicatedTerminator(const MachineInstr
&MI
) const override
;
282 bool isUnconditionalTailCall(const MachineInstr
&MI
) const override
;
283 bool canMakeTailCallConditional(SmallVectorImpl
<MachineOperand
> &Cond
,
284 const MachineInstr
&TailCall
) const override
;
285 void replaceBranchWithTailCall(MachineBasicBlock
&MBB
,
286 SmallVectorImpl
<MachineOperand
> &Cond
,
287 const MachineInstr
&TailCall
) const override
;
289 bool analyzeBranch(MachineBasicBlock
&MBB
, MachineBasicBlock
*&TBB
,
290 MachineBasicBlock
*&FBB
,
291 SmallVectorImpl
<MachineOperand
> &Cond
,
292 bool AllowModify
) const override
;
294 bool getMemOperandWithOffset(const MachineInstr
&LdSt
,
295 const MachineOperand
*&BaseOp
,
297 const TargetRegisterInfo
*TRI
) const override
;
298 bool analyzeBranchPredicate(MachineBasicBlock
&MBB
,
299 TargetInstrInfo::MachineBranchPredicate
&MBP
,
300 bool AllowModify
= false) const override
;
302 unsigned removeBranch(MachineBasicBlock
&MBB
,
303 int *BytesRemoved
= nullptr) const override
;
304 unsigned insertBranch(MachineBasicBlock
&MBB
, MachineBasicBlock
*TBB
,
305 MachineBasicBlock
*FBB
, ArrayRef
<MachineOperand
> Cond
,
307 int *BytesAdded
= nullptr) const override
;
308 bool canInsertSelect(const MachineBasicBlock
&, ArrayRef
<MachineOperand
> Cond
,
309 unsigned, unsigned, int &, int &, int &) const override
;
310 void insertSelect(MachineBasicBlock
&MBB
, MachineBasicBlock::iterator MI
,
311 const DebugLoc
&DL
, unsigned DstReg
,
312 ArrayRef
<MachineOperand
> Cond
, unsigned TrueReg
,
313 unsigned FalseReg
) const override
;
314 void copyPhysReg(MachineBasicBlock
&MBB
, MachineBasicBlock::iterator MI
,
315 const DebugLoc
&DL
, unsigned DestReg
, unsigned SrcReg
,
316 bool KillSrc
) const override
;
317 void storeRegToStackSlot(MachineBasicBlock
&MBB
,
318 MachineBasicBlock::iterator MI
, unsigned SrcReg
,
319 bool isKill
, int FrameIndex
,
320 const TargetRegisterClass
*RC
,
321 const TargetRegisterInfo
*TRI
) const override
;
323 void loadRegFromStackSlot(MachineBasicBlock
&MBB
,
324 MachineBasicBlock::iterator MI
, unsigned DestReg
,
325 int FrameIndex
, const TargetRegisterClass
*RC
,
326 const TargetRegisterInfo
*TRI
) const override
;
328 bool expandPostRAPseudo(MachineInstr
&MI
) const override
;
330 /// Check whether the target can fold a load that feeds a subreg operand
331 /// (or a subreg operand that feeds a store).
332 bool isSubregFoldable() const override
{ return true; }
334 /// foldMemoryOperand - If this target supports it, fold a load or store of
335 /// the specified stack slot into the specified machine instruction for the
336 /// specified operand(s). If this is possible, the target should perform the
337 /// folding and return true, otherwise it should return false. If it folds
338 /// the instruction, it is likely that the MachineInstruction the iterator
339 /// references has been changed.
341 foldMemoryOperandImpl(MachineFunction
&MF
, MachineInstr
&MI
,
342 ArrayRef
<unsigned> Ops
,
343 MachineBasicBlock::iterator InsertPt
, int FrameIndex
,
344 LiveIntervals
*LIS
= nullptr,
345 VirtRegMap
*VRM
= nullptr) const override
;
347 /// foldMemoryOperand - Same as the previous version except it allows folding
348 /// of any load and store from / to any address, not just from a specific
350 MachineInstr
*foldMemoryOperandImpl(
351 MachineFunction
&MF
, MachineInstr
&MI
, ArrayRef
<unsigned> Ops
,
352 MachineBasicBlock::iterator InsertPt
, MachineInstr
&LoadMI
,
353 LiveIntervals
*LIS
= nullptr) const override
;
355 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
356 /// a store or a load and a store into two or more instruction. If this is
357 /// possible, returns true as well as the new instructions by reference.
359 unfoldMemoryOperand(MachineFunction
&MF
, MachineInstr
&MI
, unsigned Reg
,
360 bool UnfoldLoad
, bool UnfoldStore
,
361 SmallVectorImpl
<MachineInstr
*> &NewMIs
) const override
;
363 bool unfoldMemoryOperand(SelectionDAG
&DAG
, SDNode
*N
,
364 SmallVectorImpl
<SDNode
*> &NewNodes
) const override
;
366 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
367 /// instruction after load / store are unfolded from an instruction of the
368 /// specified opcode. It returns zero if the specified unfolding is not
369 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
370 /// index of the operand which will hold the register holding the loaded
373 getOpcodeAfterMemoryUnfold(unsigned Opc
, bool UnfoldLoad
, bool UnfoldStore
,
374 unsigned *LoadRegIndex
= nullptr) const override
;
376 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
377 /// to determine if two loads are loading from the same base address. It
378 /// should only return true if the base pointers are the same and the
379 /// only differences between the two addresses are the offset. It also returns
380 /// the offsets by reference.
381 bool areLoadsFromSameBasePtr(SDNode
*Load1
, SDNode
*Load2
, int64_t &Offset1
,
382 int64_t &Offset2
) const override
;
384 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
385 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
386 /// should be scheduled togther. On some targets if two loads are loading from
387 /// addresses in the same cache line, it's better if they are scheduled
388 /// together. This function takes two integers that represent the load offsets
389 /// from the common base address. It returns true if it decides it's desirable
390 /// to schedule the two loads together. "NumLoads" is the number of loads that
391 /// have already been scheduled after Load1.
392 bool shouldScheduleLoadsNear(SDNode
*Load1
, SDNode
*Load2
, int64_t Offset1
,
394 unsigned NumLoads
) const override
;
396 void getNoop(MCInst
&NopInst
) const override
;
399 reverseBranchCondition(SmallVectorImpl
<MachineOperand
> &Cond
) const override
;
401 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
402 /// instruction that defines the specified register class.
403 bool isSafeToMoveRegClassDefs(const TargetRegisterClass
*RC
) const override
;
405 /// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction tha
406 /// would clobber the EFLAGS condition register. Note the result may be
407 /// conservative. If it cannot definitely determine the safety after visiting
408 /// a few instructions in each direction it assumes it's not safe.
409 bool isSafeToClobberEFLAGS(MachineBasicBlock
&MBB
,
410 MachineBasicBlock::iterator I
) const {
411 return MBB
.computeRegisterLiveness(&RI
, X86::EFLAGS
, I
, 4) ==
412 MachineBasicBlock::LQR_Dead
;
415 /// True if MI has a condition code def, e.g. EFLAGS, that is
417 bool hasLiveCondCodeDef(MachineInstr
&MI
) const;
419 /// getGlobalBaseReg - Return a virtual register initialized with the
420 /// the global base register value. Output instructions required to
421 /// initialize the register in the function entry block, if necessary.
423 unsigned getGlobalBaseReg(MachineFunction
*MF
) const;
425 std::pair
<uint16_t, uint16_t>
426 getExecutionDomain(const MachineInstr
&MI
) const override
;
428 uint16_t getExecutionDomainCustom(const MachineInstr
&MI
) const;
430 void setExecutionDomain(MachineInstr
&MI
, unsigned Domain
) const override
;
432 bool setExecutionDomainCustom(MachineInstr
&MI
, unsigned Domain
) const;
435 getPartialRegUpdateClearance(const MachineInstr
&MI
, unsigned OpNum
,
436 const TargetRegisterInfo
*TRI
) const override
;
437 unsigned getUndefRegClearance(const MachineInstr
&MI
, unsigned &OpNum
,
438 const TargetRegisterInfo
*TRI
) const override
;
439 void breakPartialRegDependency(MachineInstr
&MI
, unsigned OpNum
,
440 const TargetRegisterInfo
*TRI
) const override
;
442 MachineInstr
*foldMemoryOperandImpl(MachineFunction
&MF
, MachineInstr
&MI
,
444 ArrayRef
<MachineOperand
> MOs
,
445 MachineBasicBlock::iterator InsertPt
,
446 unsigned Size
, unsigned Alignment
,
447 bool AllowCommute
) const;
449 bool isHighLatencyDef(int opc
) const override
;
451 bool hasHighOperandLatency(const TargetSchedModel
&SchedModel
,
452 const MachineRegisterInfo
*MRI
,
453 const MachineInstr
&DefMI
, unsigned DefIdx
,
454 const MachineInstr
&UseMI
,
455 unsigned UseIdx
) const override
;
457 bool useMachineCombiner() const override
{ return true; }
459 bool isAssociativeAndCommutative(const MachineInstr
&Inst
) const override
;
461 bool hasReassociableOperands(const MachineInstr
&Inst
,
462 const MachineBasicBlock
*MBB
) const override
;
464 void setSpecialOperandAttr(MachineInstr
&OldMI1
, MachineInstr
&OldMI2
,
465 MachineInstr
&NewMI1
,
466 MachineInstr
&NewMI2
) const override
;
468 /// analyzeCompare - For a comparison instruction, return the source registers
469 /// in SrcReg and SrcReg2 if having two register operands, and the value it
470 /// compares against in CmpValue. Return true if the comparison instruction
472 bool analyzeCompare(const MachineInstr
&MI
, unsigned &SrcReg
,
473 unsigned &SrcReg2
, int &CmpMask
,
474 int &CmpValue
) const override
;
476 /// optimizeCompareInstr - Check if there exists an earlier instruction that
477 /// operates on the same source operands and sets flags in the same way as
478 /// Compare; remove Compare if possible.
479 bool optimizeCompareInstr(MachineInstr
&CmpInstr
, unsigned SrcReg
,
480 unsigned SrcReg2
, int CmpMask
, int CmpValue
,
481 const MachineRegisterInfo
*MRI
) const override
;
483 /// optimizeLoadInstr - Try to remove the load by folding it to a register
484 /// operand at the use. We fold the load instructions if and only if the
485 /// def and use are in the same BB. We only look at one load and see
486 /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register
487 /// defined by the load we are trying to fold. DefMI returns the machine
488 /// instruction that defines FoldAsLoadDefReg, and the function returns
489 /// the machine instruction generated due to folding.
490 MachineInstr
*optimizeLoadInstr(MachineInstr
&MI
,
491 const MachineRegisterInfo
*MRI
,
492 unsigned &FoldAsLoadDefReg
,
493 MachineInstr
*&DefMI
) const override
;
495 std::pair
<unsigned, unsigned>
496 decomposeMachineOperandsTargetFlags(unsigned TF
) const override
;
498 ArrayRef
<std::pair
<unsigned, const char *>>
499 getSerializableDirectMachineOperandTargetFlags() const override
;
501 virtual outliner::OutlinedFunction
getOutliningCandidateInfo(
502 std::vector
<outliner::Candidate
> &RepeatedSequenceLocs
) const override
;
504 bool isFunctionSafeToOutlineFrom(MachineFunction
&MF
,
505 bool OutlineFromLinkOnceODRs
) const override
;
508 getOutliningType(MachineBasicBlock::iterator
&MIT
, unsigned Flags
) const override
;
510 void buildOutlinedFrame(MachineBasicBlock
&MBB
, MachineFunction
&MF
,
511 const outliner::OutlinedFunction
&OF
) const override
;
513 MachineBasicBlock::iterator
514 insertOutlinedCall(Module
&M
, MachineBasicBlock
&MBB
,
515 MachineBasicBlock::iterator
&It
, MachineFunction
&MF
,
516 const outliner::Candidate
&C
) const override
;
518 #define GET_INSTRINFO_HELPER_DECLS
519 #include "X86GenInstrInfo.inc"
521 static bool hasLockPrefix(const MachineInstr
&MI
) {
522 return MI
.getDesc().TSFlags
& X86II::LOCK
;
525 Optional
<ParamLoadedValue
>
526 describeLoadedValue(const MachineInstr
&MI
) const override
;
529 /// Commutes the operands in the given instruction by changing the operands
530 /// order and/or changing the instruction's opcode and/or the immediate value
533 /// The arguments 'CommuteOpIdx1' and 'CommuteOpIdx2' specify the operands
536 /// Do not call this method for a non-commutable instruction or
537 /// non-commutable operands.
538 /// Even though the instruction is commutable, the method may still
539 /// fail to commute the operands, null pointer is returned in such cases.
540 MachineInstr
*commuteInstructionImpl(MachineInstr
&MI
, bool NewMI
,
541 unsigned CommuteOpIdx1
,
542 unsigned CommuteOpIdx2
) const override
;
544 /// If the specific machine instruction is a instruction that moves/copies
545 /// value from one register to another register return true along with
546 /// @Source machine operand and @Destination machine operand.
547 bool isCopyInstrImpl(const MachineInstr
&MI
, const MachineOperand
*&Source
,
548 const MachineOperand
*&Destination
) const override
;
551 /// This is a helper for convertToThreeAddress for 8 and 16-bit instructions.
552 /// We use 32-bit LEA to form 3-address code by promoting to a 32-bit
553 /// super-register and then truncating back down to a 8/16-bit sub-register.
554 MachineInstr
*convertToThreeAddressWithLEA(unsigned MIOpc
,
555 MachineFunction::iterator
&MFI
,
558 bool Is8BitOp
) const;
560 /// Handles memory folding for special case instructions, for instance those
561 /// requiring custom manipulation of the address.
562 MachineInstr
*foldMemoryOperandCustom(MachineFunction
&MF
, MachineInstr
&MI
,
564 ArrayRef
<MachineOperand
> MOs
,
565 MachineBasicBlock::iterator InsertPt
,
566 unsigned Size
, unsigned Align
) const;
568 /// isFrameOperand - Return true and the FrameIndex if the specified
569 /// operand and follow operands form a reference to the stack frame.
570 bool isFrameOperand(const MachineInstr
&MI
, unsigned int Op
,
571 int &FrameIndex
) const;
573 /// Returns true iff the routine could find two commutable operands in the
574 /// given machine instruction with 3 vector inputs.
575 /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. Their
576 /// input values can be re-defined in this method only if the input values
577 /// are not pre-defined, which is designated by the special value
578 /// 'CommuteAnyOperandIndex' assigned to it.
579 /// If both of indices are pre-defined and refer to some operands, then the
580 /// method simply returns true if the corresponding operands are commutable
581 /// and returns false otherwise.
583 /// For example, calling this method this way:
584 /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex;
585 /// findThreeSrcCommutedOpIndices(MI, Op1, Op2);
586 /// can be interpreted as a query asking to find an operand that would be
587 /// commutable with the operand#1.
589 /// If IsIntrinsic is set, operand 1 will be ignored for commuting.
590 bool findThreeSrcCommutedOpIndices(const MachineInstr
&MI
,
593 bool IsIntrinsic
= false) const;