| blob | b59c8a1d9550d17839c68f29f1c28414c1f395cd |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=armv6 < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM6
3 ; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM78,ARM7
4 ; RUN: llc -mtriple=armv8a < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM78,ARM8
5 ; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB6
6 ; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB78,THUMB7
7 ; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB78,THUMB8
9 ; We are looking for the following pattern here:
10 ; (X & (C << Y)) ==/!= 0
11 ; It may be optimal to hoist the constant:
12 ; ((X l>> Y) & C) ==/!= 0
14 ;------------------------------------------------------------------------------;
15 ; A few scalar test
16 ;------------------------------------------------------------------------------;
18 ; i8 scalar
20 define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
21 ; ARM-LABEL: scalar_i8_signbit_eq:
22 ; ARM: @ %bb.0:
23 ; ARM-NEXT: uxtb r1, r1
24 ; ARM-NEXT: uxtb r0, r0
25 ; ARM-NEXT: lsr r0, r0, r1
26 ; ARM-NEXT: mov r1, #1
27 ; ARM-NEXT: uxtb r0, r0
28 ; ARM-NEXT: eor r0, r1, r0, lsr #7
29 ; ARM-NEXT: bx lr
30 ;
31 ; THUMB6-LABEL: scalar_i8_signbit_eq:
32 ; THUMB6: @ %bb.0:
33 ; THUMB6-NEXT: uxtb r1, r1
34 ; THUMB6-NEXT: uxtb r0, r0
35 ; THUMB6-NEXT: lsrs r0, r1
36 ; THUMB6-NEXT: movs r1, #128
37 ; THUMB6-NEXT: ands r1, r0
38 ; THUMB6-NEXT: rsbs r0, r1, #0
39 ; THUMB6-NEXT: adcs r0, r1
40 ; THUMB6-NEXT: bx lr
41 ;
42 ; THUMB7-LABEL: scalar_i8_signbit_eq:
43 ; THUMB7: @ %bb.0:
44 ; THUMB7-NEXT: uxtb r1, r1
45 ; THUMB7-NEXT: uxtb r0, r0
46 ; THUMB7-NEXT: lsrs r0, r1
47 ; THUMB7-NEXT: movs r1, #1
48 ; THUMB7-NEXT: uxtb r0, r0
49 ; THUMB7-NEXT: eor.w r0, r1, r0, lsr #7
50 ; THUMB7-NEXT: bx lr
51 ;
52 ; THUMB8-LABEL: scalar_i8_signbit_eq:
53 ; THUMB8: @ %bb.0:
54 ; THUMB8-NEXT: uxtb r0, r0
55 ; THUMB8-NEXT: uxtb r1, r1
56 ; THUMB8-NEXT: lsrs r0, r1
57 ; THUMB8-NEXT: movs r1, #1
58 ; THUMB8-NEXT: uxtb r0, r0
59 ; THUMB8-NEXT: eor.w r0, r1, r0, lsr #7
60 ; THUMB8-NEXT: bx lr
61 %t0 = shl i8 128, %y
62 %t1 = and i8 %t0, %x
63 %res = icmp eq i8 %t1, 0
64 ret i1 %res
65 }
67 define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {
68 ; ARM-LABEL: scalar_i8_lowestbit_eq:
69 ; ARM: @ %bb.0:
70 ; ARM-NEXT: uxtb r1, r1
71 ; ARM-NEXT: uxtb r0, r0
72 ; ARM-NEXT: mov r2, #1
73 ; ARM-NEXT: bic r0, r2, r0, lsr r1
74 ; ARM-NEXT: bx lr
75 ;
76 ; THUMB6-LABEL: scalar_i8_lowestbit_eq:
77 ; THUMB6: @ %bb.0:
78 ; THUMB6-NEXT: uxtb r1, r1
79 ; THUMB6-NEXT: uxtb r0, r0
80 ; THUMB6-NEXT: lsrs r0, r1
81 ; THUMB6-NEXT: movs r1, #1
82 ; THUMB6-NEXT: ands r1, r0
83 ; THUMB6-NEXT: rsbs r0, r1, #0
84 ; THUMB6-NEXT: adcs r0, r1
85 ; THUMB6-NEXT: bx lr
86 ;
87 ; THUMB7-LABEL: scalar_i8_lowestbit_eq:
88 ; THUMB7: @ %bb.0:
89 ; THUMB7-NEXT: uxtb r1, r1
90 ; THUMB7-NEXT: uxtb r0, r0
91 ; THUMB7-NEXT: lsrs r0, r1
92 ; THUMB7-NEXT: movs r1, #1
93 ; THUMB7-NEXT: bic.w r0, r1, r0
94 ; THUMB7-NEXT: bx lr
95 ;
96 ; THUMB8-LABEL: scalar_i8_lowestbit_eq:
97 ; THUMB8: @ %bb.0:
98 ; THUMB8-NEXT: uxtb r0, r0
99 ; THUMB8-NEXT: uxtb r1, r1
100 ; THUMB8-NEXT: lsrs r0, r1
101 ; THUMB8-NEXT: movs r1, #1
102 ; THUMB8-NEXT: bic.w r0, r1, r0
103 ; THUMB8-NEXT: bx lr
104 %t0 = shl i8 1, %y
105 %t1 = and i8 %t0, %x
106 %res = icmp eq i8 %t1, 0
107 ret i1 %res
108 }
110 define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {
111 ; ARM-LABEL: scalar_i8_bitsinmiddle_eq:
112 ; ARM: @ %bb.0:
113 ; ARM-NEXT: uxtb r1, r1
114 ; ARM-NEXT: uxtb r0, r0
115 ; ARM-NEXT: mov r2, #24
116 ; ARM-NEXT: and r0, r2, r0, lsr r1
117 ; ARM-NEXT: clz r0, r0
118 ; ARM-NEXT: lsr r0, r0, #5
119 ; ARM-NEXT: bx lr
120 ;
121 ; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq:
122 ; THUMB6: @ %bb.0:
123 ; THUMB6-NEXT: uxtb r1, r1
124 ; THUMB6-NEXT: uxtb r0, r0
125 ; THUMB6-NEXT: lsrs r0, r1
126 ; THUMB6-NEXT: movs r1, #24
127 ; THUMB6-NEXT: ands r1, r0
128 ; THUMB6-NEXT: rsbs r0, r1, #0
129 ; THUMB6-NEXT: adcs r0, r1
130 ; THUMB6-NEXT: bx lr
131 ;
132 ; THUMB7-LABEL: scalar_i8_bitsinmiddle_eq:
133 ; THUMB7: @ %bb.0:
134 ; THUMB7-NEXT: uxtb r1, r1
135 ; THUMB7-NEXT: uxtb r0, r0
136 ; THUMB7-NEXT: lsrs r0, r1
137 ; THUMB7-NEXT: and r0, r0, #24
138 ; THUMB7-NEXT: clz r0, r0
139 ; THUMB7-NEXT: lsrs r0, r0, #5
140 ; THUMB7-NEXT: bx lr
141 ;
142 ; THUMB8-LABEL: scalar_i8_bitsinmiddle_eq:
143 ; THUMB8: @ %bb.0:
144 ; THUMB8-NEXT: uxtb r0, r0
145 ; THUMB8-NEXT: uxtb r1, r1
146 ; THUMB8-NEXT: lsrs r0, r1
147 ; THUMB8-NEXT: and r0, r0, #24
148 ; THUMB8-NEXT: clz r0, r0
149 ; THUMB8-NEXT: lsrs r0, r0, #5
150 ; THUMB8-NEXT: bx lr
151 %t0 = shl i8 24, %y
152 %t1 = and i8 %t0, %x
153 %res = icmp eq i8 %t1, 0
154 ret i1 %res
155 }
157 ; i16 scalar
159 define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
160 ; ARM-LABEL: scalar_i16_signbit_eq:
161 ; ARM: @ %bb.0:
162 ; ARM-NEXT: uxth r1, r1
163 ; ARM-NEXT: uxth r0, r0
164 ; ARM-NEXT: lsr r0, r0, r1
165 ; ARM-NEXT: mov r1, #1
166 ; ARM-NEXT: uxth r0, r0
167 ; ARM-NEXT: eor r0, r1, r0, lsr #15
168 ; ARM-NEXT: bx lr
169 ;
170 ; THUMB6-LABEL: scalar_i16_signbit_eq:
171 ; THUMB6: @ %bb.0:
172 ; THUMB6-NEXT: uxth r1, r1
173 ; THUMB6-NEXT: uxth r0, r0
174 ; THUMB6-NEXT: lsrs r0, r1
175 ; THUMB6-NEXT: movs r1, #1
176 ; THUMB6-NEXT: lsls r1, r1, #15
177 ; THUMB6-NEXT: ands r1, r0
178 ; THUMB6-NEXT: rsbs r0, r1, #0
179 ; THUMB6-NEXT: adcs r0, r1
180 ; THUMB6-NEXT: bx lr
181 ;
182 ; THUMB7-LABEL: scalar_i16_signbit_eq:
183 ; THUMB7: @ %bb.0:
184 ; THUMB7-NEXT: uxth r1, r1
185 ; THUMB7-NEXT: uxth r0, r0
186 ; THUMB7-NEXT: lsrs r0, r1
187 ; THUMB7-NEXT: movs r1, #1
188 ; THUMB7-NEXT: uxth r0, r0
189 ; THUMB7-NEXT: eor.w r0, r1, r0, lsr #15
190 ; THUMB7-NEXT: bx lr
191 ;
192 ; THUMB8-LABEL: scalar_i16_signbit_eq:
193 ; THUMB8: @ %bb.0:
194 ; THUMB8-NEXT: uxth r0, r0
195 ; THUMB8-NEXT: uxth r1, r1
196 ; THUMB8-NEXT: lsrs r0, r1
197 ; THUMB8-NEXT: movs r1, #1
198 ; THUMB8-NEXT: uxth r0, r0
199 ; THUMB8-NEXT: eor.w r0, r1, r0, lsr #15
200 ; THUMB8-NEXT: bx lr
201 %t0 = shl i16 32768, %y
202 %t1 = and i16 %t0, %x
203 %res = icmp eq i16 %t1, 0
204 ret i1 %res
205 }
207 define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {
208 ; ARM-LABEL: scalar_i16_lowestbit_eq:
209 ; ARM: @ %bb.0:
210 ; ARM-NEXT: uxth r1, r1
211 ; ARM-NEXT: uxth r0, r0
212 ; ARM-NEXT: mov r2, #1
213 ; ARM-NEXT: bic r0, r2, r0, lsr r1
214 ; ARM-NEXT: bx lr
215 ;
216 ; THUMB6-LABEL: scalar_i16_lowestbit_eq:
217 ; THUMB6: @ %bb.0:
218 ; THUMB6-NEXT: uxth r1, r1
219 ; THUMB6-NEXT: uxth r0, r0
220 ; THUMB6-NEXT: lsrs r0, r1
221 ; THUMB6-NEXT: movs r1, #1
222 ; THUMB6-NEXT: ands r1, r0
223 ; THUMB6-NEXT: rsbs r0, r1, #0
224 ; THUMB6-NEXT: adcs r0, r1
225 ; THUMB6-NEXT: bx lr
226 ;
227 ; THUMB7-LABEL: scalar_i16_lowestbit_eq:
228 ; THUMB7: @ %bb.0:
229 ; THUMB7-NEXT: uxth r1, r1
230 ; THUMB7-NEXT: uxth r0, r0
231 ; THUMB7-NEXT: lsrs r0, r1
232 ; THUMB7-NEXT: movs r1, #1
233 ; THUMB7-NEXT: bic.w r0, r1, r0
234 ; THUMB7-NEXT: bx lr
235 ;
236 ; THUMB8-LABEL: scalar_i16_lowestbit_eq:
237 ; THUMB8: @ %bb.0:
238 ; THUMB8-NEXT: uxth r0, r0
239 ; THUMB8-NEXT: uxth r1, r1
240 ; THUMB8-NEXT: lsrs r0, r1
241 ; THUMB8-NEXT: movs r1, #1
242 ; THUMB8-NEXT: bic.w r0, r1, r0
243 ; THUMB8-NEXT: bx lr
244 %t0 = shl i16 1, %y
245 %t1 = and i16 %t0, %x
246 %res = icmp eq i16 %t1, 0
247 ret i1 %res
248 }
250 define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {
251 ; ARM-LABEL: scalar_i16_bitsinmiddle_eq:
252 ; ARM: @ %bb.0:
253 ; ARM-NEXT: uxth r1, r1
254 ; ARM-NEXT: uxth r0, r0
255 ; ARM-NEXT: mov r2, #4080
256 ; ARM-NEXT: and r0, r2, r0, lsr r1
257 ; ARM-NEXT: clz r0, r0
258 ; ARM-NEXT: lsr r0, r0, #5
259 ; ARM-NEXT: bx lr
260 ;
261 ; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq:
262 ; THUMB6: @ %bb.0:
263 ; THUMB6-NEXT: uxth r1, r1
264 ; THUMB6-NEXT: uxth r0, r0
265 ; THUMB6-NEXT: lsrs r0, r1
266 ; THUMB6-NEXT: movs r1, #255
267 ; THUMB6-NEXT: lsls r1, r1, #4
268 ; THUMB6-NEXT: ands r1, r0
269 ; THUMB6-NEXT: rsbs r0, r1, #0
270 ; THUMB6-NEXT: adcs r0, r1
271 ; THUMB6-NEXT: bx lr
272 ;
273 ; THUMB7-LABEL: scalar_i16_bitsinmiddle_eq:
274 ; THUMB7: @ %bb.0:
275 ; THUMB7-NEXT: uxth r1, r1
276 ; THUMB7-NEXT: uxth r0, r0
277 ; THUMB7-NEXT: lsrs r0, r1
278 ; THUMB7-NEXT: and r0, r0, #4080
279 ; THUMB7-NEXT: clz r0, r0
280 ; THUMB7-NEXT: lsrs r0, r0, #5
281 ; THUMB7-NEXT: bx lr
282 ;
283 ; THUMB8-LABEL: scalar_i16_bitsinmiddle_eq:
284 ; THUMB8: @ %bb.0:
285 ; THUMB8-NEXT: uxth r0, r0
286 ; THUMB8-NEXT: uxth r1, r1
287 ; THUMB8-NEXT: lsrs r0, r1
288 ; THUMB8-NEXT: and r0, r0, #4080
289 ; THUMB8-NEXT: clz r0, r0
290 ; THUMB8-NEXT: lsrs r0, r0, #5
291 ; THUMB8-NEXT: bx lr
292 %t0 = shl i16 4080, %y
293 %t1 = and i16 %t0, %x
294 %res = icmp eq i16 %t1, 0
295 ret i1 %res
296 }
298 ; i32 scalar
300 define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind {
301 ; ARM-LABEL: scalar_i32_signbit_eq:
302 ; ARM: @ %bb.0:
303 ; ARM-NEXT: mvn r0, r0, lsr r1
304 ; ARM-NEXT: lsr r0, r0, #31
305 ; ARM-NEXT: bx lr
306 ;
307 ; THUMB6-LABEL: scalar_i32_signbit_eq:
308 ; THUMB6: @ %bb.0:
309 ; THUMB6-NEXT: lsrs r0, r1
310 ; THUMB6-NEXT: movs r1, #1
311 ; THUMB6-NEXT: lsls r1, r1, #31
312 ; THUMB6-NEXT: ands r1, r0
313 ; THUMB6-NEXT: rsbs r0, r1, #0
314 ; THUMB6-NEXT: adcs r0, r1
315 ; THUMB6-NEXT: bx lr
316 ;
317 ; THUMB78-LABEL: scalar_i32_signbit_eq:
318 ; THUMB78: @ %bb.0:
319 ; THUMB78-NEXT: lsrs r0, r1
320 ; THUMB78-NEXT: mvns r0, r0
321 ; THUMB78-NEXT: lsrs r0, r0, #31
322 ; THUMB78-NEXT: bx lr
323 %t0 = shl i32 2147483648, %y
324 %t1 = and i32 %t0, %x
325 %res = icmp eq i32 %t1, 0
326 ret i1 %res
327 }
329 define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind {
330 ; ARM-LABEL: scalar_i32_lowestbit_eq:
331 ; ARM: @ %bb.0:
332 ; ARM-NEXT: mov r2, #1
333 ; ARM-NEXT: bic r0, r2, r0, lsr r1
334 ; ARM-NEXT: bx lr
335 ;
336 ; THUMB6-LABEL: scalar_i32_lowestbit_eq:
337 ; THUMB6: @ %bb.0:
338 ; THUMB6-NEXT: lsrs r0, r1
339 ; THUMB6-NEXT: movs r1, #1
340 ; THUMB6-NEXT: ands r1, r0
341 ; THUMB6-NEXT: rsbs r0, r1, #0
342 ; THUMB6-NEXT: adcs r0, r1
343 ; THUMB6-NEXT: bx lr
344 ;
345 ; THUMB78-LABEL: scalar_i32_lowestbit_eq:
346 ; THUMB78: @ %bb.0:
347 ; THUMB78-NEXT: lsrs r0, r1
348 ; THUMB78-NEXT: movs r1, #1
349 ; THUMB78-NEXT: bic.w r0, r1, r0
350 ; THUMB78-NEXT: bx lr
351 %t0 = shl i32 1, %y
352 %t1 = and i32 %t0, %x
353 %res = icmp eq i32 %t1, 0
354 ret i1 %res
355 }
357 define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind {
358 ; ARM6-LABEL: scalar_i32_bitsinmiddle_eq:
359 ; ARM6: @ %bb.0:
360 ; ARM6-NEXT: mov r2, #65280
361 ; ARM6-NEXT: orr r2, r2, #16711680
362 ; ARM6-NEXT: and r0, r2, r0, lsr r1
363 ; ARM6-NEXT: clz r0, r0
364 ; ARM6-NEXT: lsr r0, r0, #5
365 ; ARM6-NEXT: bx lr
366 ;
367 ; ARM78-LABEL: scalar_i32_bitsinmiddle_eq:
368 ; ARM78: @ %bb.0:
369 ; ARM78-NEXT: movw r2, #65280
370 ; ARM78-NEXT: movt r2, #255
371 ; ARM78-NEXT: and r0, r2, r0, lsr r1
372 ; ARM78-NEXT: clz r0, r0
373 ; ARM78-NEXT: lsr r0, r0, #5
374 ; ARM78-NEXT: bx lr
375 ;
376 ; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq:
377 ; THUMB6: @ %bb.0:
378 ; THUMB6-NEXT: lsrs r0, r1
379 ; THUMB6-NEXT: ldr r1, .LCPI8_0
380 ; THUMB6-NEXT: ands r1, r0
381 ; THUMB6-NEXT: rsbs r0, r1, #0
382 ; THUMB6-NEXT: adcs r0, r1
383 ; THUMB6-NEXT: bx lr
384 ; THUMB6-NEXT: .p2align 2
385 ; THUMB6-NEXT: @ %bb.1:
386 ; THUMB6-NEXT: .LCPI8_0:
387 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
388 ;
389 ; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq:
390 ; THUMB78: @ %bb.0:
391 ; THUMB78-NEXT: lsrs r0, r1
392 ; THUMB78-NEXT: movw r1, #65280
393 ; THUMB78-NEXT: movt r1, #255
394 ; THUMB78-NEXT: ands r0, r1
395 ; THUMB78-NEXT: clz r0, r0
396 ; THUMB78-NEXT: lsrs r0, r0, #5
397 ; THUMB78-NEXT: bx lr
398 %t0 = shl i32 16776960, %y
399 %t1 = and i32 %t0, %x
400 %res = icmp eq i32 %t1, 0
401 ret i1 %res
402 }
404 ; i64 scalar
406 define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {
407 ; ARM6-LABEL: scalar_i64_signbit_eq:
408 ; ARM6: @ %bb.0:
409 ; ARM6-NEXT: lsr r0, r1, r2
410 ; ARM6-NEXT: subs r1, r2, #32
411 ; ARM6-NEXT: movpl r0, #0
412 ; ARM6-NEXT: mvn r0, r0
413 ; ARM6-NEXT: lsr r0, r0, #31
414 ; ARM6-NEXT: bx lr
415 ;
416 ; ARM78-LABEL: scalar_i64_signbit_eq:
417 ; ARM78: @ %bb.0:
418 ; ARM78-NEXT: lsr r0, r1, r2
419 ; ARM78-NEXT: subs r1, r2, #32
420 ; ARM78-NEXT: movwpl r0, #0
421 ; ARM78-NEXT: mvn r0, r0
422 ; ARM78-NEXT: lsr r0, r0, #31
423 ; ARM78-NEXT: bx lr
424 ;
425 ; THUMB6-LABEL: scalar_i64_signbit_eq:
426 ; THUMB6: @ %bb.0:
427 ; THUMB6-NEXT: push {r7, lr}
428 ; THUMB6-NEXT: bl __lshrdi3
429 ; THUMB6-NEXT: movs r0, #1
430 ; THUMB6-NEXT: lsls r2, r0, #31
431 ; THUMB6-NEXT: ands r2, r1
432 ; THUMB6-NEXT: rsbs r0, r2, #0
433 ; THUMB6-NEXT: adcs r0, r2
434 ; THUMB6-NEXT: pop {r7, pc}
435 ;
436 ; THUMB78-LABEL: scalar_i64_signbit_eq:
437 ; THUMB78: @ %bb.0:
438 ; THUMB78-NEXT: lsr.w r0, r1, r2
439 ; THUMB78-NEXT: subs.w r1, r2, #32
440 ; THUMB78-NEXT: it pl
441 ; THUMB78-NEXT: movpl r0, #0
442 ; THUMB78-NEXT: mvns r0, r0
443 ; THUMB78-NEXT: lsrs r0, r0, #31
444 ; THUMB78-NEXT: bx lr
445 %t0 = shl i64 9223372036854775808, %y
446 %t1 = and i64 %t0, %x
447 %res = icmp eq i64 %t1, 0
448 ret i1 %res
449 }
451 define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {
452 ; ARM-LABEL: scalar_i64_lowestbit_eq:
453 ; ARM: @ %bb.0:
454 ; ARM-NEXT: rsb r3, r2, #32
455 ; ARM-NEXT: lsr r0, r0, r2
456 ; ARM-NEXT: subs r2, r2, #32
457 ; ARM-NEXT: orr r0, r0, r1, lsl r3
458 ; ARM-NEXT: lsrpl r0, r1, r2
459 ; ARM-NEXT: mov r1, #1
460 ; ARM-NEXT: bic r0, r1, r0
461 ; ARM-NEXT: bx lr
462 ;
463 ; THUMB6-LABEL: scalar_i64_lowestbit_eq:
464 ; THUMB6: @ %bb.0:
465 ; THUMB6-NEXT: push {r7, lr}
466 ; THUMB6-NEXT: bl __lshrdi3
467 ; THUMB6-NEXT: movs r1, #1
468 ; THUMB6-NEXT: ands r1, r0
469 ; THUMB6-NEXT: rsbs r0, r1, #0
470 ; THUMB6-NEXT: adcs r0, r1
471 ; THUMB6-NEXT: pop {r7, pc}
472 ;
473 ; THUMB7-LABEL: scalar_i64_lowestbit_eq:
474 ; THUMB7: @ %bb.0:
475 ; THUMB7-NEXT: rsb.w r3, r2, #32
476 ; THUMB7-NEXT: lsrs r0, r2
477 ; THUMB7-NEXT: subs r2, #32
478 ; THUMB7-NEXT: lsl.w r3, r1, r3
479 ; THUMB7-NEXT: orr.w r0, r0, r3
480 ; THUMB7-NEXT: it pl
481 ; THUMB7-NEXT: lsrpl.w r0, r1, r2
482 ; THUMB7-NEXT: movs r1, #1
483 ; THUMB7-NEXT: bic.w r0, r1, r0
484 ; THUMB7-NEXT: bx lr
485 ;
486 ; THUMB8-LABEL: scalar_i64_lowestbit_eq:
487 ; THUMB8: @ %bb.0:
488 ; THUMB8-NEXT: rsb.w r3, r2, #32
489 ; THUMB8-NEXT: lsrs r0, r2
490 ; THUMB8-NEXT: lsl.w r3, r1, r3
491 ; THUMB8-NEXT: orrs r0, r3
492 ; THUMB8-NEXT: subs r2, #32
493 ; THUMB8-NEXT: lsr.w r1, r1, r2
494 ; THUMB8-NEXT: it mi
495 ; THUMB8-NEXT: movmi r1, r0
496 ; THUMB8-NEXT: movs r0, #1
497 ; THUMB8-NEXT: bics r0, r1
498 ; THUMB8-NEXT: bx lr
499 %t0 = shl i64 1, %y
500 %t1 = and i64 %t0, %x
501 %res = icmp eq i64 %t1, 0
502 ret i1 %res
503 }
505 define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {
506 ; ARM6-LABEL: scalar_i64_bitsinmiddle_eq:
507 ; ARM6: @ %bb.0:
508 ; ARM6-NEXT: rsb r3, r2, #32
509 ; ARM6-NEXT: lsr r0, r0, r2
510 ; ARM6-NEXT: orr r0, r0, r1, lsl r3
511 ; ARM6-NEXT: subs r3, r2, #32
512 ; ARM6-NEXT: lsrpl r0, r1, r3
513 ; ARM6-NEXT: lsr r1, r1, r2
514 ; ARM6-NEXT: movpl r1, #0
515 ; ARM6-NEXT: pkhbt r0, r1, r0
516 ; ARM6-NEXT: clz r0, r0
517 ; ARM6-NEXT: lsr r0, r0, #5
518 ; ARM6-NEXT: bx lr
519 ;
520 ; ARM78-LABEL: scalar_i64_bitsinmiddle_eq:
521 ; ARM78: @ %bb.0:
522 ; ARM78-NEXT: rsb r3, r2, #32
523 ; ARM78-NEXT: lsr r0, r0, r2
524 ; ARM78-NEXT: orr r0, r0, r1, lsl r3
525 ; ARM78-NEXT: subs r3, r2, #32
526 ; ARM78-NEXT: lsrpl r0, r1, r3
527 ; ARM78-NEXT: lsr r1, r1, r2
528 ; ARM78-NEXT: movwpl r1, #0
529 ; ARM78-NEXT: pkhbt r0, r1, r0
530 ; ARM78-NEXT: clz r0, r0
531 ; ARM78-NEXT: lsr r0, r0, #5
532 ; ARM78-NEXT: bx lr
533 ;
534 ; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq:
535 ; THUMB6: @ %bb.0:
536 ; THUMB6-NEXT: push {r7, lr}
537 ; THUMB6-NEXT: bl __lshrdi3
538 ; THUMB6-NEXT: ldr r2, .LCPI11_0
539 ; THUMB6-NEXT: ands r2, r0
540 ; THUMB6-NEXT: uxth r0, r1
541 ; THUMB6-NEXT: adds r1, r2, r0
542 ; THUMB6-NEXT: rsbs r0, r1, #0
543 ; THUMB6-NEXT: adcs r0, r1
544 ; THUMB6-NEXT: pop {r7, pc}
545 ; THUMB6-NEXT: .p2align 2
546 ; THUMB6-NEXT: @ %bb.1:
547 ; THUMB6-NEXT: .LCPI11_0:
548 ; THUMB6-NEXT: .long 4294901760 @ 0xffff0000
549 ;
550 ; THUMB7-LABEL: scalar_i64_bitsinmiddle_eq:
551 ; THUMB7: @ %bb.0:
552 ; THUMB7-NEXT: rsb.w r3, r2, #32
553 ; THUMB7-NEXT: lsrs r0, r2
554 ; THUMB7-NEXT: lsl.w r3, r1, r3
555 ; THUMB7-NEXT: orrs r0, r3
556 ; THUMB7-NEXT: subs.w r3, r2, #32
557 ; THUMB7-NEXT: it pl
558 ; THUMB7-NEXT: lsrpl.w r0, r1, r3
559 ; THUMB7-NEXT: lsr.w r1, r1, r2
560 ; THUMB7-NEXT: it pl
561 ; THUMB7-NEXT: movpl r1, #0
562 ; THUMB7-NEXT: pkhbt r0, r1, r0
563 ; THUMB7-NEXT: clz r0, r0
564 ; THUMB7-NEXT: lsrs r0, r0, #5
565 ; THUMB7-NEXT: bx lr
566 ;
567 ; THUMB8-LABEL: scalar_i64_bitsinmiddle_eq:
568 ; THUMB8: @ %bb.0:
569 ; THUMB8-NEXT: rsb.w r3, r2, #32
570 ; THUMB8-NEXT: lsrs r0, r2
571 ; THUMB8-NEXT: lsl.w r3, r1, r3
572 ; THUMB8-NEXT: orrs r0, r3
573 ; THUMB8-NEXT: subs.w r3, r2, #32
574 ; THUMB8-NEXT: lsr.w r3, r1, r3
575 ; THUMB8-NEXT: it mi
576 ; THUMB8-NEXT: movmi r3, r0
577 ; THUMB8-NEXT: lsr.w r0, r1, r2
578 ; THUMB8-NEXT: it pl
579 ; THUMB8-NEXT: movpl r0, #0
580 ; THUMB8-NEXT: pkhbt r0, r0, r3
581 ; THUMB8-NEXT: clz r0, r0
582 ; THUMB8-NEXT: lsrs r0, r0, #5
583 ; THUMB8-NEXT: bx lr
584 %t0 = shl i64 281474976645120, %y
585 %t1 = and i64 %t0, %x
586 %res = icmp eq i64 %t1, 0
587 ret i1 %res
588 }
590 ;------------------------------------------------------------------------------;
591 ; A few trivial vector tests
592 ;------------------------------------------------------------------------------;
594 define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
595 ; ARM6-LABEL: vec_4xi32_splat_eq:
596 ; ARM6: @ %bb.0:
597 ; ARM6-NEXT: push {r11, lr}
598 ; ARM6-NEXT: ldr r12, [sp, #8]
599 ; ARM6-NEXT: mov lr, #1
600 ; ARM6-NEXT: bic r0, lr, r0, lsr r12
601 ; ARM6-NEXT: ldr r12, [sp, #12]
602 ; ARM6-NEXT: bic r1, lr, r1, lsr r12
603 ; ARM6-NEXT: ldr r12, [sp, #16]
604 ; ARM6-NEXT: bic r2, lr, r2, lsr r12
605 ; ARM6-NEXT: ldr r12, [sp, #20]
606 ; ARM6-NEXT: bic r3, lr, r3, lsr r12
607 ; ARM6-NEXT: pop {r11, pc}
608 ;
609 ; ARM78-LABEL: vec_4xi32_splat_eq:
610 ; ARM78: @ %bb.0:
611 ; ARM78-NEXT: mov r12, sp
612 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
613 ; ARM78-NEXT: vmov d19, r2, r3
614 ; ARM78-NEXT: vneg.s32 q8, q8
615 ; ARM78-NEXT: vmov d18, r0, r1
616 ; ARM78-NEXT: vmov.i32 q10, #0x1
617 ; ARM78-NEXT: vshl.u32 q8, q9, q8
618 ; ARM78-NEXT: vtst.32 q8, q8, q10
619 ; ARM78-NEXT: vmvn q8, q8
620 ; ARM78-NEXT: vmovn.i32 d16, q8
621 ; ARM78-NEXT: vmov r0, r1, d16
622 ; ARM78-NEXT: bx lr
623 ;
624 ; THUMB6-LABEL: vec_4xi32_splat_eq:
625 ; THUMB6: @ %bb.0:
626 ; THUMB6-NEXT: push {r4, r5, r7, lr}
627 ; THUMB6-NEXT: ldr r4, [sp, #16]
628 ; THUMB6-NEXT: lsrs r0, r4
629 ; THUMB6-NEXT: movs r4, #1
630 ; THUMB6-NEXT: ands r0, r4
631 ; THUMB6-NEXT: rsbs r5, r0, #0
632 ; THUMB6-NEXT: adcs r0, r5
633 ; THUMB6-NEXT: ldr r5, [sp, #20]
634 ; THUMB6-NEXT: lsrs r1, r5
635 ; THUMB6-NEXT: ands r1, r4
636 ; THUMB6-NEXT: rsbs r5, r1, #0
637 ; THUMB6-NEXT: adcs r1, r5
638 ; THUMB6-NEXT: ldr r5, [sp, #24]
639 ; THUMB6-NEXT: lsrs r2, r5
640 ; THUMB6-NEXT: ands r2, r4
641 ; THUMB6-NEXT: rsbs r5, r2, #0
642 ; THUMB6-NEXT: adcs r2, r5
643 ; THUMB6-NEXT: ldr r5, [sp, #28]
644 ; THUMB6-NEXT: lsrs r3, r5
645 ; THUMB6-NEXT: ands r3, r4
646 ; THUMB6-NEXT: rsbs r4, r3, #0
647 ; THUMB6-NEXT: adcs r3, r4
648 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
649 ;
650 ; THUMB78-LABEL: vec_4xi32_splat_eq:
651 ; THUMB78: @ %bb.0:
652 ; THUMB78-NEXT: mov r12, sp
653 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
654 ; THUMB78-NEXT: vmov d19, r2, r3
655 ; THUMB78-NEXT: vneg.s32 q8, q8
656 ; THUMB78-NEXT: vmov d18, r0, r1
657 ; THUMB78-NEXT: vmov.i32 q10, #0x1
658 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
659 ; THUMB78-NEXT: vtst.32 q8, q8, q10
660 ; THUMB78-NEXT: vmvn q8, q8
661 ; THUMB78-NEXT: vmovn.i32 d16, q8
662 ; THUMB78-NEXT: vmov r0, r1, d16
663 ; THUMB78-NEXT: bx lr
664 %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
665 %t1 = and <4 x i32> %t0, %x
666 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
667 ret <4 x i1> %res
668 }
670 define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
671 ; ARM6-LABEL: vec_4xi32_nonsplat_eq:
672 ; ARM6: @ %bb.0:
673 ; ARM6-NEXT: ldr r12, [sp, #4]
674 ; ARM6-NEXT: mov r0, #1
675 ; ARM6-NEXT: bic r1, r0, r1, lsr r12
676 ; ARM6-NEXT: ldr r12, [sp, #8]
677 ; ARM6-NEXT: mov r0, #65280
678 ; ARM6-NEXT: orr r0, r0, #16711680
679 ; ARM6-NEXT: and r0, r0, r2, lsr r12
680 ; ARM6-NEXT: clz r0, r0
681 ; ARM6-NEXT: lsr r2, r0, #5
682 ; ARM6-NEXT: ldr r0, [sp, #12]
683 ; ARM6-NEXT: mvn r0, r3, lsr r0
684 ; ARM6-NEXT: lsr r3, r0, #31
685 ; ARM6-NEXT: mov r0, #1
686 ; ARM6-NEXT: bx lr
687 ;
688 ; ARM78-LABEL: vec_4xi32_nonsplat_eq:
689 ; ARM78: @ %bb.0:
690 ; ARM78-NEXT: mov r12, sp
691 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
692 ; ARM78-NEXT: adr r12, .LCPI13_0
693 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12:128]
694 ; ARM78-NEXT: vshl.u32 q8, q9, q8
695 ; ARM78-NEXT: vmov d19, r2, r3
696 ; ARM78-NEXT: vmov d18, r0, r1
697 ; ARM78-NEXT: vtst.32 q8, q8, q9
698 ; ARM78-NEXT: vmvn q8, q8
699 ; ARM78-NEXT: vmovn.i32 d16, q8
700 ; ARM78-NEXT: vmov r0, r1, d16
701 ; ARM78-NEXT: bx lr
702 ; ARM78-NEXT: .p2align 4
703 ; ARM78-NEXT: @ %bb.1:
704 ; ARM78-NEXT: .LCPI13_0:
705 ; ARM78-NEXT: .long 0 @ 0x0
706 ; ARM78-NEXT: .long 1 @ 0x1
707 ; ARM78-NEXT: .long 16776960 @ 0xffff00
708 ; ARM78-NEXT: .long 2147483648 @ 0x80000000
709 ;
710 ; THUMB6-LABEL: vec_4xi32_nonsplat_eq:
711 ; THUMB6: @ %bb.0:
712 ; THUMB6-NEXT: push {r4, lr}
713 ; THUMB6-NEXT: ldr r0, [sp, #12]
714 ; THUMB6-NEXT: lsrs r1, r0
715 ; THUMB6-NEXT: movs r0, #1
716 ; THUMB6-NEXT: ands r1, r0
717 ; THUMB6-NEXT: rsbs r4, r1, #0
718 ; THUMB6-NEXT: adcs r1, r4
719 ; THUMB6-NEXT: ldr r4, [sp, #16]
720 ; THUMB6-NEXT: lsrs r2, r4
721 ; THUMB6-NEXT: ldr r4, .LCPI13_0
722 ; THUMB6-NEXT: ands r4, r2
723 ; THUMB6-NEXT: rsbs r2, r4, #0
724 ; THUMB6-NEXT: adcs r2, r4
725 ; THUMB6-NEXT: ldr r4, [sp, #20]
726 ; THUMB6-NEXT: lsrs r3, r4
727 ; THUMB6-NEXT: lsls r4, r0, #31
728 ; THUMB6-NEXT: ands r4, r3
729 ; THUMB6-NEXT: rsbs r3, r4, #0
730 ; THUMB6-NEXT: adcs r3, r4
731 ; THUMB6-NEXT: pop {r4, pc}
732 ; THUMB6-NEXT: .p2align 2
733 ; THUMB6-NEXT: @ %bb.1:
734 ; THUMB6-NEXT: .LCPI13_0:
735 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
736 ;
737 ; THUMB78-LABEL: vec_4xi32_nonsplat_eq:
738 ; THUMB78: @ %bb.0:
739 ; THUMB78-NEXT: mov r12, sp
740 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
741 ; THUMB78-NEXT: adr.w r12, .LCPI13_0
742 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12:128]
743 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
744 ; THUMB78-NEXT: vmov d19, r2, r3
745 ; THUMB78-NEXT: vmov d18, r0, r1
746 ; THUMB78-NEXT: vtst.32 q8, q8, q9
747 ; THUMB78-NEXT: vmvn q8, q8
748 ; THUMB78-NEXT: vmovn.i32 d16, q8
749 ; THUMB78-NEXT: vmov r0, r1, d16
750 ; THUMB78-NEXT: bx lr
751 ; THUMB78-NEXT: .p2align 4
752 ; THUMB78-NEXT: @ %bb.1:
753 ; THUMB78-NEXT: .LCPI13_0:
754 ; THUMB78-NEXT: .long 0 @ 0x0
755 ; THUMB78-NEXT: .long 1 @ 0x1
756 ; THUMB78-NEXT: .long 16776960 @ 0xffff00
757 ; THUMB78-NEXT: .long 2147483648 @ 0x80000000
758 %t0 = shl <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y
759 %t1 = and <4 x i32> %t0, %x
760 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
761 ret <4 x i1> %res
762 }
764 define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
765 ; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq:
766 ; ARM6: @ %bb.0:
767 ; ARM6-NEXT: push {r11, lr}
768 ; ARM6-NEXT: ldr r2, [sp, #12]
769 ; ARM6-NEXT: mov lr, #1
770 ; ARM6-NEXT: ldr r12, [sp, #8]
771 ; ARM6-NEXT: bic r1, lr, r1, lsr r2
772 ; ARM6-NEXT: ldr r2, [sp, #20]
773 ; ARM6-NEXT: bic r0, lr, r0, lsr r12
774 ; ARM6-NEXT: bic r3, lr, r3, lsr r2
775 ; ARM6-NEXT: mov r2, #1
776 ; ARM6-NEXT: pop {r11, pc}
777 ;
778 ; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq:
779 ; ARM78: @ %bb.0:
780 ; ARM78-NEXT: mov r12, sp
781 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
782 ; ARM78-NEXT: vmov d19, r2, r3
783 ; ARM78-NEXT: vneg.s32 q8, q8
784 ; ARM78-NEXT: vmov d18, r0, r1
785 ; ARM78-NEXT: vmov.i32 q10, #0x1
786 ; ARM78-NEXT: vshl.u32 q8, q9, q8
787 ; ARM78-NEXT: vtst.32 q8, q8, q10
788 ; ARM78-NEXT: vmvn q8, q8
789 ; ARM78-NEXT: vmovn.i32 d16, q8
790 ; ARM78-NEXT: vmov r0, r1, d16
791 ; ARM78-NEXT: bx lr
792 ;
793 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef0_eq:
794 ; THUMB6: @ %bb.0:
795 ; THUMB6-NEXT: push {r4, lr}
796 ; THUMB6-NEXT: ldr r2, [sp, #8]
797 ; THUMB6-NEXT: lsrs r0, r2
798 ; THUMB6-NEXT: movs r2, #1
799 ; THUMB6-NEXT: ands r0, r2
800 ; THUMB6-NEXT: rsbs r4, r0, #0
801 ; THUMB6-NEXT: adcs r0, r4
802 ; THUMB6-NEXT: ldr r4, [sp, #12]
803 ; THUMB6-NEXT: lsrs r1, r4
804 ; THUMB6-NEXT: ands r1, r2
805 ; THUMB6-NEXT: rsbs r4, r1, #0
806 ; THUMB6-NEXT: adcs r1, r4
807 ; THUMB6-NEXT: ldr r4, [sp, #20]
808 ; THUMB6-NEXT: lsrs r3, r4
809 ; THUMB6-NEXT: ands r3, r2
810 ; THUMB6-NEXT: rsbs r4, r3, #0
811 ; THUMB6-NEXT: adcs r3, r4
812 ; THUMB6-NEXT: pop {r4, pc}
813 ;
814 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef0_eq:
815 ; THUMB78: @ %bb.0:
816 ; THUMB78-NEXT: mov r12, sp
817 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
818 ; THUMB78-NEXT: vmov d19, r2, r3
819 ; THUMB78-NEXT: vneg.s32 q8, q8
820 ; THUMB78-NEXT: vmov d18, r0, r1
821 ; THUMB78-NEXT: vmov.i32 q10, #0x1
822 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
823 ; THUMB78-NEXT: vtst.32 q8, q8, q10
824 ; THUMB78-NEXT: vmvn q8, q8
825 ; THUMB78-NEXT: vmovn.i32 d16, q8
826 ; THUMB78-NEXT: vmov r0, r1, d16
827 ; THUMB78-NEXT: bx lr
828 %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
829 %t1 = and <4 x i32> %t0, %x
830 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
831 ret <4 x i1> %res
832 }
833 define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
834 ; ARM6-LABEL: vec_4xi32_nonsplat_undef1_eq:
835 ; ARM6: @ %bb.0:
836 ; ARM6-NEXT: push {r11, lr}
837 ; ARM6-NEXT: ldr r2, [sp, #12]
838 ; ARM6-NEXT: mov lr, #1
839 ; ARM6-NEXT: ldr r12, [sp, #8]
840 ; ARM6-NEXT: bic r1, lr, r1, lsr r2
841 ; ARM6-NEXT: ldr r2, [sp, #20]
842 ; ARM6-NEXT: bic r0, lr, r0, lsr r12
843 ; ARM6-NEXT: bic r3, lr, r3, lsr r2
844 ; ARM6-NEXT: pop {r11, pc}
845 ;
846 ; ARM78-LABEL: vec_4xi32_nonsplat_undef1_eq:
847 ; ARM78: @ %bb.0:
848 ; ARM78-NEXT: vmov.i32 q8, #0x1
849 ; ARM78-NEXT: mov r12, sp
850 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12]
851 ; ARM78-NEXT: vshl.u32 q8, q8, q9
852 ; ARM78-NEXT: vmov d19, r2, r3
853 ; ARM78-NEXT: vmov d18, r0, r1
854 ; ARM78-NEXT: vtst.32 q8, q8, q9
855 ; ARM78-NEXT: vmvn q8, q8
856 ; ARM78-NEXT: vmovn.i32 d16, q8
857 ; ARM78-NEXT: vmov r0, r1, d16
858 ; ARM78-NEXT: bx lr
859 ;
860 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef1_eq:
861 ; THUMB6: @ %bb.0:
862 ; THUMB6-NEXT: push {r4, lr}
863 ; THUMB6-NEXT: ldr r2, [sp, #8]
864 ; THUMB6-NEXT: lsrs r0, r2
865 ; THUMB6-NEXT: movs r2, #1
866 ; THUMB6-NEXT: ands r0, r2
867 ; THUMB6-NEXT: rsbs r4, r0, #0
868 ; THUMB6-NEXT: adcs r0, r4
869 ; THUMB6-NEXT: ldr r4, [sp, #12]
870 ; THUMB6-NEXT: lsrs r1, r4
871 ; THUMB6-NEXT: ands r1, r2
872 ; THUMB6-NEXT: rsbs r4, r1, #0
873 ; THUMB6-NEXT: adcs r1, r4
874 ; THUMB6-NEXT: ldr r4, [sp, #20]
875 ; THUMB6-NEXT: lsrs r3, r4
876 ; THUMB6-NEXT: ands r3, r2
877 ; THUMB6-NEXT: rsbs r2, r3, #0
878 ; THUMB6-NEXT: adcs r3, r2
879 ; THUMB6-NEXT: pop {r4, pc}
880 ;
881 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef1_eq:
882 ; THUMB78: @ %bb.0:
883 ; THUMB78-NEXT: vmov.i32 q8, #0x1
884 ; THUMB78-NEXT: mov r12, sp
885 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]
886 ; THUMB78-NEXT: vshl.u32 q8, q8, q9
887 ; THUMB78-NEXT: vmov d19, r2, r3
888 ; THUMB78-NEXT: vmov d18, r0, r1
889 ; THUMB78-NEXT: vtst.32 q8, q8, q9
890 ; THUMB78-NEXT: vmvn q8, q8
891 ; THUMB78-NEXT: vmovn.i32 d16, q8
892 ; THUMB78-NEXT: vmov r0, r1, d16
893 ; THUMB78-NEXT: bx lr
894 %t0 = shl <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
895 %t1 = and <4 x i32> %t0, %x
896 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
897 ret <4 x i1> %res
898 }
899 define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
900 ; ARM6-LABEL: vec_4xi32_nonsplat_undef2_eq:
901 ; ARM6: @ %bb.0:
902 ; ARM6-NEXT: push {r11, lr}
903 ; ARM6-NEXT: ldr r2, [sp, #12]
904 ; ARM6-NEXT: mov lr, #1
905 ; ARM6-NEXT: ldr r12, [sp, #8]
906 ; ARM6-NEXT: bic r1, lr, r1, lsr r2
907 ; ARM6-NEXT: ldr r2, [sp, #20]
908 ; ARM6-NEXT: bic r0, lr, r0, lsr r12
909 ; ARM6-NEXT: bic r3, lr, r3, lsr r2
910 ; ARM6-NEXT: pop {r11, pc}
911 ;
912 ; ARM78-LABEL: vec_4xi32_nonsplat_undef2_eq:
913 ; ARM78: @ %bb.0:
914 ; ARM78-NEXT: vmov.i32 q8, #0x1
915 ; ARM78-NEXT: mov r12, sp
916 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12]
917 ; ARM78-NEXT: vshl.u32 q8, q8, q9
918 ; ARM78-NEXT: vmov d19, r2, r3
919 ; ARM78-NEXT: vmov d18, r0, r1
920 ; ARM78-NEXT: vtst.32 q8, q8, q9
921 ; ARM78-NEXT: vmvn q8, q8
922 ; ARM78-NEXT: vmovn.i32 d16, q8
923 ; ARM78-NEXT: vmov r0, r1, d16
924 ; ARM78-NEXT: bx lr
925 ;
926 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef2_eq:
927 ; THUMB6: @ %bb.0:
928 ; THUMB6-NEXT: push {r4, lr}
929 ; THUMB6-NEXT: ldr r2, [sp, #8]
930 ; THUMB6-NEXT: lsrs r0, r2
931 ; THUMB6-NEXT: movs r2, #1
932 ; THUMB6-NEXT: ands r0, r2
933 ; THUMB6-NEXT: rsbs r4, r0, #0
934 ; THUMB6-NEXT: adcs r0, r4
935 ; THUMB6-NEXT: ldr r4, [sp, #12]
936 ; THUMB6-NEXT: lsrs r1, r4
937 ; THUMB6-NEXT: ands r1, r2
938 ; THUMB6-NEXT: rsbs r4, r1, #0
939 ; THUMB6-NEXT: adcs r1, r4
940 ; THUMB6-NEXT: ldr r4, [sp, #20]
941 ; THUMB6-NEXT: lsrs r3, r4
942 ; THUMB6-NEXT: ands r3, r2
943 ; THUMB6-NEXT: rsbs r2, r3, #0
944 ; THUMB6-NEXT: adcs r3, r2
945 ; THUMB6-NEXT: pop {r4, pc}
946 ;
947 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef2_eq:
948 ; THUMB78: @ %bb.0:
949 ; THUMB78-NEXT: vmov.i32 q8, #0x1
950 ; THUMB78-NEXT: mov r12, sp
951 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12]
952 ; THUMB78-NEXT: vshl.u32 q8, q8, q9
953 ; THUMB78-NEXT: vmov d19, r2, r3
954 ; THUMB78-NEXT: vmov d18, r0, r1
955 ; THUMB78-NEXT: vtst.32 q8, q8, q9
956 ; THUMB78-NEXT: vmvn q8, q8
957 ; THUMB78-NEXT: vmovn.i32 d16, q8
958 ; THUMB78-NEXT: vmov r0, r1, d16
959 ; THUMB78-NEXT: bx lr
960 %t0 = shl <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
961 %t1 = and <4 x i32> %t0, %x
962 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
963 ret <4 x i1> %res
964 }
966 ;------------------------------------------------------------------------------;
967 ; A special tests
968 ;------------------------------------------------------------------------------;
970 define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
971 ; ARM-LABEL: scalar_i8_signbit_ne:
972 ; ARM: @ %bb.0:
973 ; ARM-NEXT: uxtb r1, r1
974 ; ARM-NEXT: uxtb r0, r0
975 ; ARM-NEXT: lsr r0, r0, r1
976 ; ARM-NEXT: uxtb r0, r0
977 ; ARM-NEXT: lsr r0, r0, #7
978 ; ARM-NEXT: bx lr
979 ;
980 ; THUMB6-LABEL: scalar_i8_signbit_ne:
981 ; THUMB6: @ %bb.0:
982 ; THUMB6-NEXT: uxtb r1, r1
983 ; THUMB6-NEXT: uxtb r0, r0
984 ; THUMB6-NEXT: lsrs r0, r1
985 ; THUMB6-NEXT: uxtb r0, r0
986 ; THUMB6-NEXT: lsrs r0, r0, #7
987 ; THUMB6-NEXT: bx lr
988 ;
989 ; THUMB7-LABEL: scalar_i8_signbit_ne:
990 ; THUMB7: @ %bb.0:
991 ; THUMB7-NEXT: uxtb r1, r1
992 ; THUMB7-NEXT: uxtb r0, r0
993 ; THUMB7-NEXT: lsrs r0, r1
994 ; THUMB7-NEXT: uxtb r0, r0
995 ; THUMB7-NEXT: lsrs r0, r0, #7
996 ; THUMB7-NEXT: bx lr
997 ;
998 ; THUMB8-LABEL: scalar_i8_signbit_ne:
999 ; THUMB8: @ %bb.0:
1000 ; THUMB8-NEXT: uxtb r0, r0
1001 ; THUMB8-NEXT: uxtb r1, r1
1002 ; THUMB8-NEXT: lsrs r0, r1
1003 ; THUMB8-NEXT: uxtb r0, r0
1004 ; THUMB8-NEXT: lsrs r0, r0, #7
1005 ; THUMB8-NEXT: bx lr
1006 %t0 = shl i8 128, %y
1007 %t1 = and i8 %t0, %x
1008 %res = icmp ne i8 %t1, 0 ; we are perfectly happy with 'ne' predicate
1009 ret i1 %res
1010 }
1012 ;------------------------------------------------------------------------------;
1013 ; What if X is a constant too?
1014 ;------------------------------------------------------------------------------;
1016 define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
1017 ; ARM6-LABEL: scalar_i32_x_is_const_eq:
1018 ; ARM6: @ %bb.0:
1019 ; ARM6-NEXT: ldr r1, .LCPI18_0
1020 ; ARM6-NEXT: mov r2, #1
1021 ; ARM6-NEXT: bic r0, r2, r1, lsl r0
1022 ; ARM6-NEXT: bx lr
1023 ; ARM6-NEXT: .p2align 2
1024 ; ARM6-NEXT: @ %bb.1:
1025 ; ARM6-NEXT: .LCPI18_0:
1026 ; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
1027 ;
1028 ; ARM78-LABEL: scalar_i32_x_is_const_eq:
1029 ; ARM78: @ %bb.0:
1030 ; ARM78-NEXT: movw r1, #43605
1031 ; ARM78-NEXT: mov r2, #1
1032 ; ARM78-NEXT: movt r1, #43605
1033 ; ARM78-NEXT: bic r0, r2, r1, lsl r0
1034 ; ARM78-NEXT: bx lr
1035 ;
1036 ; THUMB6-LABEL: scalar_i32_x_is_const_eq:
1037 ; THUMB6: @ %bb.0:
1038 ; THUMB6-NEXT: ldr r1, .LCPI18_0
1039 ; THUMB6-NEXT: lsls r1, r0
1040 ; THUMB6-NEXT: movs r2, #1
1041 ; THUMB6-NEXT: ands r2, r1
1042 ; THUMB6-NEXT: rsbs r0, r2, #0
1043 ; THUMB6-NEXT: adcs r0, r2
1044 ; THUMB6-NEXT: bx lr
1045 ; THUMB6-NEXT: .p2align 2
1046 ; THUMB6-NEXT: @ %bb.1:
1047 ; THUMB6-NEXT: .LCPI18_0:
1048 ; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
1049 ;
1050 ; THUMB78-LABEL: scalar_i32_x_is_const_eq:
1051 ; THUMB78: @ %bb.0:
1052 ; THUMB78-NEXT: movw r1, #43605
1053 ; THUMB78-NEXT: movt r1, #43605
1054 ; THUMB78-NEXT: lsl.w r0, r1, r0
1055 ; THUMB78-NEXT: movs r1, #1
1056 ; THUMB78-NEXT: bic.w r0, r1, r0
1057 ; THUMB78-NEXT: bx lr
1058 %t0 = shl i32 2857740885, %y
1059 %t1 = and i32 %t0, 1
1060 %res = icmp eq i32 %t1, 0
1061 ret i1 %res
1062 }
1063 define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
1064 ; ARM6-LABEL: scalar_i32_x_is_const2_eq:
1065 ; ARM6: @ %bb.0:
1066 ; ARM6-NEXT: ldr r2, .LCPI19_0
1067 ; ARM6-NEXT: mov r1, #1
1068 ; ARM6-NEXT: and r0, r2, r1, lsl r0
1069 ; ARM6-NEXT: clz r0, r0
1070 ; ARM6-NEXT: lsr r0, r0, #5
1071 ; ARM6-NEXT: bx lr
1072 ; ARM6-NEXT: .p2align 2
1073 ; ARM6-NEXT: @ %bb.1:
1074 ; ARM6-NEXT: .LCPI19_0:
1075 ; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
1076 ;
1077 ; ARM78-LABEL: scalar_i32_x_is_const2_eq:
1078 ; ARM78: @ %bb.0:
1079 ; ARM78-NEXT: movw r1, #43605
1080 ; ARM78-NEXT: mov r2, #1
1081 ; ARM78-NEXT: movt r1, #43605
1082 ; ARM78-NEXT: and r0, r1, r2, lsl r0
1083 ; ARM78-NEXT: clz r0, r0
1084 ; ARM78-NEXT: lsr r0, r0, #5
1085 ; ARM78-NEXT: bx lr
1086 ;
1087 ; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
1088 ; THUMB6: @ %bb.0:
1089 ; THUMB6-NEXT: movs r1, #1
1090 ; THUMB6-NEXT: lsls r1, r0
1091 ; THUMB6-NEXT: ldr r2, .LCPI19_0
1092 ; THUMB6-NEXT: ands r2, r1
1093 ; THUMB6-NEXT: rsbs r0, r2, #0
1094 ; THUMB6-NEXT: adcs r0, r2
1095 ; THUMB6-NEXT: bx lr
1096 ; THUMB6-NEXT: .p2align 2
1097 ; THUMB6-NEXT: @ %bb.1:
1098 ; THUMB6-NEXT: .LCPI19_0:
1099 ; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
1100 ;
1101 ; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
1102 ; THUMB78: @ %bb.0:
1103 ; THUMB78-NEXT: movs r1, #1
1104 ; THUMB78-NEXT: lsl.w r0, r1, r0
1105 ; THUMB78-NEXT: movw r1, #43605
1106 ; THUMB78-NEXT: movt r1, #43605
1107 ; THUMB78-NEXT: ands r0, r1
1108 ; THUMB78-NEXT: clz r0, r0
1109 ; THUMB78-NEXT: lsrs r0, r0, #5
1110 ; THUMB78-NEXT: bx lr
1111 %t0 = shl i32 1, %y
1112 %t1 = and i32 %t0, 2857740885
1113 %res = icmp eq i32 %t1, 0
1114 ret i1 %res
1115 }
1117 ;------------------------------------------------------------------------------;
1118 ; A few negative tests
1119 ;------------------------------------------------------------------------------;
1121 define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
1122 ; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1123 ; ARM6: @ %bb.0:
1124 ; ARM6-NEXT: uxtb r1, r1
1125 ; ARM6-NEXT: mov r2, #24
1126 ; ARM6-NEXT: and r0, r0, r2, lsl r1
1127 ; ARM6-NEXT: sxtb r1, r0
1128 ; ARM6-NEXT: mov r0, #0
1129 ; ARM6-NEXT: cmp r1, #0
1130 ; ARM6-NEXT: movmi r0, #1
1131 ; ARM6-NEXT: bx lr
1132 ;
1133 ; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1134 ; ARM78: @ %bb.0:
1135 ; ARM78-NEXT: uxtb r1, r1
1136 ; ARM78-NEXT: mov r2, #24
1137 ; ARM78-NEXT: and r0, r0, r2, lsl r1
1138 ; ARM78-NEXT: sxtb r1, r0
1139 ; ARM78-NEXT: mov r0, #0
1140 ; ARM78-NEXT: cmp r1, #0
1141 ; ARM78-NEXT: movwmi r0, #1
1142 ; ARM78-NEXT: bx lr
1143 ;
1144 ; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1145 ; THUMB6: @ %bb.0:
1146 ; THUMB6-NEXT: uxtb r1, r1
1147 ; THUMB6-NEXT: movs r2, #24
1148 ; THUMB6-NEXT: lsls r2, r1
1149 ; THUMB6-NEXT: ands r2, r0
1150 ; THUMB6-NEXT: sxtb r0, r2
1151 ; THUMB6-NEXT: cmp r0, #0
1152 ; THUMB6-NEXT: bmi .LBB20_2
1153 ; THUMB6-NEXT: @ %bb.1:
1154 ; THUMB6-NEXT: movs r0, #0
1155 ; THUMB6-NEXT: bx lr
1156 ; THUMB6-NEXT: .LBB20_2:
1157 ; THUMB6-NEXT: movs r0, #1
1158 ; THUMB6-NEXT: bx lr
1159 ;
1160 ; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1161 ; THUMB78: @ %bb.0:
1162 ; THUMB78-NEXT: uxtb r1, r1
1163 ; THUMB78-NEXT: movs r2, #24
1164 ; THUMB78-NEXT: lsl.w r1, r2, r1
1165 ; THUMB78-NEXT: ands r0, r1
1166 ; THUMB78-NEXT: sxtb r1, r0
1167 ; THUMB78-NEXT: movs r0, #0
1168 ; THUMB78-NEXT: cmp r1, #0
1169 ; THUMB78-NEXT: it mi
1170 ; THUMB78-NEXT: movmi r0, #1
1171 ; THUMB78-NEXT: bx lr
1172 %t0 = shl i8 24, %y
1173 %t1 = and i8 %t0, %x
1174 %res = icmp slt i8 %t1, 0
1175 ret i1 %res
1176 }
1178 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
1179 ; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:
1180 ; ARM: @ %bb.0:
1181 ; ARM-NEXT: uxtb r1, r1
1182 ; ARM-NEXT: mvn r2, #127
1183 ; ARM-NEXT: and r0, r0, r2, lsl r1
1184 ; ARM-NEXT: mvn r1, #0
1185 ; ARM-NEXT: uxtab r0, r1, r0
1186 ; ARM-NEXT: clz r0, r0
1187 ; ARM-NEXT: lsr r0, r0, #5
1188 ; ARM-NEXT: bx lr
1189 ;
1190 ; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:
1191 ; THUMB6: @ %bb.0:
1192 ; THUMB6-NEXT: uxtb r1, r1
1193 ; THUMB6-NEXT: movs r2, #127
1194 ; THUMB6-NEXT: mvns r2, r2
1195 ; THUMB6-NEXT: lsls r2, r1
1196 ; THUMB6-NEXT: ands r2, r0
1197 ; THUMB6-NEXT: uxtb r0, r2
1198 ; THUMB6-NEXT: subs r1, r0, #1
1199 ; THUMB6-NEXT: rsbs r0, r1, #0
1200 ; THUMB6-NEXT: adcs r0, r1
1201 ; THUMB6-NEXT: bx lr
1202 ;
1203 ; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:
1204 ; THUMB78: @ %bb.0:
1205 ; THUMB78-NEXT: uxtb r1, r1
1206 ; THUMB78-NEXT: mvn r2, #127
1207 ; THUMB78-NEXT: lsl.w r1, r2, r1
1208 ; THUMB78-NEXT: ands r0, r1
1209 ; THUMB78-NEXT: mov.w r1, #-1
1210 ; THUMB78-NEXT: uxtab r0, r1, r0
1211 ; THUMB78-NEXT: clz r0, r0
1212 ; THUMB78-NEXT: lsrs r0, r0, #5
1213 ; THUMB78-NEXT: bx lr
1214 %t0 = shl i8 128, %y
1215 %t1 = and i8 %t0, %x
1216 %res = icmp eq i8 %t1, 1 ; should be comparing with 0
1217 ret i1 %res
1218 }