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[InstCombine] Signed saturation patterns
[llvm-core.git]
/
test
/
CodeGen
/
ARM
/
zext-logic-shift-load.ll
blob
ab6bc7d572aec179ba25452c69f8c7ab4ca01295
1
; RUN: llc -mtriple=armv7-linux-gnu < %s -o - | FileCheck %s
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define void @test1(i8* %p, i16* %q) {
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; CHECK: ldrb
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; CHECK-NEXT: mov
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; CHECK-NEXT: and
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; CHECK-NEXT: strh
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; CHECK-NEXT: bx
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%1 = load i8, i8* %p
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%2 = shl i8 %1, 2
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%3 = and i8 %2, 12
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%4 = zext i8 %3 to i16
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store i16 %4, i16* %q
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ret void
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}
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