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[InstCombine] Signed saturation patterns
[llvm-core.git] / test / CodeGen / MSP430 / flt_rounds.ll
blobfb89363d4d0a94c916984b204b816e8dcf86a001
1 ; RUN: llc -verify-machineinstrs < %s -march=msp430
2
3 define i16 @foo() {
4 entry:
5   %0 = call i32 @llvm.flt.rounds()
6   %1 = trunc i32 %0 to i16
7   ret i16 %1
8 }
9
10 declare i32 @llvm.flt.rounds() nounwind 
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