1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
4 define arm_aapcs_vfpcc <4 x i32> @sext_0246(<8 x i16> %src) {
5 ; CHECK-LABEL: sext_0246:
6 ; CHECK: @ %bb.0: @ %entry
7 ; CHECK-NEXT: vmovlb.s16 q0, q0
10 %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
11 %out = sext <4 x i16> %strided.vec to <4 x i32>
15 define arm_aapcs_vfpcc <4 x i32> @sext_1357(<8 x i16> %src) {
16 ; CHECK-LABEL: sext_1357:
17 ; CHECK: @ %bb.0: @ %entry
18 ; CHECK-NEXT: vrev32.16 q0, q0
19 ; CHECK-NEXT: vmovlb.s16 q0, q0
22 %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
23 %out = sext <4 x i16> %strided.vec to <4 x i32>
27 define arm_aapcs_vfpcc <4 x i32> @zext_0246(<8 x i16> %src) {
28 ; CHECK-LABEL: zext_0246:
29 ; CHECK: @ %bb.0: @ %entry
30 ; CHECK-NEXT: vmovlb.u16 q0, q0
33 %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
34 %out = zext <4 x i16> %strided.vec to <4 x i32>
38 define arm_aapcs_vfpcc <4 x i32> @zext_1357(<8 x i16> %src) {
39 ; CHECK-LABEL: zext_1357:
40 ; CHECK: @ %bb.0: @ %entry
41 ; CHECK-NEXT: vrev32.16 q0, q0
42 ; CHECK-NEXT: vmovlb.u16 q0, q0
45 %strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
46 %out = zext <4 x i16> %strided.vec to <4 x i32>
50 define arm_aapcs_vfpcc <8 x i16> @sext_02468101214(<16 x i8> %src) {
51 ; CHECK-LABEL: sext_02468101214:
52 ; CHECK: @ %bb.0: @ %entry
53 ; CHECK-NEXT: vmovlb.s8 q0, q0
56 %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
57 %out = sext <8 x i8> %strided.vec to <8 x i16>
61 define arm_aapcs_vfpcc <8 x i16> @sext_13579111315(<16 x i8> %src) {
62 ; CHECK-LABEL: sext_13579111315:
63 ; CHECK: @ %bb.0: @ %entry
64 ; CHECK-NEXT: vrev16.8 q0, q0
65 ; CHECK-NEXT: vmovlb.s8 q0, q0
68 %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
69 %out = sext <8 x i8> %strided.vec to <8 x i16>
73 define arm_aapcs_vfpcc <8 x i16> @zext_02468101214(<16 x i8> %src) {
74 ; CHECK-LABEL: zext_02468101214:
75 ; CHECK: @ %bb.0: @ %entry
76 ; CHECK-NEXT: vmovlb.u8 q0, q0
79 %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
80 %out = zext <8 x i8> %strided.vec to <8 x i16>
84 define arm_aapcs_vfpcc <8 x i16> @zext_13579111315(<16 x i8> %src) {
85 ; CHECK-LABEL: zext_13579111315:
86 ; CHECK: @ %bb.0: @ %entry
87 ; CHECK-NEXT: vrev16.8 q0, q0
88 ; CHECK-NEXT: vmovlb.u8 q0, q0
91 %strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
92 %out = zext <8 x i8> %strided.vec to <8 x i16>