test/MC/AArch64/SVE2/directive-arch-negative.s

   1 // RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
   2
   3 .arch armv8-a+sve2
   4 .arch armv8-a+nosve2
   5 tbx z0.b, z1.b, z2.b
   6 // CHECK: error: instruction requires: sve2
   7 // CHECK-NEXT: tbx z0.b, z1.b, z2.b
   8
   9 .arch armv8-a+sve2-aes
  10 .arch armv8-a+nosve2-aes
  11 aesd z23.b, z23.b, z13.b
  12 // CHECK: error: instruction requires: sve2-aes
  13 // CHECK-NEXT: aesd z23.b, z23.b, z13.b
  14
  15 .arch armv8-a+sve2-sm4
  16 .arch armv8-a+nosve2-sm4
  17 sm4e z0.s, z0.s, z0.s
  18 // CHECK: error: instruction requires: sve2-sm4
  19 // CHECK-NEXT: sm4e z0.s, z0.s, z0.s
  20
  21 .arch armv8-a+sve2-sha3
  22 .arch armv8-a+nosve2-sha3
  23 rax1 z0.d, z0.d, z0.d
  24 // CHECK: error: instruction requires: sve2-sha3
  25 // CHECK-NEXT: rax1 z0.d, z0.d, z0.d
  26
  27 .arch armv8-a+sve2-bitperm
  28 .arch armv8-a+nosve2-bitperm
  29 bgrp z21.s, z10.s, z21.s
  30 // CHECK: error: instruction requires: sve2-bitperm
  31 // CHECK-NEXT: bgrp z21.s, z10.s, z21.s