1 // RUN
: not llvm-mc
-triple
=aarch64
-show-encoding
-mattr
=+sve2
2>&1 < %s| FileCheck
%s
3 // --------------------------------------------------------------------------//
4 // Source
and Destination Registers must match
6 fmaxp z0.h
, p0
/m
, z1.h
, z2.h
7 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: operand must match destination register
8 // CHECK-NEXT
: fmaxp z0.h
, p0
/m
, z1.h
, z2.h
9 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
12 // --------------------------------------------------------------------------//
13 // Invalid element width
15 fmaxp z0.
b, p0
/m
, z0.
b, z1.
b
16 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: invalid element width
17 // CHECK-NEXT
: fmaxp z0.
b, p0
/m
, z0.
b, z1.
b
18 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
21 // --------------------------------------------------------------------------//
22 // Element sizes must match
24 fmaxp z0.h
, p0
/m
, z0.s
, z1.s
25 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: invalid element width
26 // CHECK-NEXT
: fmaxp z0.h
, p0
/m
, z0.s
, z1.s
27 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
29 fmaxp z0.h
, p0
/m
, z0.h
, z1.s
30 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: invalid element width
31 // CHECK-NEXT
: fmaxp z0.h
, p0
/m
, z0.h
, z1.s
32 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
35 // --------------------------------------------------------------------------//
36 // Invalid predicate operation
38 fmaxp z0.h
, p0
/z
, z0.h
, z1.h
39 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: invalid operand for instruction
40 // CHECK-NEXT
: fmaxp z0.h
, p0
/z
, z0.h
, z1.h
41 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}:
44 // --------------------------------------------------------------------------//
45 // Predicate
not in restricted predicate range
47 fmaxp z0.h
, p8
/m
, z0.h
, z1.h
48 // CHECK
: [[@LINE-
1]]:{{[0-9]+}}: error
: invalid restricted predicate register
, expected p0.
.p7 (without element suffix)
49 // CHECK-NEXT
: fmaxp z0.h
, p8
/m
, z0.h
, z1.h
50 // CHECK-
NOT: [[@LINE-
1]]:{{[0-9]+}}: