test/MC/AArch64/SVE2/sqshlu-diagnostics.s

   1 // RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
   2
   3 sqshlu z0.b, p0/m, z0.b, #-1
   4 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
   5 // CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #-1
   6 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
   7
   8 sqshlu z0.b, p0/m, z0.b, #8
   9 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
  10 // CHECK-NEXT: sqshlu z0.b, p0/m, z0.b, #8
  11 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  12
  13 sqshlu z0.h, p0/m, z0.h, #-1
  14 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
  15 // CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #-1
  16 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  17
  18 sqshlu z0.h, p0/m, z0.h, #16
  19 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
  20 // CHECK-NEXT: sqshlu z0.h, p0/m, z0.h, #16
  21 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  22
  23 sqshlu z0.s, p0/m, z0.s, #-1
  24 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
  25 // CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #-1
  26 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  27
  28 sqshlu z0.s, p0/m, z0.s, #32
  29 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
  30 // CHECK-NEXT: sqshlu z0.s, p0/m, z0.s, #32
  31 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  32
  33 sqshlu z0.d, p0/m, z0.d, #-1
  34 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
  35 // CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #-1
  36 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  37
  38 sqshlu z0.d, p0/m, z0.d, #64
  39 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
  40 // CHECK-NEXT: sqshlu z0.d, p0/m, z0.d, #64
  41 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  42
  43
  44 // --------------------------------------------------------------------------//
  45 // Source and Destination Registers must match
  46
  47 sqshlu z0.b, p0/m, z1.b, #0
  48 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
  49 // CHECK-NEXT: sqshlu z0.b, p0/m, z1.b, #0
  50 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  51
  52
  53 // --------------------------------------------------------------------------//
  54 // Element sizes must match
  55
  56 sqshlu z0.b, p0/m, z0.d, #0
  57 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  58 // CHECK-NEXT: sqshlu z0.b, p0/m, z0.d, #0
  59 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  60
  61 sqshlu z0.d, p0/m, z0.b, #0
  62 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
  63 // CHECK-NEXT: sqshlu z0.d, p0/m, z0.b, #0
  64 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  65
  66
  67 // --------------------------------------------------------------------------//
  68 // Invalid predicate
  69
  70 sqshlu z0.b, p0/z, z0.b, #0
  71 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
  72 // CHECK-NEXT: sqshlu z0.b, p0/z, z0.b, #0
  73 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
  74
  75 sqshlu z0.b, p8/m, z0.b, #0
  76 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
  77 // CHECK-NEXT: sqshlu z0.b, p8/m, z0.b, #0
  78 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: