test/MC/AArch64/arm64-diags.s

   1 ; RUN: not llvm-mc -triple arm64-apple-darwin -show-encoding < %s 2> %t | FileCheck %s
   2 ; RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
   3
   4 foo:
   5
   6 ; The first should encode as an expression. The second should error expecting
   7 ; a register.
   8   ldr x3, (foo + 4)
   9   ldr x3, [foo + 4]
  10 ; CHECK:  ldr x3, foo+4               ; encoding: [0bAAA00011,A,A,0x58]
  11 ; CHECK:                              ;   fixup A - offset: 0, value: foo+4, kind: fixup_aarch64_ldr_pcrel_imm19
  12 ; CHECK-ERRORS: error: invalid operand for instruction
  13
  14 ; The last argument should be flagged as an error.  rdar://9576009
  15   ld4.8b        {v0, v1, v2, v3}, [x0], #33
  16 ; CHECK-ERRORS: error: invalid operand for instruction
  17 ; CHECK-ERRORS: ld4.8b  {v0, v1, v2, v3}, [x0], #33
  18
  19
  20         ldr x0, [x0, #804]
  21         ldr w0, [x0, #802]
  22         ldr x0, [x0, #804]!
  23         ldr w0, [w0, #301]!
  24         ldr x0, [x0], #804
  25         ldr w0, [w0], #301
  26
  27         ldp w3, w4, [x5, #11]!
  28         ldp x3, x4, [x5, #12]!
  29         ldp q3, q4, [x5, #12]!
  30         ldp w3, w4, [x5], #11
  31         ldp x3, x4, [x5], #12
  32         ldp q3, q4, [x5], #12
  33
  34         ldur x0, [x1, #-257]
  35
  36 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
  37 ; CHECK-ERRORS:         ldr x0, [x0, #804]
  38 ; CHECK-ERRORS:                 ^
  39 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
  40 ; CHECK-ERRORS:         ldr w0, [x0, #802]
  41 ; CHECK-ERRORS:                 ^
  42 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
  43 ; CHECK-ERRORS:         ldr x0, [x0, #804]!
  44 ; CHECK-ERRORS:                 ^
  45 ; CHECK-ERRORS: error: invalid operand for instruction
  46 ; CHECK-ERRORS:         ldr w0, [w0, #301]!
  47 ; CHECK-ERRORS:                  ^
  48 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
  49 ; CHECK-ERRORS:         ldr x0, [x0], #804
  50 ; CHECK-ERRORS:                       ^
  51 ; CHECK-ERRORS: error: invalid operand for instruction
  52 ; CHECK-ERRORS:         ldr w0, [w0], #301
  53 ; CHECK-ERRORS:                  ^
  54 ; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
  55 ; CHECK-ERRORS:         ldp w3, w4, [x5, #11]!
  56 ; CHECK-ERRORS:                     ^
  57 ; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
  58 ; CHECK-ERRORS:         ldp x3, x4, [x5, #12]!
  59 ; CHECK-ERRORS:                     ^
  60 ; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
  61 ; CHECK-ERRORS:         ldp q3, q4, [x5, #12]!
  62 ; CHECK-ERRORS:                     ^
  63 ; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
  64 ; CHECK-ERRORS:         ldp w3, w4, [x5], #11
  65 ; CHECK-ERRORS:                           ^
  66 ; CHECK-ERRORS: error: index must be a multiple of 8 in range [-512, 504].
  67 ; CHECK-ERRORS:         ldp x3, x4, [x5], #12
  68 ; CHECK-ERRORS:                           ^
  69 ; CHECK-ERRORS: error: index must be a multiple of 16 in range [-1024, 1008].
  70 ; CHECK-ERRORS:         ldp q3, q4, [x5], #12
  71 ; CHECK-ERRORS:                           ^
  72 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
  73 ; CHECK-ERRORS:         ldur x0, [x1, #-257]
  74 ; CHECK-ERRORS:                   ^
  75
  76
  77 ldrb   w1, [x3, w3, sxtw #4]
  78 ldrh   w1, [x3, w3, sxtw #4]
  79 ldr    w1, [x3, w3, sxtw #4]
  80 ldr    x1, [x3, w3, sxtw #4]
  81 ldr    b1, [x3, w3, sxtw #4]
  82 ldr    h1, [x3, w3, sxtw #4]
  83 ldr    s1, [x3, w3, sxtw #4]
  84 ldr    d1, [x3, w3, sxtw #4]
  85 ldr    q1, [x3, w3, sxtw #1]
  86
  87 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
  88 ; CHECK-ERRORS:ldrb   w1, [x3, w3, sxtw #4]
  89 ; CHECK-ERRORS:           ^
  90 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
  91 ; CHECK-ERRORS:ldrh   w1, [x3, w3, sxtw #4]
  92 ; CHECK-ERRORS:           ^
  93 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
  94 ; CHECK-ERRORS:ldr    w1, [x3, w3, sxtw #4]
  95 ; CHECK-ERRORS:           ^
  96 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
  97 ; CHECK-ERRORS:ldr    x1, [x3, w3, sxtw #4]
  98 ; CHECK-ERRORS:           ^
  99 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0
 100 ; CHECK-ERRORS:ldr    b1, [x3, w3, sxtw #4]
 101 ; CHECK-ERRORS:           ^
 102 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #1
 103 ; CHECK-ERRORS:ldr    h1, [x3, w3, sxtw #4]
 104 ; CHECK-ERRORS:           ^
 105 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #2
 106 ; CHECK-ERRORS:ldr    s1, [x3, w3, sxtw #4]
 107 ; CHECK-ERRORS:           ^
 108 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
 109 ; CHECK-ERRORS:ldr    d1, [x3, w3, sxtw #4]
 110 ; CHECK-ERRORS:           ^
 111 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #4
 112 ; CHECK-ERRORS:ldr    q1, [x3, w3, sxtw #1]
 113 ; CHECK-ERRORS:           ^
 114
 115 ; Check that register offset addressing modes only accept 32-bit offset
 116 ; registers when using uxtw/sxtw extends. Everything else requires a 64-bit
 117 ; register.
 118   str    d1, [x3, w3, sxtx #3]
 119   ldr    s1, [x3, d3, sxtx #2]
 120
 121 ; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
 122 ; CHECK-ERRORS:   str    d1, [x3, w3, sxtx #3]
 123 ; CHECK-ERRORS:                       ^
 124 ; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
 125 ; CHECK-ERRORS:   ldr    s1, [x3, d3, sxtx #2]
 126 ; CHECK-ERRORS:                   ^
 127
 128 ; Shift immediates range checking.
 129   sqrshrn b4, h9, #10
 130   rshrn v9.8b, v11.8h, #17
 131   sqrshrn v7.4h, v8.4s, #39
 132   uqshrn2 v4.4s, v5.2d, #67
 133
 134 ; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
 135 ; CHECK-ERRORS:   sqrshrn b4, h9, #10
 136 ; CHECK-ERRORS:                   ^
 137 ; CHECK-ERRORS: error: immediate must be an integer in range [1, 8].
 138 ; CHECK-ERRORS:   rshrn v9.8b, v11.8h, #17
 139 ; CHECK-ERRORS:                        ^
 140 ; CHECK-ERRORS: error: immediate must be an integer in range [1, 16].
 141 ; CHECK-ERRORS:   sqrshrn v7.4h, v8.4s, #39
 142 ; CHECK-ERRORS:                         ^
 143 ; CHECK-ERRORS: error: immediate must be an integer in range [1, 32].
 144 ; CHECK-ERRORS:   uqshrn2 v4.4s, v5.2d, #67
 145 ; CHECK-ERRORS:                         ^
 146
 147
 148   st1.s4 {v14, v15}, [x2], #32
 149 ; CHECK-ERRORS: error: invalid type suffix for instruction
 150 ; CHECK-ERRORS: st1.s4 {v14, v15}, [x2], #32
 151 ; CHECK-ERRORS:     ^
 152
 153
 154
 155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
 156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
 157   ldp x1, x2, [x2], #16
 158   ldp x2, x2, [x2], #16
 159   ldp w1, w2, [x2], #16
 160   ldp w2, w2, [x2], #16
 161   ldp x1, x1, [x2]
 162   ldp s1, s1, [x1], #8
 163   ldp s1, s1, [x1, #8]!
 164   ldp s1, s1, [x1, #8]
 165   ldp d1, d1, [x1], #16
 166   ldp d1, d1, [x1, #16]!
 167   ldp d1, d1, [x1, #16]
 168   ldp q1, q1, [x1], #32
 169   ldp q1, q1, [x1, #32]!
 170   ldp q1, q1, [x1, #32]
 171
 172   ldr x2, [x2], #8
 173   ldr x2, [x2, #8]!
 174   ldr w2, [x2], #8
 175   ldr w2, [x2, #8]!
 176
 177   str x2, [x2], #8
 178   str x2, [x2, #8]!
 179   str w2, [x2], #8
 180   str w2, [x2, #8]!
 181
 182 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
 183 ; CHECK-ERRORS:   ldp x1, x2, [x2], #16
 184 ; CHECK-ERRORS:           ^
 185 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
 186 ; CHECK-ERRORS:   ldp x2, x2, [x2], #16
 187 ; CHECK-ERRORS:       ^
 188 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
 189 ; CHECK-ERRORS:   ldp w1, w2, [x2], #16
 190 ; CHECK-ERRORS:           ^
 191 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
 192 ; CHECK-ERRORS:   ldp w2, w2, [x2], #16
 193 ; CHECK-ERRORS:       ^
 194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 195 ; CHECK-ERRORS:   ldp x1, x1, [x2]
 196 ; CHECK-ERRORS:           ^
 197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 198 ; CHECK-ERRORS:   ldp s1, s1, [x1], #8
 199 ; CHECK-ERRORS:           ^
 200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 201 ; CHECK-ERRORS:   ldp s1, s1, [x1, #8]!
 202 ; CHECK-ERRORS:           ^
 203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 204 ; CHECK-ERRORS:   ldp s1, s1, [x1, #8]
 205 ; CHECK-ERRORS:           ^
 206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 207 ; CHECK-ERRORS:   ldp d1, d1, [x1], #16
 208 ; CHECK-ERRORS:           ^
 209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 210 ; CHECK-ERRORS:   ldp d1, d1, [x1, #16]!
 211 ; CHECK-ERRORS:           ^
 212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 213 ; CHECK-ERRORS:   ldp d1, d1, [x1, #16]
 214 ; CHECK-ERRORS:           ^
 215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 216 ; CHECK-ERRORS:   ldp q1, q1, [x1], #32
 217 ; CHECK-ERRORS:           ^
 218 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 219 ; CHECK-ERRORS:   ldp q1, q1, [x1, #32]!
 220 ; CHECK-ERRORS:           ^
 221 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
 222 ; CHECK-ERRORS:   ldp q1, q1, [x1, #32]
 223 ; CHECK-ERRORS:           ^
 224 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
 225 ; CHECK-ERRORS:   ldr x2, [x2], #8
 226 ; CHECK-ERRORS:       ^
 227 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
 228 ; CHECK-ERRORS:   ldr x2, [x2, #8]!
 229 ; CHECK-ERRORS:       ^
 230 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
 231 ; CHECK-ERRORS:   ldr w2, [x2], #8
 232 ; CHECK-ERRORS:       ^
 233 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
 234 ; CHECK-ERRORS:   ldr w2, [x2, #8]!
 235 ; CHECK-ERRORS:       ^
 236 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
 237 ; CHECK-ERRORS:   str x2, [x2], #8
 238 ; CHECK-ERRORS:       ^
 239 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
 240 ; CHECK-ERRORS:   str x2, [x2, #8]!
 241 ; CHECK-ERRORS:       ^
 242 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
 243 ; CHECK-ERRORS:   str w2, [x2], #8
 244 ; CHECK-ERRORS:       ^
 245 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
 246 ; CHECK-ERRORS:   str w2, [x2, #8]!
 247 ; CHECK-ERRORS:       ^
 248
 249 ; Store exclusive instructions are unpredictable if the status register clashes
 250 ; with anything.
 251   stlxrb w1, w1, [x5]
 252   stxrb w3, w5, [x3]
 253   stxrh w7, w9, [x7]
 254   stlxrh wzr, wzr, [x13]
 255   stxr w9, w9, [x12]
 256   stlxr w22, x1, [x22]
 257   stxr w4, x4, [x9]
 258   stlxr w5, x0, [x5]
 259 ; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
 260 ; CHECK-ERRORS:   stlxrb w1, w1, [x5]
 261 ; CHECK-ERRORS:          ^
 262 ; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
 263 ; CHECK-ERRORS:   stxrb w3, w5, [x3]
 264 ; CHECK-ERRORS:         ^
 265 ; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
 266 ; CHECK-ERRORS:   stxrh w7, w9, [x7]
 267 ; CHECK-ERRORS:         ^
 268 ; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
 269 ; CHECK-ERRORS:   stlxrh wzr, wzr, [x13]
 270 ; CHECK-ERRORS:          ^
 271 ; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
 272 ; CHECK-ERRORS:   stxr w9, w9, [x12]
 273 ; CHECK-ERRORS:        ^
 274 ; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
 275 ; CHECK-ERRORS:   stlxr w22, x1, [x22]
 276 ; CHECK-ERRORS:         ^
 277 ; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
 278 ; CHECK-ERRORS:   stxr w4, x4, [x9]
 279 ; CHECK-ERRORS:        ^
 280 ; CHECK-ERRORS: error: unpredictable STXR instruction, status is also a source
 281 ; CHECK-ERRORS:   stlxr w5, x0, [x5]
 282 ; CHECK-ERRORS:         ^
 283
 284   stxp w0, w0, w1, [x3]
 285   stxp w0, w1, w0, [x5]
 286   stxp w10, w4, w5, [x10]
 287   stxp wzr, xzr, x4, [x5]
 288   stxp w3, x5, x3, [sp]
 289   stxp w25, x4, x2, [x25]
 290 ; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
 291 ; CHECK-ERRORS:   stxp w0, w0, w1, [x3]
 292 ; CHECK-ERRORS:        ^
 293 ; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
 294 ; CHECK-ERRORS:   stxp w0, w1, w0, [x5]
 295 ; CHECK-ERRORS:        ^
 296 ; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
 297 ; CHECK-ERRORS:   stxp w10, w4, w5, [x10]
 298 ; CHECK-ERRORS:        ^
 299 ; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
 300 ; CHECK-ERRORS:   stxp wzr, xzr, x4, [x5]
 301 ; CHECK-ERRORS:        ^
 302 ; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
 303 ; CHECK-ERRORS:   stxp w3, x5, x3, [sp]
 304 ; CHECK-ERRORS:        ^
 305 ; CHECK-ERRORS: error: unpredictable STXP instruction, status is also a source
 306 ; CHECK-ERRORS:   stxp w25, x4, x2, [x25]
 307 ; CHECK-ERRORS:        ^
 308
 309
 310 ; The validity checking for shifted-immediate operands.  rdar://13174476
 311 ; Where the immediate is out of range.
 312   add w1, w2, w3, lsr #75
 313
 314 ; CHECK-ERRORS: error: expected 'sxtx' 'uxtx' or 'lsl' with optional integer in range [0, 4]
 315 ; CHECK-ERRORS: add w1, w2, w3, lsr #75
 316 ; CHECK-ERRORS:                      ^
 317
 318 ; logical instructions on 32-bit regs with shift > 31 is not legal
 319 orr w0, w0, w0, lsl #32
 320 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
 321 ; CHECK-ERRORS:        orr w0, w0, w0, lsl #32
 322 ; CHECK-ERRORS:                        ^
 323 eor w0, w0, w0, lsl #32
 324 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
 325 ; CHECK-ERRORS:        eor w0, w0, w0, lsl #32
 326 ; CHECK-ERRORS:                        ^
 327 and w0, w0, w0, lsl #32
 328 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
 329 ; CHECK-ERRORS:        and w0, w0, w0, lsl #32
 330 ; CHECK-ERRORS:                        ^
 331 ands w0, w0, w0, lsl #32
 332 ; CHECK-ERRORS: error: expected 'lsl', 'lsr' or 'asr' with optional integer in range [0, 31]
 333 ; CHECK-ERRORS:        ands w0, w0, w0, lsl #32
 334 ; CHECK-ERRORS:                        ^
 335
 336 ; Relocated expressions should not be accepted for 32-bit adds or sub (imm)
 337 add w3, w5, sym@PAGEOFF
 338 ; CHECK-ERRORS: error: invalid immediate expression
 339 ; CHECK-ERRORS: add w3, w5, sym@PAGEOFF
 340 ; CHECK-ERRORS:             ^
 341
 342 adds w3, w5, sym@PAGEOFF
 343 adds x9, x12, sym@PAGEOFF
 344 ; CHECK-ERRORS: error: invalid immediate expression
 345 ; CHECK-ERRORS: adds w3, w5, sym@PAGEOFF
 346 ; CHECK-ERRORS:              ^
 347 ; CHECK-ERRORS: error: invalid immediate expression
 348 ; CHECK-ERRORS: adds x9, x12, sym@PAGEOFF
 349 ; CHECK-ERRORS:               ^
 350
 351 sub x3, x5, sym@PAGEOFF
 352 sub w20, w30, sym@PAGEOFF
 353 ; CHECK-ERRORS: error: invalid immediate expression
 354 ; CHECK-ERRORS: sub x3, x5, sym@PAGEOFF
 355 ; CHECK-ERRORS:             ^
 356 ; CHECK-ERRORS: error: invalid immediate expression
 357 ; CHECK-ERRORS: sub w20, w30, sym@PAGEOFF
 358 ; CHECK-ERRORS:               ^
 359
 360 subs w9, w10, sym@PAGEOFF
 361 subs x20, x30, sym@PAGEOFF
 362 ; CHECK-ERRORS: error: invalid immediate expression
 363 ; CHECK-ERRORS: subs w9, w10, sym@PAGEOFF
 364 ; CHECK-ERRORS:               ^
 365 ; CHECK-ERRORS: error: invalid immediate expression
 366 ; CHECK-ERRORS: subs x20, x30, sym@PAGEOFF
 367 ; CHECK-ERRORS:                ^
 368
 369 tbl v0.8b, { v1 }, v0.8b
 370 tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
 371 tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
 372 tbx v2.8b, { v0 }, v6.8b
 373 ; CHECK-ERRORS: error: invalid operand for instruction
 374 ; CHECK-ERRORS: tbl v0.8b, { v1 }, v0.8b
 375 ; CHECK-ERRORS:            ^
 376 ; CHECK-ERRORS: error: invalid operand for instruction
 377 ; CHECK-ERRORS: tbl v0.16b, { v1.8b, v2.8b, v3.8b }, v0.16b
 378 ; CHECK-ERRORS:             ^
 379 ; CHECK-ERRORS: error: invalid operand for instruction
 380 ; CHECK-ERRORS: tbx v3.16b, { v12.8b, v13.8b, v14.8b }, v6.8b
 381 ; CHECK-ERRORS:             ^
 382 ; CHECK-ERRORS: error: invalid operand for instruction
 383 ; CHECK-ERRORS: tbx v2.8b, { v0 }, v6.8b
 384 ; CHECK-ERRORS:            ^
 385
 386 b.c #0x4
 387 ; CHECK-ERRORS: error: invalid condition code
 388 ; CHECK-ERRORS: b.c #0x4
 389 ; CHECK-ERRORS:   ^
 390
 391 ic ialluis, x0
 392 ; CHECK-ERRORS: error: specified ic op does not use a register
 393 ic iallu, x0
 394 ; CHECK-ERRORS: error: specified ic op does not use a register
 395 ic ivau
 396 ; CHECK-ERRORS: error: specified ic op requires a register
 397
 398 dc zva
 399 ; CHECK-ERRORS: error: specified dc op requires a register
 400 dc ivac
 401 ; CHECK-ERRORS: error: specified dc op requires a register
 402 dc isw
 403 ; CHECK-ERRORS: error: specified dc op requires a register
 404 dc cvac
 405 ; CHECK-ERRORS: error: specified dc op requires a register
 406 dc csw
 407 ; CHECK-ERRORS: error: specified dc op requires a register
 408 dc cvau
 409 ; CHECK-ERRORS: error: specified dc op requires a register
 410 dc civac
 411 ; CHECK-ERRORS: error: specified dc op requires a register
 412 dc cisw
 413 ; CHECK-ERRORS: error: specified dc op requires a register
 414
 415 at s1e1r
 416 ; CHECK-ERRORS: error: specified at op requires a register
 417 at s1e2r
 418 ; CHECK-ERRORS: error: specified at op requires a register
 419 at s1e3r
 420 ; CHECK-ERRORS: error: specified at op requires a register
 421 at s1e1w
 422 ; CHECK-ERRORS: error: specified at op requires a register
 423 at s1e2w
 424 ; CHECK-ERRORS: error: specified at op requires a register
 425 at s1e3w
 426 ; CHECK-ERRORS: error: specified at op requires a register
 427 at s1e0r
 428 ; CHECK-ERRORS: error: specified at op requires a register
 429 at s1e0w
 430 ; CHECK-ERRORS: error: specified at op requires a register
 431 at s12e1r
 432 ; CHECK-ERRORS: error: specified at op requires a register
 433 at s12e1w
 434 ; CHECK-ERRORS: error: specified at op requires a register
 435 at s12e0r
 436 ; CHECK-ERRORS: error: specified at op requires a register
 437 at s12e0w
 438 ; CHECK-ERRORS: error: specified at op requires a register
 439
 440 tlbi vmalle1is, x0
 441 ; CHECK-ERRORS: error: specified tlbi op does not use a register
 442 tlbi vmalle1, x0
 443 ; CHECK-ERRORS: error: specified tlbi op does not use a register
 444 tlbi alle1is, x0
 445 ; CHECK-ERRORS: error: specified tlbi op does not use a register
 446 tlbi alle2is, x0
 447 ; CHECK-ERRORS: error: specified tlbi op does not use a register
 448 tlbi alle3is, x0
 449 ; CHECK-ERRORS: error: specified tlbi op does not use a register
 450 tlbi alle1, x0
 451 ; CHECK-ERRORS: error: specified tlbi op does not use a register
 452 tlbi alle2, x0
 453 ; CHECK-ERRORS: error: specified tlbi op does not use a register
 454 tlbi alle3, x0
 455 ; CHECK-ERRORS: error: specified tlbi op does not use a register
 456 tlbi vae1is
 457 ; CHECK-ERRORS: error: specified tlbi op requires a register
 458 tlbi vae2is
 459 ; CHECK-ERRORS: error: specified tlbi op requires a register
 460 tlbi vae3is
 461 ; CHECK-ERRORS: error: specified tlbi op requires a register
 462 tlbi aside1is
 463 ; CHECK-ERRORS: error: specified tlbi op requires a register
 464 tlbi vaae1is
 465 ; CHECK-ERRORS: error: specified tlbi op requires a register
 466 tlbi vale1is
 467 ; CHECK-ERRORS: error: specified tlbi op requires a register
 468 tlbi vaale1is
 469 ; CHECK-ERRORS: error: specified tlbi op requires a register
 470 tlbi vale2is
 471 ; CHECK-ERRORS: error: specified tlbi op requires a register
 472 tlbi vale3is
 473 ; CHECK-ERRORS: error: specified tlbi op requires a register
 474 tlbi vae1
 475 ; CHECK-ERRORS: error: specified tlbi op requires a register
 476 tlbi vae2
 477 ; CHECK-ERRORS: error: specified tlbi op requires a register
 478 tlbi vae3
 479 ; CHECK-ERRORS: error: specified tlbi op requires a register
 480 tlbi aside1
 481 ; CHECK-ERRORS: error: specified tlbi op requires a register
 482 tlbi vaae1
 483 ; CHECK-ERRORS: error: specified tlbi op requires a register
 484 tlbi vale1
 485 ; CHECK-ERRORS: error: specified tlbi op requires a register
 486 tlbi vale2
 487 ; CHECK-ERRORS: error: specified tlbi op requires a register
 488 tlbi vale3
 489 ; CHECK-ERRORS: error: specified tlbi op requires a register
 490
 491
 492 ; Check that we give the proper "too few operands" diagnostic even when
 493 ; using short-form NEON.
 494
 495   add.16b v0, v1, v2, v3
 496   add.8b v0, v1
 497   sub.8h v0, v1
 498   fadd.4s v0
 499   fmul.2s
 500
 501 ; CHECK-ERRORS: error: invalid operand for instruction
 502 ; CHECK-ERRORS:   add.16b v0, v1, v2, v3
 503 ; CHECK-ERRORS:                       ^
 504 ; CHECK-ERRORS: error: too few operands for instruction
 505 ; CHECK-ERRORS:   add.8b v0, v1
 506 ; CHECK-ERRORS:   ^
 507 ; CHECK-ERRORS: error: too few operands for instruction
 508 ; CHECK-ERRORS:   sub.8h v0, v1
 509 ; CHECK-ERRORS:   ^
 510 ; CHECK-ERRORS: error: too few operands for instruction
 511 ; CHECK-ERRORS:   fadd.4s v0
 512 ; CHECK-ERRORS:   ^
 513 ; CHECK-ERRORS: error: too few operands for instruction
 514 ; CHECK-ERRORS:   fmul.2s
 515 ; CHECK-ERRORS:   ^
 516
 517 ; Also for 2-operand instructions.
 518
 519   frsqrte.4s v0, v1, v2
 520   frsqrte.2s v0
 521   frecpe.2d
 522
 523 ; CHECK-ERRORS: error: invalid operand for instruction
 524 ; CHECK-ERRORS:   frsqrte.4s v0, v1, v2
 525 ; CHECK-ERRORS:                      ^
 526 ; CHECK-ERRORS: error: too few operands for instruction
 527 ; CHECK-ERRORS:   frsqrte.2s v0
 528 ; CHECK-ERRORS:   ^
 529 ; CHECK-ERRORS: error: too few operands for instruction
 530 ; CHECK-ERRORS:   frecpe.2d
 531 ; CHECK-ERRORS:   ^
 532
 533 ; And check that we do the same for non-NEON instructions.
 534
 535   b.ne
 536   b.eq 0, 0
 537
 538 ; CHECK-ERRORS: error: too few operands for instruction
 539 ; CHECK-ERRORS:   b.ne
 540 ; CHECK-ERRORS:   ^
 541 ; CHECK-ERRORS: error: invalid operand for instruction
 542 ; CHECK-ERRORS:   b.eq 0, 0
 543 ; CHECK-ERRORS:           ^
 544
 545 ; Check that we give the proper "too few operands" diagnostic instead of
 546 ; asserting.
 547
 548   ldr
 549
 550 ; CHECK-ERRORS: error: too few operands for instruction
 551 ; CHECK-ERRORS:   ldr
 552 ; CHECK-ERRORS:   ^