[InstCombine] Signed saturation patterns
[llvm-core.git] / test / MC / AArch64 / elf-globaladdress.ll
blobd8a0b5b8d5e7772ad944c4c6b8b3863fd35a04bb
1 ;; RUN: llc -mtriple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
2 ;; RUN:   llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s
4 ; Also take it on a round-trip through llvm-mc to stretch assembly-parsing's legs:
5 ;; RUN: llc -mtriple=aarch64-none-linux-gnu %s -o - | \
6 ;; RUN:     llvm-mc -triple=arm64-none-linux-gnu -filetype=obj -o - | \
7 ;; RUN:     llvm-readobj -h -r | FileCheck -check-prefix=OBJ %s
9 @var8 = global i8 0
10 @var16 = global i16 0
11 @var32 = global i32 0
12 @var64 = global i64 0
14 define void @loadstore() {
15     %val8 = load i8, i8* @var8
16     store volatile i8 %val8, i8* @var8
18     %val16 = load i16, i16* @var16
19     store volatile i16 %val16, i16* @var16
21     %val32 = load i32, i32* @var32
22     store volatile i32 %val32, i32* @var32
24     %val64 = load i64, i64* @var64
25     store volatile i64 %val64, i64* @var64
27     ret void
30 @globaddr = global i64* null
32 define void @address() {
33     store i64* @var64, i64** @globaddr
34     ret void
37 ; Check we're using EM_AARCH64
38 ; OBJ: ElfHeader {
39 ; OBJ:   Machine: EM_AARCH64
40 ; OBJ: }
42 ; OBJ: Relocations [
43 ; OBJ:   Section {{.*}} .rela.text {
44 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21   var8
45 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_LDST8_ABS_LO12_NC  var8
46 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21   var16
47 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_LDST16_ABS_LO12_NC var16
48 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21   var32
49 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_LDST32_ABS_LO12_NC var32
50 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21   var64
51 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_LDST64_ABS_LO12_NC var64
53 ; This is on the store, so not really important, but it stops the next
54 ; match working.
55 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_LDST64_ABS_LO12_NC var64
57 ; Pure address-calculation against var64
58 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21   var64
59 ; OBJ:     0x{{[0-9,A-F]+}} R_AARCH64_ADD_ABS_LO12_NC    var64
61 ; OBJ:   }
62 ; OBJ: ]