[InstCombine] Signed saturation patterns
[llvm-core.git] / test / MC / ELF / relax-arith3.s
blob88f7ba30e3259c30dc8e9f3a21cd76c5b3ffe014
1 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o - | llvm-objdump -d - | FileCheck %s
3 // Test that we correctly relax these instructions into versions that use
4 // 16 or 32 bit immediate values.
6 bar:
7 // CHECK: Disassembly of section imul:
8 // CHECK-EMPTY:
9 // CHECK-NEXT: imul:
10 // CHECK-NEXT: 0: 66 69 1d 00 00 00 00 00 00 imulw $0, (%rip), %bx
11 // CHECK-NEXT: 9: 69 1d 00 00 00 00 00 00 00 00 imull $0, (%rip), %ebx
12 // CHECK-NEXT: 13: 48 69 1d 00 00 00 00 00 00 00 00 imulq $0, (%rip), %rbx
13 .section imul,"x"
14 imul $foo, bar(%rip), %bx
15 imul $foo, bar(%rip), %ebx
16 imul $foo, bar(%rip), %rbx
19 // CHECK: Disassembly of section and:
20 // CHECK-EMPTY:
21 // CHECK-NEXT: and:
22 // CHECK-NEXT: 0: 66 81 25 00 00 00 00 00 00 andw $0, (%rip)
23 // CHECK-NEXT: 9: 81 25 00 00 00 00 00 00 00 00 andl $0, (%rip)
24 // CHECK-NEXT: 13: 48 81 25 00 00 00 00 00 00 00 00 andq $0, (%rip)
25 .section and,"x"
26 andw $foo, bar(%rip)
27 andl $foo, bar(%rip)
28 andq $foo, bar(%rip)
30 // CHECK: Disassembly of section or:
31 // CHECK-EMPTY:
32 // CHECK-NEXT: or:
33 // CHECK-NEXT: 0: 66 81 0d 00 00 00 00 00 00 orw $0, (%rip)
34 // CHECK-NEXT: 9: 81 0d 00 00 00 00 00 00 00 00 orl $0, (%rip)
35 // CHECK-NEXT: 13: 48 81 0d 00 00 00 00 00 00 00 00 orq $0, (%rip)
36 .section or,"x"
37 orw $foo, bar(%rip)
38 orl $foo, bar(%rip)
39 orq $foo, bar(%rip)
41 // CHECK: Disassembly of section xor:
42 // CHECK-EMPTY:
43 // CHECK-NEXT: xor:
44 // CHECK-NEXT: 0: 66 81 35 00 00 00 00 00 00 xorw $0, (%rip)
45 // CHECK-NEXT: 9: 81 35 00 00 00 00 00 00 00 00 xorl $0, (%rip)
46 // CHECK-NEXT: 13: 48 81 35 00 00 00 00 00 00 00 00 xorq $0, (%rip)
47 .section xor,"x"
48 xorw $foo, bar(%rip)
49 xorl $foo, bar(%rip)
50 xorq $foo, bar(%rip)
52 // CHECK: Disassembly of section add:
53 // CHECK-EMPTY:
54 // CHECK-NEXT: add:
55 // CHECK-NEXT: 0: 66 81 05 00 00 00 00 00 00 addw $0, (%rip)
56 // CHECK-NEXT: 9: 81 05 00 00 00 00 00 00 00 00 addl $0, (%rip)
57 // CHECK-NEXT: 13: 48 81 05 00 00 00 00 00 00 00 00 addq $0, (%rip)
58 .section add,"x"
59 addw $foo, bar(%rip)
60 addl $foo, bar(%rip)
61 addq $foo, bar(%rip)
63 // CHECK: Disassembly of section sub:
64 // CHECK-EMPTY:
65 // CHECK-NEXT: sub:
66 // CHECK-NEXT: 0: 66 81 2d 00 00 00 00 00 00 subw $0, (%rip)
67 // CHECK-NEXT: 9: 81 2d 00 00 00 00 00 00 00 00 subl $0, (%rip)
68 // CHECK-NEXT: 13: 48 81 2d 00 00 00 00 00 00 00 00 subq $0, (%rip)
69 .section sub,"x"
70 subw $foo, bar(%rip)
71 subl $foo, bar(%rip)
72 subq $foo, bar(%rip)
74 // CHECK: Disassembly of section cmp:
75 // CHECK-EMPTY:
76 // CHECK-NEXT: cmp:
77 // CHECK-NEXT: 0: 66 81 3d 00 00 00 00 00 00 cmpw $0, (%rip)
78 // CHECK-NEXT: 9: 81 3d 00 00 00 00 00 00 00 00 cmpl $0, (%rip)
79 // CHECK-NEXT: 13: 48 81 3d 00 00 00 00 00 00 00 00 cmpq $0, (%rip)
80 .section cmp,"x"
81 cmpw $foo, bar(%rip)
82 cmpl $foo, bar(%rip)
83 cmpq $foo, bar(%rip)