[InstCombine] Signed saturation patterns
[llvm-core.git] / test / MC / RISCV / rv64f-invalid.s
blob698da796a7e70d09348e97b64ae4d30d4373e818
1 # RUN: not llvm-mc -triple riscv64 -mattr=+f < %s 2>&1 | FileCheck %s
3 # Integer registers where FP regs are expected
4 fcvt.l.s ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
5 fcvt.lu.s ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
7 # FP registers where integer regs are expected
8 fcvt.s.l a2, ft2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
9 fcvt.s.lu a3, ft3 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction