1 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2 ; RUN: opt < %s -slp-vectorizer -instcombine -S | FileCheck %s
4 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
5 target triple = "aarch64--linux-gnu"
7 define <2 x i64> @build_vec_v2i64(<2 x i64> %v0, <2 x i64> %v1) {
8 ; CHECK-LABEL: @build_vec_v2i64(
9 ; CHECK-NEXT: [[V0_0:%.*]] = extractelement <2 x i64> [[V0:%.*]], i32 0
10 ; CHECK-NEXT: [[V0_1:%.*]] = extractelement <2 x i64> [[V0]], i32 1
11 ; CHECK-NEXT: [[V1_0:%.*]] = extractelement <2 x i64> [[V1:%.*]], i32 0
12 ; CHECK-NEXT: [[V1_1:%.*]] = extractelement <2 x i64> [[V1]], i32 1
13 ; CHECK-NEXT: [[TMP0_0:%.*]] = add i64 [[V0_0]], [[V1_0]]
14 ; CHECK-NEXT: [[TMP0_1:%.*]] = add i64 [[V0_1]], [[V1_1]]
15 ; CHECK-NEXT: [[TMP1_0:%.*]] = sub i64 [[V0_0]], [[V1_0]]
16 ; CHECK-NEXT: [[TMP1_1:%.*]] = sub i64 [[V0_1]], [[V1_1]]
17 ; CHECK-NEXT: [[TMP2_0:%.*]] = add i64 [[TMP0_0]], [[TMP0_1]]
18 ; CHECK-NEXT: [[TMP2_1:%.*]] = add i64 [[TMP1_0]], [[TMP1_1]]
19 ; CHECK-NEXT: [[TMP3_0:%.*]] = insertelement <2 x i64> undef, i64 [[TMP2_0]], i32 0
20 ; CHECK-NEXT: [[TMP3_1:%.*]] = insertelement <2 x i64> [[TMP3_0]], i64 [[TMP2_1]], i32 1
21 ; CHECK-NEXT: ret <2 x i64> [[TMP3_1]]
23 %v0.0 = extractelement <2 x i64> %v0, i32 0
24 %v0.1 = extractelement <2 x i64> %v0, i32 1
25 %v1.0 = extractelement <2 x i64> %v1, i32 0
26 %v1.1 = extractelement <2 x i64> %v1, i32 1
27 %tmp0.0 = add i64 %v0.0, %v1.0
28 %tmp0.1 = add i64 %v0.1, %v1.1
29 %tmp1.0 = sub i64 %v0.0, %v1.0
30 %tmp1.1 = sub i64 %v0.1, %v1.1
31 %tmp2.0 = add i64 %tmp0.0, %tmp0.1
32 %tmp2.1 = add i64 %tmp1.0, %tmp1.1
33 %tmp3.0 = insertelement <2 x i64> undef, i64 %tmp2.0, i32 0
34 %tmp3.1 = insertelement <2 x i64> %tmp3.0, i64 %tmp2.1, i32 1
38 define void @store_chain_v2i64(i64* %a, i64* %b, i64* %c) {
39 ; CHECK-LABEL: @store_chain_v2i64(
40 ; CHECK-NEXT: [[A_1:%.*]] = getelementptr i64, i64* [[A:%.*]], i64 1
41 ; CHECK-NEXT: [[B_1:%.*]] = getelementptr i64, i64* [[B:%.*]], i64 1
42 ; CHECK-NEXT: [[C_1:%.*]] = getelementptr i64, i64* [[C:%.*]], i64 1
43 ; CHECK-NEXT: [[V0_0:%.*]] = load i64, i64* [[A]], align 8
44 ; CHECK-NEXT: [[V0_1:%.*]] = load i64, i64* [[A_1]], align 8
45 ; CHECK-NEXT: [[V1_0:%.*]] = load i64, i64* [[B]], align 8
46 ; CHECK-NEXT: [[V1_1:%.*]] = load i64, i64* [[B_1]], align 8
47 ; CHECK-NEXT: [[TMP0_0:%.*]] = add i64 [[V0_0]], [[V1_0]]
48 ; CHECK-NEXT: [[TMP0_1:%.*]] = add i64 [[V0_1]], [[V1_1]]
49 ; CHECK-NEXT: [[TMP1_0:%.*]] = sub i64 [[V0_0]], [[V1_0]]
50 ; CHECK-NEXT: [[TMP1_1:%.*]] = sub i64 [[V0_1]], [[V1_1]]
51 ; CHECK-NEXT: [[TMP2_0:%.*]] = add i64 [[TMP0_0]], [[TMP0_1]]
52 ; CHECK-NEXT: [[TMP2_1:%.*]] = add i64 [[TMP1_0]], [[TMP1_1]]
53 ; CHECK-NEXT: store i64 [[TMP2_0]], i64* [[C]], align 8
54 ; CHECK-NEXT: store i64 [[TMP2_1]], i64* [[C_1]], align 8
55 ; CHECK-NEXT: ret void
57 %a.0 = getelementptr i64, i64* %a, i64 0
58 %a.1 = getelementptr i64, i64* %a, i64 1
59 %b.0 = getelementptr i64, i64* %b, i64 0
60 %b.1 = getelementptr i64, i64* %b, i64 1
61 %c.0 = getelementptr i64, i64* %c, i64 0
62 %c.1 = getelementptr i64, i64* %c, i64 1
63 %v0.0 = load i64, i64* %a.0, align 8
64 %v0.1 = load i64, i64* %a.1, align 8
65 %v1.0 = load i64, i64* %b.0, align 8
66 %v1.1 = load i64, i64* %b.1, align 8
67 %tmp0.0 = add i64 %v0.0, %v1.0
68 %tmp0.1 = add i64 %v0.1, %v1.1
69 %tmp1.0 = sub i64 %v0.0, %v1.0
70 %tmp1.1 = sub i64 %v0.1, %v1.1
71 %tmp2.0 = add i64 %tmp0.0, %tmp0.1
72 %tmp2.1 = add i64 %tmp1.0, %tmp1.1
73 store i64 %tmp2.0, i64* %c.0, align 8
74 store i64 %tmp2.1, i64* %c.1, align 8
78 define <4 x i32> @build_vec_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
79 ; CHECK-LABEL: @build_vec_v4i32(
80 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 2>
81 ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
82 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 2>
83 ; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
84 ; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i32> [[SHUFFLE]], [[SHUFFLE1]]
85 ; CHECK-NEXT: [[TMP4:%.*]] = sub <4 x i32> [[SHUFFLE]], [[SHUFFLE1]]
86 ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
87 ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[V0]], <4 x i32> undef, <2 x i32> <i32 1, i32 3>
88 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
89 ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[V1]], <4 x i32> undef, <2 x i32> <i32 1, i32 3>
90 ; CHECK-NEXT: [[SHUFFLE3:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
91 ; CHECK-NEXT: [[TMP8:%.*]] = add <4 x i32> [[SHUFFLE2]], [[SHUFFLE3]]
92 ; CHECK-NEXT: [[TMP9:%.*]] = sub <4 x i32> [[SHUFFLE2]], [[SHUFFLE3]]
93 ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> [[TMP9]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
94 ; CHECK-NEXT: [[TMP11:%.*]] = add <4 x i32> [[TMP5]], [[TMP10]]
95 ; CHECK-NEXT: ret <4 x i32> [[TMP11]]
97 %v0.0 = extractelement <4 x i32> %v0, i32 0
98 %v0.1 = extractelement <4 x i32> %v0, i32 1
99 %v0.2 = extractelement <4 x i32> %v0, i32 2
100 %v0.3 = extractelement <4 x i32> %v0, i32 3
101 %v1.0 = extractelement <4 x i32> %v1, i32 0
102 %v1.1 = extractelement <4 x i32> %v1, i32 1
103 %v1.2 = extractelement <4 x i32> %v1, i32 2
104 %v1.3 = extractelement <4 x i32> %v1, i32 3
105 %tmp0.0 = add i32 %v0.0, %v1.0
106 %tmp0.1 = add i32 %v0.1, %v1.1
107 %tmp0.2 = add i32 %v0.2, %v1.2
108 %tmp0.3 = add i32 %v0.3, %v1.3
109 %tmp1.0 = sub i32 %v0.0, %v1.0
110 %tmp1.1 = sub i32 %v0.1, %v1.1
111 %tmp1.2 = sub i32 %v0.2, %v1.2
112 %tmp1.3 = sub i32 %v0.3, %v1.3
113 %tmp2.0 = add i32 %tmp0.0, %tmp0.1
114 %tmp2.1 = add i32 %tmp1.0, %tmp1.1
115 %tmp2.2 = add i32 %tmp0.2, %tmp0.3
116 %tmp2.3 = add i32 %tmp1.2, %tmp1.3
117 %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0
118 %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
119 %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.2, i32 2
120 %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.3, i32 3
121 ret <4 x i32> %tmp3.3
124 define <4 x i32> @build_vec_v4i32_reuse_0(<2 x i32> %v0, <2 x i32> %v1) {
125 ; CHECK-LABEL: @build_vec_v4i32_reuse_0(
126 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
127 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[V1:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
128 ; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP1]], [[TMP2]]
129 ; CHECK-NEXT: [[TMP4:%.*]] = sub <2 x i32> [[TMP1]], [[TMP2]]
130 ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> <i32 0, i32 3>
131 ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[V0]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>
132 ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[V1]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>
133 ; CHECK-NEXT: [[TMP8:%.*]] = add <2 x i32> [[TMP6]], [[TMP7]]
134 ; CHECK-NEXT: [[TMP9:%.*]] = sub <2 x i32> [[TMP6]], [[TMP7]]
135 ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> [[TMP9]], <2 x i32> <i32 0, i32 3>
136 ; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i32> [[TMP5]], [[TMP10]]
137 ; CHECK-NEXT: [[TMP3_3:%.*]] = shufflevector <2 x i32> [[TMP11]], <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
138 ; CHECK-NEXT: ret <4 x i32> [[TMP3_3]]
140 %v0.0 = extractelement <2 x i32> %v0, i32 0
141 %v0.1 = extractelement <2 x i32> %v0, i32 1
142 %v1.0 = extractelement <2 x i32> %v1, i32 0
143 %v1.1 = extractelement <2 x i32> %v1, i32 1
144 %tmp0.0 = add i32 %v0.0, %v1.0
145 %tmp0.1 = add i32 %v0.1, %v1.1
146 %tmp1.0 = sub i32 %v0.0, %v1.0
147 %tmp1.1 = sub i32 %v0.1, %v1.1
148 %tmp2.0 = add i32 %tmp0.0, %tmp0.1
149 %tmp2.1 = add i32 %tmp1.0, %tmp1.1
150 %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0
151 %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
152 %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.0, i32 2
153 %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.1, i32 3
154 ret <4 x i32> %tmp3.3
157 define <4 x i32> @build_vec_v4i32_reuse_1(<2 x i32> %v0, <2 x i32> %v1) {
158 ; CHECK-LABEL: @build_vec_v4i32_reuse_1(
159 ; CHECK-NEXT: [[V0_0:%.*]] = extractelement <2 x i32> [[V0:%.*]], i32 0
160 ; CHECK-NEXT: [[V0_1:%.*]] = extractelement <2 x i32> [[V0]], i32 1
161 ; CHECK-NEXT: [[V1_0:%.*]] = extractelement <2 x i32> [[V1:%.*]], i32 0
162 ; CHECK-NEXT: [[V1_1:%.*]] = extractelement <2 x i32> [[V1]], i32 1
163 ; CHECK-NEXT: [[TMP0_0:%.*]] = add i32 [[V0_0]], [[V1_0]]
164 ; CHECK-NEXT: [[TMP0_1:%.*]] = add i32 [[V0_1]], [[V1_1]]
165 ; CHECK-NEXT: [[TMP0_2:%.*]] = xor i32 [[V0_0]], [[V1_0]]
166 ; CHECK-NEXT: [[TMP0_3:%.*]] = xor i32 [[V0_1]], [[V1_1]]
167 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> undef, i32 [[TMP0_0]], i32 0
168 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> undef, i32 [[TMP0_1]], i32 0
169 ; CHECK-NEXT: [[TMP3:%.*]] = sub <2 x i32> [[TMP1]], [[TMP2]]
170 ; CHECK-NEXT: [[TMP1_2:%.*]] = sub i32 [[TMP0_2]], [[TMP0_3]]
171 ; CHECK-NEXT: [[TMP1_3:%.*]] = sub i32 [[TMP0_3]], [[TMP0_2]]
172 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i32> [[TMP3]], i32 0
173 ; CHECK-NEXT: [[TMP2_0:%.*]] = insertelement <4 x i32> undef, i32 [[TMP4]], i32 0
174 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i32> [[TMP3]], i32 0
175 ; CHECK-NEXT: [[TMP2_1:%.*]] = insertelement <4 x i32> [[TMP2_0]], i32 [[TMP5]], i32 1
176 ; CHECK-NEXT: [[TMP2_2:%.*]] = insertelement <4 x i32> [[TMP2_1]], i32 [[TMP1_2]], i32 2
177 ; CHECK-NEXT: [[TMP2_3:%.*]] = insertelement <4 x i32> [[TMP2_2]], i32 [[TMP1_3]], i32 3
178 ; CHECK-NEXT: ret <4 x i32> [[TMP2_3]]
180 %v0.0 = extractelement <2 x i32> %v0, i32 0
181 %v0.1 = extractelement <2 x i32> %v0, i32 1
182 %v1.0 = extractelement <2 x i32> %v1, i32 0
183 %v1.1 = extractelement <2 x i32> %v1, i32 1
184 %tmp0.0 = add i32 %v0.0, %v1.0
185 %tmp0.1 = add i32 %v0.1, %v1.1
186 %tmp0.2 = xor i32 %v0.0, %v1.0
187 %tmp0.3 = xor i32 %v0.1, %v1.1
188 %tmp1.0 = sub i32 %tmp0.0, %tmp0.1
189 %tmp1.1 = sub i32 %tmp0.0, %tmp0.1
190 %tmp1.2 = sub i32 %tmp0.2, %tmp0.3
191 %tmp1.3 = sub i32 %tmp0.3, %tmp0.2
192 %tmp2.0 = insertelement <4 x i32> undef, i32 %tmp1.0, i32 0
193 %tmp2.1 = insertelement <4 x i32> %tmp2.0, i32 %tmp1.1, i32 1
194 %tmp2.2 = insertelement <4 x i32> %tmp2.1, i32 %tmp1.2, i32 2
195 %tmp2.3 = insertelement <4 x i32> %tmp2.2, i32 %tmp1.3, i32 3
196 ret <4 x i32> %tmp2.3
199 define <4 x i32> @build_vec_v4i32_3_binops(<2 x i32> %v0, <2 x i32> %v1) {
200 ; CHECK-LABEL: @build_vec_v4i32_3_binops(
201 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i32> [[V0:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
202 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[V1:%.*]], <2 x i32> undef, <2 x i32> zeroinitializer
203 ; CHECK-NEXT: [[TMP3:%.*]] = add <2 x i32> [[TMP1]], [[TMP2]]
204 ; CHECK-NEXT: [[TMP4:%.*]] = mul <2 x i32> [[TMP1]], [[TMP2]]
205 ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> [[TMP4]], <2 x i32> <i32 0, i32 3>
206 ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[V0]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>
207 ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[V1]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>
208 ; CHECK-NEXT: [[TMP8:%.*]] = add <2 x i32> [[TMP6]], [[TMP7]]
209 ; CHECK-NEXT: [[TMP9:%.*]] = mul <2 x i32> [[TMP6]], [[TMP7]]
210 ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i32> [[TMP8]], <2 x i32> [[TMP9]], <2 x i32> <i32 0, i32 3>
211 ; CHECK-NEXT: [[TMP11:%.*]] = xor <2 x i32> [[TMP1]], [[TMP2]]
212 ; CHECK-NEXT: [[TMP12:%.*]] = xor <2 x i32> [[TMP6]], [[TMP7]]
213 ; CHECK-NEXT: [[TMP13:%.*]] = add <2 x i32> [[TMP5]], [[TMP10]]
214 ; CHECK-NEXT: [[TMP14:%.*]] = add <2 x i32> [[TMP11]], [[TMP12]]
215 ; CHECK-NEXT: [[TMP3_3:%.*]] = shufflevector <2 x i32> [[TMP13]], <2 x i32> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
216 ; CHECK-NEXT: ret <4 x i32> [[TMP3_3]]
218 %v0.0 = extractelement <2 x i32> %v0, i32 0
219 %v0.1 = extractelement <2 x i32> %v0, i32 1
220 %v1.0 = extractelement <2 x i32> %v1, i32 0
221 %v1.1 = extractelement <2 x i32> %v1, i32 1
222 %tmp0.0 = add i32 %v0.0, %v1.0
223 %tmp0.1 = add i32 %v0.1, %v1.1
224 %tmp0.2 = xor i32 %v0.0, %v1.0
225 %tmp0.3 = xor i32 %v0.1, %v1.1
226 %tmp1.0 = mul i32 %v0.0, %v1.0
227 %tmp1.1 = mul i32 %v0.1, %v1.1
228 %tmp1.2 = xor i32 %v0.0, %v1.0
229 %tmp1.3 = xor i32 %v0.1, %v1.1
230 %tmp2.0 = add i32 %tmp0.0, %tmp0.1
231 %tmp2.1 = add i32 %tmp1.0, %tmp1.1
232 %tmp2.2 = add i32 %tmp0.2, %tmp0.3
233 %tmp2.3 = add i32 %tmp1.2, %tmp1.3
234 %tmp3.0 = insertelement <4 x i32> undef, i32 %tmp2.0, i32 0
235 %tmp3.1 = insertelement <4 x i32> %tmp3.0, i32 %tmp2.1, i32 1
236 %tmp3.2 = insertelement <4 x i32> %tmp3.1, i32 %tmp2.2, i32 2
237 %tmp3.3 = insertelement <4 x i32> %tmp3.2, i32 %tmp2.3, i32 3
238 ret <4 x i32> %tmp3.3
241 define i32 @reduction_v4i32(<4 x i32> %v0, <4 x i32> %v1) {
242 ; CHECK-LABEL: @reduction_v4i32(
243 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[V0:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 2>
244 ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
245 ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[V1:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 2>
246 ; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
247 ; CHECK-NEXT: [[TMP3:%.*]] = sub <4 x i32> [[SHUFFLE]], [[SHUFFLE1]]
248 ; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> [[SHUFFLE]], [[SHUFFLE1]]
249 ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
250 ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[V0]], <4 x i32> undef, <2 x i32> <i32 1, i32 3>
251 ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <2 x i32> [[TMP6]], <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
252 ; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[V1]], <4 x i32> undef, <2 x i32> <i32 1, i32 3>
253 ; CHECK-NEXT: [[SHUFFLE3:%.*]] = shufflevector <2 x i32> [[TMP7]], <2 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
254 ; CHECK-NEXT: [[TMP8:%.*]] = sub <4 x i32> [[SHUFFLE2]], [[SHUFFLE3]]
255 ; CHECK-NEXT: [[TMP9:%.*]] = add <4 x i32> [[SHUFFLE2]], [[SHUFFLE3]]
256 ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> [[TMP9]], <4 x i32> <i32 0, i32 5, i32 6, i32 3>
257 ; CHECK-NEXT: [[TMP11:%.*]] = add <4 x i32> [[TMP5]], [[TMP10]]
258 ; CHECK-NEXT: [[TMP12:%.*]] = lshr <4 x i32> [[TMP11]], <i32 15, i32 15, i32 15, i32 15>
259 ; CHECK-NEXT: [[TMP13:%.*]] = and <4 x i32> [[TMP12]], <i32 65537, i32 65537, i32 65537, i32 65537>
260 ; CHECK-NEXT: [[TMP14:%.*]] = mul nuw <4 x i32> [[TMP13]], <i32 65535, i32 65535, i32 65535, i32 65535>
261 ; CHECK-NEXT: [[TMP15:%.*]] = add <4 x i32> [[TMP14]], [[TMP11]]
262 ; CHECK-NEXT: [[TMP16:%.*]] = xor <4 x i32> [[TMP15]], [[TMP14]]
263 ; CHECK-NEXT: [[TMP17:%.*]] = call i32 @llvm.experimental.vector.reduce.add.v4i32(<4 x i32> [[TMP16]])
264 ; CHECK-NEXT: ret i32 [[TMP17]]
266 %v0.0 = extractelement <4 x i32> %v0, i32 0
267 %v0.1 = extractelement <4 x i32> %v0, i32 1
268 %v0.2 = extractelement <4 x i32> %v0, i32 2
269 %v0.3 = extractelement <4 x i32> %v0, i32 3
270 %v1.0 = extractelement <4 x i32> %v1, i32 0
271 %v1.1 = extractelement <4 x i32> %v1, i32 1
272 %v1.2 = extractelement <4 x i32> %v1, i32 2
273 %v1.3 = extractelement <4 x i32> %v1, i32 3
274 %tmp0.0 = add i32 %v0.0, %v1.0
275 %tmp0.1 = add i32 %v0.1, %v1.1
276 %tmp0.2 = add i32 %v0.2, %v1.2
277 %tmp0.3 = add i32 %v0.3, %v1.3
278 %tmp1.0 = sub i32 %v0.0, %v1.0
279 %tmp1.1 = sub i32 %v0.1, %v1.1
280 %tmp1.2 = sub i32 %v0.2, %v1.2
281 %tmp1.3 = sub i32 %v0.3, %v1.3
282 %tmp2.0 = add i32 %tmp0.0, %tmp0.1
283 %tmp2.1 = add i32 %tmp1.0, %tmp1.1
284 %tmp2.2 = add i32 %tmp0.2, %tmp0.3
285 %tmp2.3 = add i32 %tmp1.2, %tmp1.3
286 %tmp3.0 = lshr i32 %tmp2.0, 15
287 %tmp3.1 = lshr i32 %tmp2.1, 15
288 %tmp3.2 = lshr i32 %tmp2.2, 15
289 %tmp3.3 = lshr i32 %tmp2.3, 15
290 %tmp4.0 = and i32 %tmp3.0, 65537
291 %tmp4.1 = and i32 %tmp3.1, 65537
292 %tmp4.2 = and i32 %tmp3.2, 65537
293 %tmp4.3 = and i32 %tmp3.3, 65537
294 %tmp5.0 = mul nuw i32 %tmp4.0, 65535
295 %tmp5.1 = mul nuw i32 %tmp4.1, 65535
296 %tmp5.2 = mul nuw i32 %tmp4.2, 65535
297 %tmp5.3 = mul nuw i32 %tmp4.3, 65535
298 %tmp6.0 = add i32 %tmp5.0, %tmp2.0
299 %tmp6.1 = add i32 %tmp5.1, %tmp2.1
300 %tmp6.2 = add i32 %tmp5.2, %tmp2.2
301 %tmp6.3 = add i32 %tmp5.3, %tmp2.3
302 %tmp7.0 = xor i32 %tmp6.0, %tmp5.0
303 %tmp7.1 = xor i32 %tmp6.1, %tmp5.1
304 %tmp7.2 = xor i32 %tmp6.2, %tmp5.2
305 %tmp7.3 = xor i32 %tmp6.3, %tmp5.3
306 %reduce.0 = add i32 %tmp7.1, %tmp7.0
307 %reduce.1 = add i32 %reduce.0, %tmp7.2
308 %reduce.2 = add i32 %reduce.1, %tmp7.3