1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 -instruction-tables < %s | FileCheck %s
7 # CHECK: Instruction Info:
8 # CHECK-NEXT: [1]: #uOps
9 # CHECK-NEXT: [2]: Latency
10 # CHECK-NEXT: [3]: RThroughput
11 # CHECK-NEXT: [4]: MayLoad
12 # CHECK-NEXT: [5]: MayStore
13 # CHECK-NEXT: [6]: HasSideEffects (U)
15 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
16 # CHECK-NEXT: 1 5 0.50 * * prefetch (%rax)
17 # CHECK-NEXT: 1 5 0.50 * * prefetchw (%rax)
20 # CHECK-NEXT: [0] - SKXDivider
21 # CHECK-NEXT: [1] - SKXFPDivider
22 # CHECK-NEXT: [2] - SKXPort0
23 # CHECK-NEXT: [3] - SKXPort1
24 # CHECK-NEXT: [4] - SKXPort2
25 # CHECK-NEXT: [5] - SKXPort3
26 # CHECK-NEXT: [6] - SKXPort4
27 # CHECK-NEXT: [7] - SKXPort5
28 # CHECK-NEXT: [8] - SKXPort6
29 # CHECK-NEXT: [9] - SKXPort7
31 # CHECK: Resource pressure per iteration:
32 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
33 # CHECK-NEXT: - - - - 1.00 1.00 - - - -
35 # CHECK: Resource pressure by instruction:
36 # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
37 # CHECK-NEXT: - - - - 0.50 0.50 - - - - prefetch (%rax)
38 # CHECK-NEXT: - - - - 0.50 0.50 - - - - prefetchw (%rax)