1 ; RUN: llc -mtriple=arm -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | grep -v "Verify generated machine code" | FileCheck %s
5 ; CHECK: ModulePass Manager
6 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
7 ; CHECK-NEXT: FunctionPass Manager
8 ; CHECK-NEXT: Expand Atomic instructions
9 ; CHECK-NEXT: Simplify the CFG
10 ; CHECK-NEXT: Dominator Tree Construction
11 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
12 ; CHECK-NEXT: Module Verifier
13 ; CHECK-NEXT: Natural Loop Information
14 ; CHECK-NEXT: Canonicalize natural loops
15 ; CHECK-NEXT: Scalar Evolution Analysis
16 ; CHECK-NEXT: Loop Pass Manager
17 ; CHECK-NEXT: Induction Variable Users
18 ; CHECK-NEXT: Loop Strength Reduction
19 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
20 ; CHECK-NEXT: Function Alias Analysis Results
21 ; CHECK-NEXT: Merge contiguous icmps into a memcmp
22 ; CHECK-NEXT: Expand memcmp() to load/stores
23 ; CHECK-NEXT: Lower Garbage Collection Instructions
24 ; CHECK-NEXT: Shadow Stack GC Lowering
25 ; CHECK-NEXT: Remove unreachable blocks from the CFG
26 ; CHECK-NEXT: Dominator Tree Construction
27 ; CHECK-NEXT: Natural Loop Information
28 ; CHECK-NEXT: Branch Probability Analysis
29 ; CHECK-NEXT: Block Frequency Analysis
30 ; CHECK-NEXT: Constant Hoisting
31 ; CHECK-NEXT: Partially inline calls to library functions
32 ; CHECK-NEXT: Instrument function entry/exit with calls to e.g. mcount() (post inlining)
33 ; CHECK-NEXT: Scalarize Masked Memory Intrinsics
34 ; CHECK-NEXT: Expand reduction intrinsics
35 ; CHECK-NEXT: Dominator Tree Construction
36 ; CHECK-NEXT: Natural Loop Information
37 ; CHECK-NEXT: Scalar Evolution Analysis
38 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
39 ; CHECK-NEXT: Function Alias Analysis Results
40 ; CHECK-NEXT: Loop Pass Manager
41 ; CHECK-NEXT: Transform loops to use DSP intrinsics
42 ; CHECK-NEXT: Interleaved Access Pass
43 ; CHECK-NEXT: ARM IR optimizations
44 ; CHECK-NEXT: Dominator Tree Construction
45 ; CHECK-NEXT: Natural Loop Information
46 ; CHECK-NEXT: CodeGen Prepare
47 ; CHECK-NEXT: Rewrite Symbols
48 ; CHECK-NEXT: FunctionPass Manager
49 ; CHECK-NEXT: Dominator Tree Construction
50 ; CHECK-NEXT: Exception handling preparation
51 ; CHECK-NEXT: Merge internal globals
52 ; CHECK-NEXT: Dominator Tree Construction
53 ; CHECK-NEXT: Natural Loop Information
54 ; CHECK-NEXT: Scalar Evolution Analysis
55 ; CHECK-NEXT: Hardware Loop Insertion
56 ; CHECK-NEXT: Safe Stack instrumentation pass
57 ; CHECK-NEXT: Insert stack protectors
58 ; CHECK-NEXT: Module Verifier
59 ; CHECK-NEXT: Dominator Tree Construction
60 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
61 ; CHECK-NEXT: Function Alias Analysis Results
62 ; CHECK-NEXT: Natural Loop Information
63 ; CHECK-NEXT: Branch Probability Analysis
64 ; CHECK-NEXT: ARM Instruction Selection
65 ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
66 ; CHECK-NEXT: Early Tail Duplication
67 ; CHECK-NEXT: Optimize machine instruction PHIs
68 ; CHECK-NEXT: Slot index numbering
69 ; CHECK-NEXT: Merge disjoint stack slots
70 ; CHECK-NEXT: Local Stack Slot Allocation
71 ; CHECK-NEXT: Remove dead machine instructions
72 ; CHECK-NEXT: MachineDominator Tree Construction
73 ; CHECK-NEXT: Machine Natural Loop Construction
74 ; CHECK-NEXT: Early Machine Loop Invariant Code Motion
75 ; CHECK-NEXT: Machine Common Subexpression Elimination
76 ; CHECK-NEXT: MachinePostDominator Tree Construction
77 ; CHECK-NEXT: Machine Block Frequency Analysis
78 ; CHECK-NEXT: Machine code sinking
79 ; CHECK-NEXT: Peephole Optimizations
80 ; CHECK-NEXT: Remove dead machine instructions
81 ; CHECK-NEXT: ARM MLA / MLS expansion pass
82 ; CHECK-NEXT: ARM pre- register allocation load / store optimization pass
83 ; CHECK-NEXT: ARM A15 S->D optimizer
84 ; CHECK-NEXT: Detect Dead Lanes
85 ; CHECK-NEXT: Process Implicit Definitions
86 ; CHECK-NEXT: Remove unreachable machine basic blocks
87 ; CHECK-NEXT: Live Variable Analysis
88 ; CHECK-NEXT: MachineDominator Tree Construction
89 ; CHECK-NEXT: Machine Natural Loop Construction
90 ; CHECK-NEXT: Eliminate PHI nodes for register allocation
91 ; CHECK-NEXT: Two-Address instruction pass
92 ; CHECK-NEXT: Slot index numbering
93 ; CHECK-NEXT: Live Interval Analysis
94 ; CHECK-NEXT: Simple Register Coalescing
95 ; CHECK-NEXT: Rename Disconnected Subregister Components
96 ; CHECK-NEXT: Machine Instruction Scheduler
97 ; CHECK-NEXT: Machine Block Frequency Analysis
98 ; CHECK-NEXT: Debug Variable Analysis
99 ; CHECK-NEXT: Live Stack Slot Analysis
100 ; CHECK-NEXT: Virtual Register Map
101 ; CHECK-NEXT: Live Register Matrix
102 ; CHECK-NEXT: Bundle Machine CFG Edges
103 ; CHECK-NEXT: Spill Code Placement Analysis
104 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
105 ; CHECK-NEXT: Machine Optimization Remark Emitter
106 ; CHECK-NEXT: Greedy Register Allocator
107 ; CHECK-NEXT: Virtual Register Rewriter
108 ; CHECK-NEXT: Stack Slot Coloring
109 ; CHECK-NEXT: Machine Copy Propagation Pass
110 ; CHECK-NEXT: Machine Loop Invariant Code Motion
111 ; CHECK-NEXT: PostRA Machine Sink
112 ; CHECK-NEXT: Machine Block Frequency Analysis
113 ; CHECK-NEXT: MachinePostDominator Tree Construction
114 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
115 ; CHECK-NEXT: Machine Optimization Remark Emitter
116 ; CHECK-NEXT: Shrink Wrapping analysis
117 ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
118 ; CHECK-NEXT: Control Flow Optimizer
119 ; CHECK-NEXT: Tail Duplication
120 ; CHECK-NEXT: Machine Copy Propagation Pass
121 ; CHECK-NEXT: Post-RA pseudo instruction expansion pass
122 ; CHECK-NEXT: ARM load / store optimization pass
123 ; CHECK-NEXT: ReachingDefAnalysis
124 ; CHECK-NEXT: ARM Execution Domain Fix
125 ; CHECK-NEXT: BreakFalseDeps
126 ; CHECK-NEXT: ARM pseudo instruction expansion pass
127 ; CHECK-NEXT: Thumb2 instruction size reduce pass
128 ; CHECK-NEXT: MachineDominator Tree Construction
129 ; CHECK-NEXT: Machine Natural Loop Construction
130 ; CHECK-NEXT: Machine Block Frequency Analysis
131 ; CHECK-NEXT: If Converter
132 ; CHECK-NEXT: MVE VPT block insertion pass
133 ; CHECK-NEXT: Thumb IT blocks insertion pass
134 ; CHECK-NEXT: MachineDominator Tree Construction
135 ; CHECK-NEXT: Machine Natural Loop Construction
136 ; CHECK-NEXT: Post RA top-down list latency scheduler
137 ; CHECK-NEXT: Analyze Machine Code For Garbage Collection
138 ; CHECK-NEXT: Machine Block Frequency Analysis
139 ; CHECK-NEXT: MachinePostDominator Tree Construction
140 ; CHECK-NEXT: Branch Probability Basic Block Placement
141 ; CHECK-NEXT: Thumb2 instruction size reduce pass
142 ; CHECK-NEXT: Unpack machine instruction bundles
143 ; CHECK-NEXT: optimise barriers pass
144 ; CHECK-NEXT: ARM constant island placement and branch shortening pass
145 ; CHECK-NEXT: MachineDominator Tree Construction
146 ; CHECK-NEXT: Machine Natural Loop Construction
147 ; CHECK-NEXT: ARM Low Overhead Loops pass
148 ; CHECK-NEXT: Contiguously Lay Out Funclets
149 ; CHECK-NEXT: StackMap Liveness Analysis
150 ; CHECK-NEXT: Live DEBUG_VALUE analysis
151 ; CHECK-NEXT: Insert fentry calls
152 ; CHECK-NEXT: Insert XRay ops
153 ; CHECK-NEXT: Implement the 'patchable-function' attribute
154 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
155 ; CHECK-NEXT: Machine Optimization Remark Emitter
156 ; CHECK-NEXT: ARM Assembly Printer
157 ; CHECK-NEXT: Free MachineFunction