| blob | 77414929970cf76288640fe54e6a1f0de0b6b8fb |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=armv6 < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM6
3 ; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM78,ARM7
4 ; RUN: llc -mtriple=armv8a < %s | FileCheck %s --check-prefixes=CHECK,ARM,ARM78,ARM8
5 ; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB6
6 ; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB78,THUMB7
7 ; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=CHECK,THUMB,THUMB78,THUMB8
9 ; We are looking for the following pattern here:
10 ; (X & (C l>> Y)) ==/!= 0
11 ; It may be optimal to hoist the constant:
12 ; ((X << Y) & C) ==/!= 0
14 ;------------------------------------------------------------------------------;
15 ; A few scalar test
16 ;------------------------------------------------------------------------------;
18 ; i8 scalar
20 define i1 @scalar_i8_signbit_eq(i8 %x, i8 %y) nounwind {
21 ; ARM-LABEL: scalar_i8_signbit_eq:
22 ; ARM: @ %bb.0:
23 ; ARM-NEXT: uxtb r1, r1
24 ; ARM-NEXT: mov r2, #128
25 ; ARM-NEXT: and r0, r0, r2, lsr r1
26 ; ARM-NEXT: uxtb r0, r0
27 ; ARM-NEXT: clz r0, r0
28 ; ARM-NEXT: lsr r0, r0, #5
29 ; ARM-NEXT: bx lr
30 ;
31 ; THUMB6-LABEL: scalar_i8_signbit_eq:
32 ; THUMB6: @ %bb.0:
33 ; THUMB6-NEXT: uxtb r1, r1
34 ; THUMB6-NEXT: movs r2, #128
35 ; THUMB6-NEXT: lsrs r2, r1
36 ; THUMB6-NEXT: ands r2, r0
37 ; THUMB6-NEXT: uxtb r1, r2
38 ; THUMB6-NEXT: rsbs r0, r1, #0
39 ; THUMB6-NEXT: adcs r0, r1
40 ; THUMB6-NEXT: bx lr
41 ;
42 ; THUMB78-LABEL: scalar_i8_signbit_eq:
43 ; THUMB78: @ %bb.0:
44 ; THUMB78-NEXT: uxtb r1, r1
45 ; THUMB78-NEXT: movs r2, #128
46 ; THUMB78-NEXT: lsr.w r1, r2, r1
47 ; THUMB78-NEXT: ands r0, r1
48 ; THUMB78-NEXT: uxtb r0, r0
49 ; THUMB78-NEXT: clz r0, r0
50 ; THUMB78-NEXT: lsrs r0, r0, #5
51 ; THUMB78-NEXT: bx lr
52 %t0 = lshr i8 128, %y
53 %t1 = and i8 %t0, %x
54 %res = icmp eq i8 %t1, 0
55 ret i1 %res
56 }
58 define i1 @scalar_i8_lowestbit_eq(i8 %x, i8 %y) nounwind {
59 ; ARM-LABEL: scalar_i8_lowestbit_eq:
60 ; ARM: @ %bb.0:
61 ; ARM-NEXT: uxtb r1, r1
62 ; ARM-NEXT: mov r2, #1
63 ; ARM-NEXT: and r0, r0, r2, lsr r1
64 ; ARM-NEXT: uxtb r0, r0
65 ; ARM-NEXT: clz r0, r0
66 ; ARM-NEXT: lsr r0, r0, #5
67 ; ARM-NEXT: bx lr
68 ;
69 ; THUMB6-LABEL: scalar_i8_lowestbit_eq:
70 ; THUMB6: @ %bb.0:
71 ; THUMB6-NEXT: uxtb r1, r1
72 ; THUMB6-NEXT: movs r2, #1
73 ; THUMB6-NEXT: lsrs r2, r1
74 ; THUMB6-NEXT: ands r2, r0
75 ; THUMB6-NEXT: uxtb r1, r2
76 ; THUMB6-NEXT: rsbs r0, r1, #0
77 ; THUMB6-NEXT: adcs r0, r1
78 ; THUMB6-NEXT: bx lr
79 ;
80 ; THUMB78-LABEL: scalar_i8_lowestbit_eq:
81 ; THUMB78: @ %bb.0:
82 ; THUMB78-NEXT: uxtb r1, r1
83 ; THUMB78-NEXT: movs r2, #1
84 ; THUMB78-NEXT: lsr.w r1, r2, r1
85 ; THUMB78-NEXT: ands r0, r1
86 ; THUMB78-NEXT: uxtb r0, r0
87 ; THUMB78-NEXT: clz r0, r0
88 ; THUMB78-NEXT: lsrs r0, r0, #5
89 ; THUMB78-NEXT: bx lr
90 %t0 = lshr i8 1, %y
91 %t1 = and i8 %t0, %x
92 %res = icmp eq i8 %t1, 0
93 ret i1 %res
94 }
96 define i1 @scalar_i8_bitsinmiddle_eq(i8 %x, i8 %y) nounwind {
97 ; ARM-LABEL: scalar_i8_bitsinmiddle_eq:
98 ; ARM: @ %bb.0:
99 ; ARM-NEXT: uxtb r1, r1
100 ; ARM-NEXT: mov r2, #24
101 ; ARM-NEXT: and r0, r0, r2, lsr r1
102 ; ARM-NEXT: uxtb r0, r0
103 ; ARM-NEXT: clz r0, r0
104 ; ARM-NEXT: lsr r0, r0, #5
105 ; ARM-NEXT: bx lr
106 ;
107 ; THUMB6-LABEL: scalar_i8_bitsinmiddle_eq:
108 ; THUMB6: @ %bb.0:
109 ; THUMB6-NEXT: uxtb r1, r1
110 ; THUMB6-NEXT: movs r2, #24
111 ; THUMB6-NEXT: lsrs r2, r1
112 ; THUMB6-NEXT: ands r2, r0
113 ; THUMB6-NEXT: uxtb r1, r2
114 ; THUMB6-NEXT: rsbs r0, r1, #0
115 ; THUMB6-NEXT: adcs r0, r1
116 ; THUMB6-NEXT: bx lr
117 ;
118 ; THUMB78-LABEL: scalar_i8_bitsinmiddle_eq:
119 ; THUMB78: @ %bb.0:
120 ; THUMB78-NEXT: uxtb r1, r1
121 ; THUMB78-NEXT: movs r2, #24
122 ; THUMB78-NEXT: lsr.w r1, r2, r1
123 ; THUMB78-NEXT: ands r0, r1
124 ; THUMB78-NEXT: uxtb r0, r0
125 ; THUMB78-NEXT: clz r0, r0
126 ; THUMB78-NEXT: lsrs r0, r0, #5
127 ; THUMB78-NEXT: bx lr
128 %t0 = lshr i8 24, %y
129 %t1 = and i8 %t0, %x
130 %res = icmp eq i8 %t1, 0
131 ret i1 %res
132 }
134 ; i16 scalar
136 define i1 @scalar_i16_signbit_eq(i16 %x, i16 %y) nounwind {
137 ; ARM-LABEL: scalar_i16_signbit_eq:
138 ; ARM: @ %bb.0:
139 ; ARM-NEXT: uxth r1, r1
140 ; ARM-NEXT: mov r2, #32768
141 ; ARM-NEXT: and r0, r0, r2, lsr r1
142 ; ARM-NEXT: uxth r0, r0
143 ; ARM-NEXT: clz r0, r0
144 ; ARM-NEXT: lsr r0, r0, #5
145 ; ARM-NEXT: bx lr
146 ;
147 ; THUMB6-LABEL: scalar_i16_signbit_eq:
148 ; THUMB6: @ %bb.0:
149 ; THUMB6-NEXT: uxth r1, r1
150 ; THUMB6-NEXT: movs r2, #1
151 ; THUMB6-NEXT: lsls r2, r2, #15
152 ; THUMB6-NEXT: lsrs r2, r1
153 ; THUMB6-NEXT: ands r2, r0
154 ; THUMB6-NEXT: uxth r1, r2
155 ; THUMB6-NEXT: rsbs r0, r1, #0
156 ; THUMB6-NEXT: adcs r0, r1
157 ; THUMB6-NEXT: bx lr
158 ;
159 ; THUMB78-LABEL: scalar_i16_signbit_eq:
160 ; THUMB78: @ %bb.0:
161 ; THUMB78-NEXT: uxth r1, r1
162 ; THUMB78-NEXT: mov.w r2, #32768
163 ; THUMB78-NEXT: lsr.w r1, r2, r1
164 ; THUMB78-NEXT: ands r0, r1
165 ; THUMB78-NEXT: uxth r0, r0
166 ; THUMB78-NEXT: clz r0, r0
167 ; THUMB78-NEXT: lsrs r0, r0, #5
168 ; THUMB78-NEXT: bx lr
169 %t0 = lshr i16 32768, %y
170 %t1 = and i16 %t0, %x
171 %res = icmp eq i16 %t1, 0
172 ret i1 %res
173 }
175 define i1 @scalar_i16_lowestbit_eq(i16 %x, i16 %y) nounwind {
176 ; ARM-LABEL: scalar_i16_lowestbit_eq:
177 ; ARM: @ %bb.0:
178 ; ARM-NEXT: uxth r1, r1
179 ; ARM-NEXT: mov r2, #1
180 ; ARM-NEXT: and r0, r0, r2, lsr r1
181 ; ARM-NEXT: uxth r0, r0
182 ; ARM-NEXT: clz r0, r0
183 ; ARM-NEXT: lsr r0, r0, #5
184 ; ARM-NEXT: bx lr
185 ;
186 ; THUMB6-LABEL: scalar_i16_lowestbit_eq:
187 ; THUMB6: @ %bb.0:
188 ; THUMB6-NEXT: uxth r1, r1
189 ; THUMB6-NEXT: movs r2, #1
190 ; THUMB6-NEXT: lsrs r2, r1
191 ; THUMB6-NEXT: ands r2, r0
192 ; THUMB6-NEXT: uxth r1, r2
193 ; THUMB6-NEXT: rsbs r0, r1, #0
194 ; THUMB6-NEXT: adcs r0, r1
195 ; THUMB6-NEXT: bx lr
196 ;
197 ; THUMB78-LABEL: scalar_i16_lowestbit_eq:
198 ; THUMB78: @ %bb.0:
199 ; THUMB78-NEXT: uxth r1, r1
200 ; THUMB78-NEXT: movs r2, #1
201 ; THUMB78-NEXT: lsr.w r1, r2, r1
202 ; THUMB78-NEXT: ands r0, r1
203 ; THUMB78-NEXT: uxth r0, r0
204 ; THUMB78-NEXT: clz r0, r0
205 ; THUMB78-NEXT: lsrs r0, r0, #5
206 ; THUMB78-NEXT: bx lr
207 %t0 = lshr i16 1, %y
208 %t1 = and i16 %t0, %x
209 %res = icmp eq i16 %t1, 0
210 ret i1 %res
211 }
213 define i1 @scalar_i16_bitsinmiddle_eq(i16 %x, i16 %y) nounwind {
214 ; ARM-LABEL: scalar_i16_bitsinmiddle_eq:
215 ; ARM: @ %bb.0:
216 ; ARM-NEXT: uxth r1, r1
217 ; ARM-NEXT: mov r2, #4080
218 ; ARM-NEXT: and r0, r0, r2, lsr r1
219 ; ARM-NEXT: uxth r0, r0
220 ; ARM-NEXT: clz r0, r0
221 ; ARM-NEXT: lsr r0, r0, #5
222 ; ARM-NEXT: bx lr
223 ;
224 ; THUMB6-LABEL: scalar_i16_bitsinmiddle_eq:
225 ; THUMB6: @ %bb.0:
226 ; THUMB6-NEXT: uxth r1, r1
227 ; THUMB6-NEXT: movs r2, #255
228 ; THUMB6-NEXT: lsls r2, r2, #4
229 ; THUMB6-NEXT: lsrs r2, r1
230 ; THUMB6-NEXT: ands r2, r0
231 ; THUMB6-NEXT: uxth r1, r2
232 ; THUMB6-NEXT: rsbs r0, r1, #0
233 ; THUMB6-NEXT: adcs r0, r1
234 ; THUMB6-NEXT: bx lr
235 ;
236 ; THUMB78-LABEL: scalar_i16_bitsinmiddle_eq:
237 ; THUMB78: @ %bb.0:
238 ; THUMB78-NEXT: uxth r1, r1
239 ; THUMB78-NEXT: mov.w r2, #4080
240 ; THUMB78-NEXT: lsr.w r1, r2, r1
241 ; THUMB78-NEXT: ands r0, r1
242 ; THUMB78-NEXT: uxth r0, r0
243 ; THUMB78-NEXT: clz r0, r0
244 ; THUMB78-NEXT: lsrs r0, r0, #5
245 ; THUMB78-NEXT: bx lr
246 %t0 = lshr i16 4080, %y
247 %t1 = and i16 %t0, %x
248 %res = icmp eq i16 %t1, 0
249 ret i1 %res
250 }
252 ; i32 scalar
254 define i1 @scalar_i32_signbit_eq(i32 %x, i32 %y) nounwind {
255 ; ARM-LABEL: scalar_i32_signbit_eq:
256 ; ARM: @ %bb.0:
257 ; ARM-NEXT: mov r2, #-2147483648
258 ; ARM-NEXT: and r0, r0, r2, lsr r1
259 ; ARM-NEXT: clz r0, r0
260 ; ARM-NEXT: lsr r0, r0, #5
261 ; ARM-NEXT: bx lr
262 ;
263 ; THUMB6-LABEL: scalar_i32_signbit_eq:
264 ; THUMB6: @ %bb.0:
265 ; THUMB6-NEXT: movs r2, #1
266 ; THUMB6-NEXT: lsls r2, r2, #31
267 ; THUMB6-NEXT: lsrs r2, r1
268 ; THUMB6-NEXT: ands r2, r0
269 ; THUMB6-NEXT: rsbs r0, r2, #0
270 ; THUMB6-NEXT: adcs r0, r2
271 ; THUMB6-NEXT: bx lr
272 ;
273 ; THUMB78-LABEL: scalar_i32_signbit_eq:
274 ; THUMB78: @ %bb.0:
275 ; THUMB78-NEXT: mov.w r2, #-2147483648
276 ; THUMB78-NEXT: lsr.w r1, r2, r1
277 ; THUMB78-NEXT: ands r0, r1
278 ; THUMB78-NEXT: clz r0, r0
279 ; THUMB78-NEXT: lsrs r0, r0, #5
280 ; THUMB78-NEXT: bx lr
281 %t0 = lshr i32 2147483648, %y
282 %t1 = and i32 %t0, %x
283 %res = icmp eq i32 %t1, 0
284 ret i1 %res
285 }
287 define i1 @scalar_i32_lowestbit_eq(i32 %x, i32 %y) nounwind {
288 ; ARM-LABEL: scalar_i32_lowestbit_eq:
289 ; ARM: @ %bb.0:
290 ; ARM-NEXT: mov r2, #1
291 ; ARM-NEXT: and r0, r0, r2, lsr r1
292 ; ARM-NEXT: clz r0, r0
293 ; ARM-NEXT: lsr r0, r0, #5
294 ; ARM-NEXT: bx lr
295 ;
296 ; THUMB6-LABEL: scalar_i32_lowestbit_eq:
297 ; THUMB6: @ %bb.0:
298 ; THUMB6-NEXT: movs r2, #1
299 ; THUMB6-NEXT: lsrs r2, r1
300 ; THUMB6-NEXT: ands r2, r0
301 ; THUMB6-NEXT: rsbs r0, r2, #0
302 ; THUMB6-NEXT: adcs r0, r2
303 ; THUMB6-NEXT: bx lr
304 ;
305 ; THUMB78-LABEL: scalar_i32_lowestbit_eq:
306 ; THUMB78: @ %bb.0:
307 ; THUMB78-NEXT: movs r2, #1
308 ; THUMB78-NEXT: lsr.w r1, r2, r1
309 ; THUMB78-NEXT: ands r0, r1
310 ; THUMB78-NEXT: clz r0, r0
311 ; THUMB78-NEXT: lsrs r0, r0, #5
312 ; THUMB78-NEXT: bx lr
313 %t0 = lshr i32 1, %y
314 %t1 = and i32 %t0, %x
315 %res = icmp eq i32 %t1, 0
316 ret i1 %res
317 }
319 define i1 @scalar_i32_bitsinmiddle_eq(i32 %x, i32 %y) nounwind {
320 ; ARM6-LABEL: scalar_i32_bitsinmiddle_eq:
321 ; ARM6: @ %bb.0:
322 ; ARM6-NEXT: mov r2, #65280
323 ; ARM6-NEXT: orr r2, r2, #16711680
324 ; ARM6-NEXT: and r0, r0, r2, lsr r1
325 ; ARM6-NEXT: clz r0, r0
326 ; ARM6-NEXT: lsr r0, r0, #5
327 ; ARM6-NEXT: bx lr
328 ;
329 ; ARM78-LABEL: scalar_i32_bitsinmiddle_eq:
330 ; ARM78: @ %bb.0:
331 ; ARM78-NEXT: movw r2, #65280
332 ; ARM78-NEXT: movt r2, #255
333 ; ARM78-NEXT: and r0, r0, r2, lsr r1
334 ; ARM78-NEXT: clz r0, r0
335 ; ARM78-NEXT: lsr r0, r0, #5
336 ; ARM78-NEXT: bx lr
337 ;
338 ; THUMB6-LABEL: scalar_i32_bitsinmiddle_eq:
339 ; THUMB6: @ %bb.0:
340 ; THUMB6-NEXT: ldr r2, .LCPI8_0
341 ; THUMB6-NEXT: lsrs r2, r1
342 ; THUMB6-NEXT: ands r2, r0
343 ; THUMB6-NEXT: rsbs r0, r2, #0
344 ; THUMB6-NEXT: adcs r0, r2
345 ; THUMB6-NEXT: bx lr
346 ; THUMB6-NEXT: .p2align 2
347 ; THUMB6-NEXT: @ %bb.1:
348 ; THUMB6-NEXT: .LCPI8_0:
349 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
350 ;
351 ; THUMB78-LABEL: scalar_i32_bitsinmiddle_eq:
352 ; THUMB78: @ %bb.0:
353 ; THUMB78-NEXT: movw r2, #65280
354 ; THUMB78-NEXT: movt r2, #255
355 ; THUMB78-NEXT: lsr.w r1, r2, r1
356 ; THUMB78-NEXT: ands r0, r1
357 ; THUMB78-NEXT: clz r0, r0
358 ; THUMB78-NEXT: lsrs r0, r0, #5
359 ; THUMB78-NEXT: bx lr
360 %t0 = lshr i32 16776960, %y
361 %t1 = and i32 %t0, %x
362 %res = icmp eq i32 %t1, 0
363 ret i1 %res
364 }
366 ; i64 scalar
368 define i1 @scalar_i64_signbit_eq(i64 %x, i64 %y) nounwind {
369 ; ARM6-LABEL: scalar_i64_signbit_eq:
370 ; ARM6: @ %bb.0:
371 ; ARM6-NEXT: push {r11, lr}
372 ; ARM6-NEXT: mov r12, #-2147483648
373 ; ARM6-NEXT: subs lr, r2, #32
374 ; ARM6-NEXT: lsr r3, r12, r2
375 ; ARM6-NEXT: rsb r2, r2, #32
376 ; ARM6-NEXT: movpl r3, #0
377 ; ARM6-NEXT: and r1, r3, r1
378 ; ARM6-NEXT: lsl r2, r12, r2
379 ; ARM6-NEXT: lsrpl r2, r12, lr
380 ; ARM6-NEXT: and r0, r2, r0
381 ; ARM6-NEXT: orr r0, r0, r1
382 ; ARM6-NEXT: clz r0, r0
383 ; ARM6-NEXT: lsr r0, r0, #5
384 ; ARM6-NEXT: pop {r11, pc}
385 ;
386 ; ARM78-LABEL: scalar_i64_signbit_eq:
387 ; ARM78: @ %bb.0:
388 ; ARM78-NEXT: push {r11, lr}
389 ; ARM78-NEXT: mov r12, #-2147483648
390 ; ARM78-NEXT: subs lr, r2, #32
391 ; ARM78-NEXT: lsr r3, r12, r2
392 ; ARM78-NEXT: rsb r2, r2, #32
393 ; ARM78-NEXT: movwpl r3, #0
394 ; ARM78-NEXT: and r1, r3, r1
395 ; ARM78-NEXT: lsl r2, r12, r2
396 ; ARM78-NEXT: lsrpl r2, r12, lr
397 ; ARM78-NEXT: and r0, r2, r0
398 ; ARM78-NEXT: orr r0, r0, r1
399 ; ARM78-NEXT: clz r0, r0
400 ; ARM78-NEXT: lsr r0, r0, #5
401 ; ARM78-NEXT: pop {r11, pc}
402 ;
403 ; THUMB6-LABEL: scalar_i64_signbit_eq:
404 ; THUMB6: @ %bb.0:
405 ; THUMB6-NEXT: push {r4, r5, r7, lr}
406 ; THUMB6-NEXT: mov r4, r1
407 ; THUMB6-NEXT: mov r5, r0
408 ; THUMB6-NEXT: movs r0, #1
409 ; THUMB6-NEXT: lsls r1, r0, #31
410 ; THUMB6-NEXT: movs r0, #0
411 ; THUMB6-NEXT: bl __lshrdi3
412 ; THUMB6-NEXT: ands r1, r4
413 ; THUMB6-NEXT: ands r0, r5
414 ; THUMB6-NEXT: orrs r0, r1
415 ; THUMB6-NEXT: rsbs r1, r0, #0
416 ; THUMB6-NEXT: adcs r0, r1
417 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
418 ;
419 ; THUMB7-LABEL: scalar_i64_signbit_eq:
420 ; THUMB7: @ %bb.0:
421 ; THUMB7-NEXT: push {r7, lr}
422 ; THUMB7-NEXT: rsb.w r3, r2, #32
423 ; THUMB7-NEXT: mov.w r12, #-2147483648
424 ; THUMB7-NEXT: subs.w lr, r2, #32
425 ; THUMB7-NEXT: lsr.w r2, r12, r2
426 ; THUMB7-NEXT: lsl.w r3, r12, r3
427 ; THUMB7-NEXT: it pl
428 ; THUMB7-NEXT: lsrpl.w r3, r12, lr
429 ; THUMB7-NEXT: it pl
430 ; THUMB7-NEXT: movpl r2, #0
431 ; THUMB7-NEXT: ands r0, r3
432 ; THUMB7-NEXT: ands r1, r2
433 ; THUMB7-NEXT: orrs r0, r1
434 ; THUMB7-NEXT: clz r0, r0
435 ; THUMB7-NEXT: lsrs r0, r0, #5
436 ; THUMB7-NEXT: pop {r7, pc}
437 ;
438 ; THUMB8-LABEL: scalar_i64_signbit_eq:
439 ; THUMB8: @ %bb.0:
440 ; THUMB8-NEXT: .save {r7, lr}
441 ; THUMB8-NEXT: push {r7, lr}
442 ; THUMB8-NEXT: subs.w r3, r2, #32
443 ; THUMB8-NEXT: mov.w r12, #-2147483648
444 ; THUMB8-NEXT: lsr.w lr, r12, r3
445 ; THUMB8-NEXT: rsb.w r3, r2, #32
446 ; THUMB8-NEXT: lsr.w r2, r12, r2
447 ; THUMB8-NEXT: lsl.w r3, r12, r3
448 ; THUMB8-NEXT: it pl
449 ; THUMB8-NEXT: movpl r3, lr
450 ; THUMB8-NEXT: it pl
451 ; THUMB8-NEXT: movpl r2, #0
452 ; THUMB8-NEXT: ands r0, r3
453 ; THUMB8-NEXT: ands r1, r2
454 ; THUMB8-NEXT: orrs r0, r1
455 ; THUMB8-NEXT: clz r0, r0
456 ; THUMB8-NEXT: lsrs r0, r0, #5
457 ; THUMB8-NEXT: pop {r7, pc}
458 %t0 = lshr i64 9223372036854775808, %y
459 %t1 = and i64 %t0, %x
460 %res = icmp eq i64 %t1, 0
461 ret i1 %res
462 }
464 define i1 @scalar_i64_lowestbit_eq(i64 %x, i64 %y) nounwind {
465 ; ARM6-LABEL: scalar_i64_lowestbit_eq:
466 ; ARM6: @ %bb.0:
467 ; ARM6-NEXT: mov r1, #1
468 ; ARM6-NEXT: lsr r1, r1, r2
469 ; ARM6-NEXT: subs r2, r2, #32
470 ; ARM6-NEXT: movpl r1, #0
471 ; ARM6-NEXT: and r0, r1, r0
472 ; ARM6-NEXT: clz r0, r0
473 ; ARM6-NEXT: lsr r0, r0, #5
474 ; ARM6-NEXT: bx lr
475 ;
476 ; ARM78-LABEL: scalar_i64_lowestbit_eq:
477 ; ARM78: @ %bb.0:
478 ; ARM78-NEXT: mov r1, #1
479 ; ARM78-NEXT: lsr r1, r1, r2
480 ; ARM78-NEXT: subs r2, r2, #32
481 ; ARM78-NEXT: movwpl r1, #0
482 ; ARM78-NEXT: and r0, r1, r0
483 ; ARM78-NEXT: clz r0, r0
484 ; ARM78-NEXT: lsr r0, r0, #5
485 ; ARM78-NEXT: bx lr
486 ;
487 ; THUMB6-LABEL: scalar_i64_lowestbit_eq:
488 ; THUMB6: @ %bb.0:
489 ; THUMB6-NEXT: push {r4, r5, r7, lr}
490 ; THUMB6-NEXT: mov r4, r1
491 ; THUMB6-NEXT: mov r5, r0
492 ; THUMB6-NEXT: movs r0, #1
493 ; THUMB6-NEXT: movs r1, #0
494 ; THUMB6-NEXT: bl __lshrdi3
495 ; THUMB6-NEXT: ands r1, r4
496 ; THUMB6-NEXT: ands r0, r5
497 ; THUMB6-NEXT: orrs r0, r1
498 ; THUMB6-NEXT: rsbs r1, r0, #0
499 ; THUMB6-NEXT: adcs r0, r1
500 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
501 ;
502 ; THUMB78-LABEL: scalar_i64_lowestbit_eq:
503 ; THUMB78: @ %bb.0:
504 ; THUMB78-NEXT: movs r1, #1
505 ; THUMB78-NEXT: lsrs r1, r2
506 ; THUMB78-NEXT: subs r2, #32
507 ; THUMB78-NEXT: it pl
508 ; THUMB78-NEXT: movpl r1, #0
509 ; THUMB78-NEXT: ands r0, r1
510 ; THUMB78-NEXT: clz r0, r0
511 ; THUMB78-NEXT: lsrs r0, r0, #5
512 ; THUMB78-NEXT: bx lr
513 %t0 = lshr i64 1, %y
514 %t1 = and i64 %t0, %x
515 %res = icmp eq i64 %t1, 0
516 ret i1 %res
517 }
519 define i1 @scalar_i64_bitsinmiddle_eq(i64 %x, i64 %y) nounwind {
520 ; ARM6-LABEL: scalar_i64_bitsinmiddle_eq:
521 ; ARM6: @ %bb.0:
522 ; ARM6-NEXT: push {r11, lr}
523 ; ARM6-NEXT: mov r12, #255
524 ; ARM6-NEXT: subs lr, r2, #32
525 ; ARM6-NEXT: orr r12, r12, #65280
526 ; ARM6-NEXT: lsr r3, r12, r2
527 ; ARM6-NEXT: movpl r3, #0
528 ; ARM6-NEXT: and r1, r3, r1
529 ; ARM6-NEXT: mov r3, #16711680
530 ; ARM6-NEXT: cmp lr, #0
531 ; ARM6-NEXT: orr r3, r3, #-16777216
532 ; ARM6-NEXT: lsr r3, r3, r2
533 ; ARM6-NEXT: rsb r2, r2, #32
534 ; ARM6-NEXT: orr r2, r3, r12, lsl r2
535 ; ARM6-NEXT: lsrpl r2, r12, lr
536 ; ARM6-NEXT: and r0, r2, r0
537 ; ARM6-NEXT: orr r0, r0, r1
538 ; ARM6-NEXT: clz r0, r0
539 ; ARM6-NEXT: lsr r0, r0, #5
540 ; ARM6-NEXT: pop {r11, pc}
541 ;
542 ; ARM78-LABEL: scalar_i64_bitsinmiddle_eq:
543 ; ARM78: @ %bb.0:
544 ; ARM78-NEXT: push {r11, lr}
545 ; ARM78-NEXT: movw r12, #65535
546 ; ARM78-NEXT: subs lr, r2, #32
547 ; ARM78-NEXT: lsr r3, r12, r2
548 ; ARM78-NEXT: movwpl r3, #0
549 ; ARM78-NEXT: and r1, r3, r1
550 ; ARM78-NEXT: movw r3, #0
551 ; ARM78-NEXT: cmp lr, #0
552 ; ARM78-NEXT: movt r3, #65535
553 ; ARM78-NEXT: lsr r3, r3, r2
554 ; ARM78-NEXT: rsb r2, r2, #32
555 ; ARM78-NEXT: orr r2, r3, r12, lsl r2
556 ; ARM78-NEXT: lsrpl r2, r12, lr
557 ; ARM78-NEXT: and r0, r2, r0
558 ; ARM78-NEXT: orr r0, r0, r1
559 ; ARM78-NEXT: clz r0, r0
560 ; ARM78-NEXT: lsr r0, r0, #5
561 ; ARM78-NEXT: pop {r11, pc}
562 ;
563 ; THUMB6-LABEL: scalar_i64_bitsinmiddle_eq:
564 ; THUMB6: @ %bb.0:
565 ; THUMB6-NEXT: push {r4, r5, r7, lr}
566 ; THUMB6-NEXT: mov r4, r1
567 ; THUMB6-NEXT: mov r5, r0
568 ; THUMB6-NEXT: ldr r0, .LCPI11_0
569 ; THUMB6-NEXT: ldr r1, .LCPI11_1
570 ; THUMB6-NEXT: bl __lshrdi3
571 ; THUMB6-NEXT: ands r1, r4
572 ; THUMB6-NEXT: ands r0, r5
573 ; THUMB6-NEXT: orrs r0, r1
574 ; THUMB6-NEXT: rsbs r1, r0, #0
575 ; THUMB6-NEXT: adcs r0, r1
576 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
577 ; THUMB6-NEXT: .p2align 2
578 ; THUMB6-NEXT: @ %bb.1:
579 ; THUMB6-NEXT: .LCPI11_0:
580 ; THUMB6-NEXT: .long 4294901760 @ 0xffff0000
581 ; THUMB6-NEXT: .LCPI11_1:
582 ; THUMB6-NEXT: .long 65535 @ 0xffff
583 ;
584 ; THUMB7-LABEL: scalar_i64_bitsinmiddle_eq:
585 ; THUMB7: @ %bb.0:
586 ; THUMB7-NEXT: push {r7, lr}
587 ; THUMB7-NEXT: movs r3, #0
588 ; THUMB7-NEXT: movw lr, #65535
589 ; THUMB7-NEXT: movt r3, #65535
590 ; THUMB7-NEXT: lsr.w r12, r3, r2
591 ; THUMB7-NEXT: rsb.w r3, r2, #32
592 ; THUMB7-NEXT: lsl.w r3, lr, r3
593 ; THUMB7-NEXT: orr.w r12, r12, r3
594 ; THUMB7-NEXT: subs.w r3, r2, #32
595 ; THUMB7-NEXT: lsr.w r2, lr, r2
596 ; THUMB7-NEXT: it pl
597 ; THUMB7-NEXT: lsrpl.w r12, lr, r3
598 ; THUMB7-NEXT: it pl
599 ; THUMB7-NEXT: movpl r2, #0
600 ; THUMB7-NEXT: and.w r0, r0, r12
601 ; THUMB7-NEXT: ands r1, r2
602 ; THUMB7-NEXT: orrs r0, r1
603 ; THUMB7-NEXT: clz r0, r0
604 ; THUMB7-NEXT: lsrs r0, r0, #5
605 ; THUMB7-NEXT: pop {r7, pc}
606 ;
607 ; THUMB8-LABEL: scalar_i64_bitsinmiddle_eq:
608 ; THUMB8: @ %bb.0:
609 ; THUMB8-NEXT: .save {r7, lr}
610 ; THUMB8-NEXT: push {r7, lr}
611 ; THUMB8-NEXT: movs r3, #0
612 ; THUMB8-NEXT: movw lr, #65535
613 ; THUMB8-NEXT: movt r3, #65535
614 ; THUMB8-NEXT: lsr.w r12, r3, r2
615 ; THUMB8-NEXT: rsb.w r3, r2, #32
616 ; THUMB8-NEXT: lsl.w r3, lr, r3
617 ; THUMB8-NEXT: orr.w r12, r12, r3
618 ; THUMB8-NEXT: subs.w r3, r2, #32
619 ; THUMB8-NEXT: lsr.w r2, lr, r2
620 ; THUMB8-NEXT: lsr.w r3, lr, r3
621 ; THUMB8-NEXT: it mi
622 ; THUMB8-NEXT: movmi r3, r12
623 ; THUMB8-NEXT: it pl
624 ; THUMB8-NEXT: movpl r2, #0
625 ; THUMB8-NEXT: ands r0, r3
626 ; THUMB8-NEXT: ands r1, r2
627 ; THUMB8-NEXT: orrs r0, r1
628 ; THUMB8-NEXT: clz r0, r0
629 ; THUMB8-NEXT: lsrs r0, r0, #5
630 ; THUMB8-NEXT: pop {r7, pc}
631 %t0 = lshr i64 281474976645120, %y
632 %t1 = and i64 %t0, %x
633 %res = icmp eq i64 %t1, 0
634 ret i1 %res
635 }
637 ;------------------------------------------------------------------------------;
638 ; A few trivial vector tests
639 ;------------------------------------------------------------------------------;
641 define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
642 ; ARM6-LABEL: vec_4xi32_splat_eq:
643 ; ARM6: @ %bb.0:
644 ; ARM6-NEXT: push {r11, lr}
645 ; ARM6-NEXT: ldr r12, [sp, #8]
646 ; ARM6-NEXT: mov lr, #1
647 ; ARM6-NEXT: and r0, r0, lr, lsr r12
648 ; ARM6-NEXT: ldr r12, [sp, #12]
649 ; ARM6-NEXT: clz r0, r0
650 ; ARM6-NEXT: and r1, r1, lr, lsr r12
651 ; ARM6-NEXT: ldr r12, [sp, #16]
652 ; ARM6-NEXT: clz r1, r1
653 ; ARM6-NEXT: lsr r0, r0, #5
654 ; ARM6-NEXT: and r2, r2, lr, lsr r12
655 ; ARM6-NEXT: ldr r12, [sp, #20]
656 ; ARM6-NEXT: clz r2, r2
657 ; ARM6-NEXT: lsr r1, r1, #5
658 ; ARM6-NEXT: and r3, r3, lr, lsr r12
659 ; ARM6-NEXT: lsr r2, r2, #5
660 ; ARM6-NEXT: clz r3, r3
661 ; ARM6-NEXT: lsr r3, r3, #5
662 ; ARM6-NEXT: pop {r11, pc}
663 ;
664 ; ARM78-LABEL: vec_4xi32_splat_eq:
665 ; ARM78: @ %bb.0:
666 ; ARM78-NEXT: mov r12, sp
667 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
668 ; ARM78-NEXT: vmov.i32 q9, #0x1
669 ; ARM78-NEXT: vneg.s32 q8, q8
670 ; ARM78-NEXT: vshl.u32 q8, q9, q8
671 ; ARM78-NEXT: vmov d19, r2, r3
672 ; ARM78-NEXT: vmov d18, r0, r1
673 ; ARM78-NEXT: vtst.32 q8, q8, q9
674 ; ARM78-NEXT: vmvn q8, q8
675 ; ARM78-NEXT: vmovn.i32 d16, q8
676 ; ARM78-NEXT: vmov r0, r1, d16
677 ; ARM78-NEXT: bx lr
678 ;
679 ; THUMB6-LABEL: vec_4xi32_splat_eq:
680 ; THUMB6: @ %bb.0:
681 ; THUMB6-NEXT: push {r4, r5, r6, lr}
682 ; THUMB6-NEXT: ldr r5, [sp, #16]
683 ; THUMB6-NEXT: movs r4, #1
684 ; THUMB6-NEXT: mov r6, r4
685 ; THUMB6-NEXT: lsrs r6, r5
686 ; THUMB6-NEXT: ands r6, r0
687 ; THUMB6-NEXT: rsbs r0, r6, #0
688 ; THUMB6-NEXT: adcs r0, r6
689 ; THUMB6-NEXT: ldr r5, [sp, #20]
690 ; THUMB6-NEXT: mov r6, r4
691 ; THUMB6-NEXT: lsrs r6, r5
692 ; THUMB6-NEXT: ands r6, r1
693 ; THUMB6-NEXT: rsbs r1, r6, #0
694 ; THUMB6-NEXT: adcs r1, r6
695 ; THUMB6-NEXT: ldr r5, [sp, #24]
696 ; THUMB6-NEXT: mov r6, r4
697 ; THUMB6-NEXT: lsrs r6, r5
698 ; THUMB6-NEXT: ands r6, r2
699 ; THUMB6-NEXT: rsbs r2, r6, #0
700 ; THUMB6-NEXT: adcs r2, r6
701 ; THUMB6-NEXT: ldr r5, [sp, #28]
702 ; THUMB6-NEXT: lsrs r4, r5
703 ; THUMB6-NEXT: ands r4, r3
704 ; THUMB6-NEXT: rsbs r3, r4, #0
705 ; THUMB6-NEXT: adcs r3, r4
706 ; THUMB6-NEXT: pop {r4, r5, r6, pc}
707 ;
708 ; THUMB78-LABEL: vec_4xi32_splat_eq:
709 ; THUMB78: @ %bb.0:
710 ; THUMB78-NEXT: mov r12, sp
711 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
712 ; THUMB78-NEXT: vmov.i32 q9, #0x1
713 ; THUMB78-NEXT: vneg.s32 q8, q8
714 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
715 ; THUMB78-NEXT: vmov d19, r2, r3
716 ; THUMB78-NEXT: vmov d18, r0, r1
717 ; THUMB78-NEXT: vtst.32 q8, q8, q9
718 ; THUMB78-NEXT: vmvn q8, q8
719 ; THUMB78-NEXT: vmovn.i32 d16, q8
720 ; THUMB78-NEXT: vmov r0, r1, d16
721 ; THUMB78-NEXT: bx lr
722 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
723 %t1 = and <4 x i32> %t0, %x
724 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
725 ret <4 x i1> %res
726 }
728 define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
729 ; ARM6-LABEL: vec_4xi32_nonsplat_eq:
730 ; ARM6: @ %bb.0:
731 ; ARM6-NEXT: ldr r12, [sp, #4]
732 ; ARM6-NEXT: mov r0, #1
733 ; ARM6-NEXT: and r0, r1, r0, lsr r12
734 ; ARM6-NEXT: ldr r12, [sp, #8]
735 ; ARM6-NEXT: clz r0, r0
736 ; ARM6-NEXT: lsr r1, r0, #5
737 ; ARM6-NEXT: mov r0, #65280
738 ; ARM6-NEXT: orr r0, r0, #16711680
739 ; ARM6-NEXT: and r0, r2, r0, lsr r12
740 ; ARM6-NEXT: ldr r12, [sp, #12]
741 ; ARM6-NEXT: clz r0, r0
742 ; ARM6-NEXT: lsr r2, r0, #5
743 ; ARM6-NEXT: mov r0, #-2147483648
744 ; ARM6-NEXT: and r0, r3, r0, lsr r12
745 ; ARM6-NEXT: clz r0, r0
746 ; ARM6-NEXT: lsr r3, r0, #5
747 ; ARM6-NEXT: mov r0, #1
748 ; ARM6-NEXT: bx lr
749 ;
750 ; ARM78-LABEL: vec_4xi32_nonsplat_eq:
751 ; ARM78: @ %bb.0:
752 ; ARM78-NEXT: mov r12, sp
753 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
754 ; ARM78-NEXT: adr r12, .LCPI13_0
755 ; ARM78-NEXT: vneg.s32 q8, q8
756 ; ARM78-NEXT: vld1.64 {d18, d19}, [r12:128]
757 ; ARM78-NEXT: vshl.u32 q8, q9, q8
758 ; ARM78-NEXT: vmov d19, r2, r3
759 ; ARM78-NEXT: vmov d18, r0, r1
760 ; ARM78-NEXT: vtst.32 q8, q8, q9
761 ; ARM78-NEXT: vmvn q8, q8
762 ; ARM78-NEXT: vmovn.i32 d16, q8
763 ; ARM78-NEXT: vmov r0, r1, d16
764 ; ARM78-NEXT: bx lr
765 ; ARM78-NEXT: .p2align 4
766 ; ARM78-NEXT: @ %bb.1:
767 ; ARM78-NEXT: .LCPI13_0:
768 ; ARM78-NEXT: .long 0 @ 0x0
769 ; ARM78-NEXT: .long 1 @ 0x1
770 ; ARM78-NEXT: .long 16776960 @ 0xffff00
771 ; ARM78-NEXT: .long 2147483648 @ 0x80000000
772 ;
773 ; THUMB6-LABEL: vec_4xi32_nonsplat_eq:
774 ; THUMB6: @ %bb.0:
775 ; THUMB6-NEXT: push {r4, r5, r7, lr}
776 ; THUMB6-NEXT: ldr r4, [sp, #20]
777 ; THUMB6-NEXT: movs r0, #1
778 ; THUMB6-NEXT: mov r5, r0
779 ; THUMB6-NEXT: lsrs r5, r4
780 ; THUMB6-NEXT: ands r5, r1
781 ; THUMB6-NEXT: rsbs r1, r5, #0
782 ; THUMB6-NEXT: adcs r1, r5
783 ; THUMB6-NEXT: ldr r4, [sp, #24]
784 ; THUMB6-NEXT: ldr r5, .LCPI13_0
785 ; THUMB6-NEXT: lsrs r5, r4
786 ; THUMB6-NEXT: ands r5, r2
787 ; THUMB6-NEXT: rsbs r2, r5, #0
788 ; THUMB6-NEXT: adcs r2, r5
789 ; THUMB6-NEXT: lsls r4, r0, #31
790 ; THUMB6-NEXT: ldr r5, [sp, #28]
791 ; THUMB6-NEXT: lsrs r4, r5
792 ; THUMB6-NEXT: ands r4, r3
793 ; THUMB6-NEXT: rsbs r3, r4, #0
794 ; THUMB6-NEXT: adcs r3, r4
795 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
796 ; THUMB6-NEXT: .p2align 2
797 ; THUMB6-NEXT: @ %bb.1:
798 ; THUMB6-NEXT: .LCPI13_0:
799 ; THUMB6-NEXT: .long 16776960 @ 0xffff00
800 ;
801 ; THUMB78-LABEL: vec_4xi32_nonsplat_eq:
802 ; THUMB78: @ %bb.0:
803 ; THUMB78-NEXT: mov r12, sp
804 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
805 ; THUMB78-NEXT: adr.w r12, .LCPI13_0
806 ; THUMB78-NEXT: vneg.s32 q8, q8
807 ; THUMB78-NEXT: vld1.64 {d18, d19}, [r12:128]
808 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
809 ; THUMB78-NEXT: vmov d19, r2, r3
810 ; THUMB78-NEXT: vmov d18, r0, r1
811 ; THUMB78-NEXT: vtst.32 q8, q8, q9
812 ; THUMB78-NEXT: vmvn q8, q8
813 ; THUMB78-NEXT: vmovn.i32 d16, q8
814 ; THUMB78-NEXT: vmov r0, r1, d16
815 ; THUMB78-NEXT: bx lr
816 ; THUMB78-NEXT: .p2align 4
817 ; THUMB78-NEXT: @ %bb.1:
818 ; THUMB78-NEXT: .LCPI13_0:
819 ; THUMB78-NEXT: .long 0 @ 0x0
820 ; THUMB78-NEXT: .long 1 @ 0x1
821 ; THUMB78-NEXT: .long 16776960 @ 0xffff00
822 ; THUMB78-NEXT: .long 2147483648 @ 0x80000000
823 %t0 = lshr <4 x i32> <i32 0, i32 1, i32 16776960, i32 2147483648>, %y
824 %t1 = and <4 x i32> %t0, %x
825 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
826 ret <4 x i1> %res
827 }
829 define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
830 ; ARM6-LABEL: vec_4xi32_nonsplat_undef0_eq:
831 ; ARM6: @ %bb.0:
832 ; ARM6-NEXT: push {r11, lr}
833 ; ARM6-NEXT: ldr r2, [sp, #12]
834 ; ARM6-NEXT: mov lr, #1
835 ; ARM6-NEXT: ldr r12, [sp, #8]
836 ; ARM6-NEXT: and r1, r1, lr, lsr r2
837 ; ARM6-NEXT: ldr r2, [sp, #20]
838 ; ARM6-NEXT: and r0, r0, lr, lsr r12
839 ; ARM6-NEXT: clz r1, r1
840 ; ARM6-NEXT: clz r0, r0
841 ; ARM6-NEXT: and r2, r3, lr, lsr r2
842 ; ARM6-NEXT: lsr r1, r1, #5
843 ; ARM6-NEXT: clz r2, r2
844 ; ARM6-NEXT: lsr r0, r0, #5
845 ; ARM6-NEXT: lsr r3, r2, #5
846 ; ARM6-NEXT: mov r2, #1
847 ; ARM6-NEXT: pop {r11, pc}
848 ;
849 ; ARM78-LABEL: vec_4xi32_nonsplat_undef0_eq:
850 ; ARM78: @ %bb.0:
851 ; ARM78-NEXT: mov r12, sp
852 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
853 ; ARM78-NEXT: vmov.i32 q9, #0x1
854 ; ARM78-NEXT: vneg.s32 q8, q8
855 ; ARM78-NEXT: vshl.u32 q8, q9, q8
856 ; ARM78-NEXT: vmov d19, r2, r3
857 ; ARM78-NEXT: vmov d18, r0, r1
858 ; ARM78-NEXT: vtst.32 q8, q8, q9
859 ; ARM78-NEXT: vmvn q8, q8
860 ; ARM78-NEXT: vmovn.i32 d16, q8
861 ; ARM78-NEXT: vmov r0, r1, d16
862 ; ARM78-NEXT: bx lr
863 ;
864 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef0_eq:
865 ; THUMB6: @ %bb.0:
866 ; THUMB6-NEXT: push {r4, r5, r7, lr}
867 ; THUMB6-NEXT: ldr r4, [sp, #16]
868 ; THUMB6-NEXT: movs r2, #1
869 ; THUMB6-NEXT: mov r5, r2
870 ; THUMB6-NEXT: lsrs r5, r4
871 ; THUMB6-NEXT: ands r5, r0
872 ; THUMB6-NEXT: rsbs r0, r5, #0
873 ; THUMB6-NEXT: adcs r0, r5
874 ; THUMB6-NEXT: ldr r4, [sp, #20]
875 ; THUMB6-NEXT: mov r5, r2
876 ; THUMB6-NEXT: lsrs r5, r4
877 ; THUMB6-NEXT: ands r5, r1
878 ; THUMB6-NEXT: rsbs r1, r5, #0
879 ; THUMB6-NEXT: adcs r1, r5
880 ; THUMB6-NEXT: ldr r4, [sp, #28]
881 ; THUMB6-NEXT: mov r5, r2
882 ; THUMB6-NEXT: lsrs r5, r4
883 ; THUMB6-NEXT: ands r5, r3
884 ; THUMB6-NEXT: rsbs r3, r5, #0
885 ; THUMB6-NEXT: adcs r3, r5
886 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
887 ;
888 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef0_eq:
889 ; THUMB78: @ %bb.0:
890 ; THUMB78-NEXT: mov r12, sp
891 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
892 ; THUMB78-NEXT: vmov.i32 q9, #0x1
893 ; THUMB78-NEXT: vneg.s32 q8, q8
894 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
895 ; THUMB78-NEXT: vmov d19, r2, r3
896 ; THUMB78-NEXT: vmov d18, r0, r1
897 ; THUMB78-NEXT: vtst.32 q8, q8, q9
898 ; THUMB78-NEXT: vmvn q8, q8
899 ; THUMB78-NEXT: vmovn.i32 d16, q8
900 ; THUMB78-NEXT: vmov r0, r1, d16
901 ; THUMB78-NEXT: bx lr
902 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
903 %t1 = and <4 x i32> %t0, %x
904 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
905 ret <4 x i1> %res
906 }
907 define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
908 ; ARM6-LABEL: vec_4xi32_nonsplat_undef1_eq:
909 ; ARM6: @ %bb.0:
910 ; ARM6-NEXT: push {r11, lr}
911 ; ARM6-NEXT: ldr r2, [sp, #12]
912 ; ARM6-NEXT: mov lr, #1
913 ; ARM6-NEXT: ldr r12, [sp, #8]
914 ; ARM6-NEXT: and r1, r1, lr, lsr r2
915 ; ARM6-NEXT: ldr r2, [sp, #20]
916 ; ARM6-NEXT: and r0, r0, lr, lsr r12
917 ; ARM6-NEXT: clz r1, r1
918 ; ARM6-NEXT: clz r0, r0
919 ; ARM6-NEXT: and r2, r3, lr, lsr r2
920 ; ARM6-NEXT: lsr r1, r1, #5
921 ; ARM6-NEXT: clz r2, r2
922 ; ARM6-NEXT: lsr r0, r0, #5
923 ; ARM6-NEXT: lsr r3, r2, #5
924 ; ARM6-NEXT: pop {r11, pc}
925 ;
926 ; ARM78-LABEL: vec_4xi32_nonsplat_undef1_eq:
927 ; ARM78: @ %bb.0:
928 ; ARM78-NEXT: mov r12, sp
929 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
930 ; ARM78-NEXT: vmov.i32 q9, #0x1
931 ; ARM78-NEXT: vneg.s32 q8, q8
932 ; ARM78-NEXT: vshl.u32 q8, q9, q8
933 ; ARM78-NEXT: vmov d19, r2, r3
934 ; ARM78-NEXT: vmov d18, r0, r1
935 ; ARM78-NEXT: vtst.32 q8, q8, q9
936 ; ARM78-NEXT: vmvn q8, q8
937 ; ARM78-NEXT: vmovn.i32 d16, q8
938 ; ARM78-NEXT: vmov r0, r1, d16
939 ; ARM78-NEXT: bx lr
940 ;
941 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef1_eq:
942 ; THUMB6: @ %bb.0:
943 ; THUMB6-NEXT: push {r4, r5, r7, lr}
944 ; THUMB6-NEXT: ldr r4, [sp, #16]
945 ; THUMB6-NEXT: movs r2, #1
946 ; THUMB6-NEXT: mov r5, r2
947 ; THUMB6-NEXT: lsrs r5, r4
948 ; THUMB6-NEXT: ands r5, r0
949 ; THUMB6-NEXT: rsbs r0, r5, #0
950 ; THUMB6-NEXT: adcs r0, r5
951 ; THUMB6-NEXT: ldr r4, [sp, #20]
952 ; THUMB6-NEXT: mov r5, r2
953 ; THUMB6-NEXT: lsrs r5, r4
954 ; THUMB6-NEXT: ands r5, r1
955 ; THUMB6-NEXT: rsbs r1, r5, #0
956 ; THUMB6-NEXT: adcs r1, r5
957 ; THUMB6-NEXT: ldr r4, [sp, #28]
958 ; THUMB6-NEXT: lsrs r2, r4
959 ; THUMB6-NEXT: ands r2, r3
960 ; THUMB6-NEXT: rsbs r3, r2, #0
961 ; THUMB6-NEXT: adcs r3, r2
962 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
963 ;
964 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef1_eq:
965 ; THUMB78: @ %bb.0:
966 ; THUMB78-NEXT: mov r12, sp
967 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
968 ; THUMB78-NEXT: vmov.i32 q9, #0x1
969 ; THUMB78-NEXT: vneg.s32 q8, q8
970 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
971 ; THUMB78-NEXT: vmov d19, r2, r3
972 ; THUMB78-NEXT: vmov d18, r0, r1
973 ; THUMB78-NEXT: vtst.32 q8, q8, q9
974 ; THUMB78-NEXT: vmvn q8, q8
975 ; THUMB78-NEXT: vmovn.i32 d16, q8
976 ; THUMB78-NEXT: vmov r0, r1, d16
977 ; THUMB78-NEXT: bx lr
978 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 1, i32 1>, %y
979 %t1 = and <4 x i32> %t0, %x
980 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
981 ret <4 x i1> %res
982 }
983 define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
984 ; ARM6-LABEL: vec_4xi32_nonsplat_undef2_eq:
985 ; ARM6: @ %bb.0:
986 ; ARM6-NEXT: push {r11, lr}
987 ; ARM6-NEXT: ldr r2, [sp, #12]
988 ; ARM6-NEXT: mov lr, #1
989 ; ARM6-NEXT: ldr r12, [sp, #8]
990 ; ARM6-NEXT: and r1, r1, lr, lsr r2
991 ; ARM6-NEXT: ldr r2, [sp, #20]
992 ; ARM6-NEXT: and r0, r0, lr, lsr r12
993 ; ARM6-NEXT: clz r1, r1
994 ; ARM6-NEXT: clz r0, r0
995 ; ARM6-NEXT: and r2, r3, lr, lsr r2
996 ; ARM6-NEXT: lsr r1, r1, #5
997 ; ARM6-NEXT: clz r2, r2
998 ; ARM6-NEXT: lsr r0, r0, #5
999 ; ARM6-NEXT: lsr r3, r2, #5
1000 ; ARM6-NEXT: pop {r11, pc}
1001 ;
1002 ; ARM78-LABEL: vec_4xi32_nonsplat_undef2_eq:
1003 ; ARM78: @ %bb.0:
1004 ; ARM78-NEXT: mov r12, sp
1005 ; ARM78-NEXT: vld1.64 {d16, d17}, [r12]
1006 ; ARM78-NEXT: vmov.i32 q9, #0x1
1007 ; ARM78-NEXT: vneg.s32 q8, q8
1008 ; ARM78-NEXT: vshl.u32 q8, q9, q8
1009 ; ARM78-NEXT: vmov d19, r2, r3
1010 ; ARM78-NEXT: vmov d18, r0, r1
1011 ; ARM78-NEXT: vtst.32 q8, q8, q9
1012 ; ARM78-NEXT: vmvn q8, q8
1013 ; ARM78-NEXT: vmovn.i32 d16, q8
1014 ; ARM78-NEXT: vmov r0, r1, d16
1015 ; ARM78-NEXT: bx lr
1016 ;
1017 ; THUMB6-LABEL: vec_4xi32_nonsplat_undef2_eq:
1018 ; THUMB6: @ %bb.0:
1019 ; THUMB6-NEXT: push {r4, r5, r7, lr}
1020 ; THUMB6-NEXT: ldr r4, [sp, #16]
1021 ; THUMB6-NEXT: movs r2, #1
1022 ; THUMB6-NEXT: mov r5, r2
1023 ; THUMB6-NEXT: lsrs r5, r4
1024 ; THUMB6-NEXT: ands r5, r0
1025 ; THUMB6-NEXT: rsbs r0, r5, #0
1026 ; THUMB6-NEXT: adcs r0, r5
1027 ; THUMB6-NEXT: ldr r4, [sp, #20]
1028 ; THUMB6-NEXT: mov r5, r2
1029 ; THUMB6-NEXT: lsrs r5, r4
1030 ; THUMB6-NEXT: ands r5, r1
1031 ; THUMB6-NEXT: rsbs r1, r5, #0
1032 ; THUMB6-NEXT: adcs r1, r5
1033 ; THUMB6-NEXT: ldr r4, [sp, #28]
1034 ; THUMB6-NEXT: lsrs r2, r4
1035 ; THUMB6-NEXT: ands r2, r3
1036 ; THUMB6-NEXT: rsbs r3, r2, #0
1037 ; THUMB6-NEXT: adcs r3, r2
1038 ; THUMB6-NEXT: pop {r4, r5, r7, pc}
1039 ;
1040 ; THUMB78-LABEL: vec_4xi32_nonsplat_undef2_eq:
1041 ; THUMB78: @ %bb.0:
1042 ; THUMB78-NEXT: mov r12, sp
1043 ; THUMB78-NEXT: vld1.64 {d16, d17}, [r12]
1044 ; THUMB78-NEXT: vmov.i32 q9, #0x1
1045 ; THUMB78-NEXT: vneg.s32 q8, q8
1046 ; THUMB78-NEXT: vshl.u32 q8, q9, q8
1047 ; THUMB78-NEXT: vmov d19, r2, r3
1048 ; THUMB78-NEXT: vmov d18, r0, r1
1049 ; THUMB78-NEXT: vtst.32 q8, q8, q9
1050 ; THUMB78-NEXT: vmvn q8, q8
1051 ; THUMB78-NEXT: vmovn.i32 d16, q8
1052 ; THUMB78-NEXT: vmov r0, r1, d16
1053 ; THUMB78-NEXT: bx lr
1054 %t0 = lshr <4 x i32> <i32 1, i32 1, i32 undef, i32 1>, %y
1055 %t1 = and <4 x i32> %t0, %x
1056 %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 undef, i32 0>
1057 ret <4 x i1> %res
1058 }
1060 ;------------------------------------------------------------------------------;
1061 ; A special tests
1062 ;------------------------------------------------------------------------------;
1064 define i1 @scalar_i8_signbit_ne(i8 %x, i8 %y) nounwind {
1065 ; ARM6-LABEL: scalar_i8_signbit_ne:
1066 ; ARM6: @ %bb.0:
1067 ; ARM6-NEXT: uxtb r1, r1
1068 ; ARM6-NEXT: mov r2, #128
1069 ; ARM6-NEXT: and r0, r0, r2, lsr r1
1070 ; ARM6-NEXT: uxtb r0, r0
1071 ; ARM6-NEXT: cmp r0, #0
1072 ; ARM6-NEXT: movne r0, #1
1073 ; ARM6-NEXT: bx lr
1074 ;
1075 ; ARM78-LABEL: scalar_i8_signbit_ne:
1076 ; ARM78: @ %bb.0:
1077 ; ARM78-NEXT: uxtb r1, r1
1078 ; ARM78-NEXT: mov r2, #128
1079 ; ARM78-NEXT: and r0, r0, r2, lsr r1
1080 ; ARM78-NEXT: uxtb r0, r0
1081 ; ARM78-NEXT: cmp r0, #0
1082 ; ARM78-NEXT: movwne r0, #1
1083 ; ARM78-NEXT: bx lr
1084 ;
1085 ; THUMB6-LABEL: scalar_i8_signbit_ne:
1086 ; THUMB6: @ %bb.0:
1087 ; THUMB6-NEXT: uxtb r1, r1
1088 ; THUMB6-NEXT: movs r2, #128
1089 ; THUMB6-NEXT: lsrs r2, r1
1090 ; THUMB6-NEXT: ands r2, r0
1091 ; THUMB6-NEXT: uxtb r0, r2
1092 ; THUMB6-NEXT: subs r1, r0, #1
1093 ; THUMB6-NEXT: sbcs r0, r1
1094 ; THUMB6-NEXT: bx lr
1095 ;
1096 ; THUMB78-LABEL: scalar_i8_signbit_ne:
1097 ; THUMB78: @ %bb.0:
1098 ; THUMB78-NEXT: uxtb r1, r1
1099 ; THUMB78-NEXT: movs r2, #128
1100 ; THUMB78-NEXT: lsr.w r1, r2, r1
1101 ; THUMB78-NEXT: ands r0, r1
1102 ; THUMB78-NEXT: uxtb r0, r0
1103 ; THUMB78-NEXT: cmp r0, #0
1104 ; THUMB78-NEXT: it ne
1105 ; THUMB78-NEXT: movne r0, #1
1106 ; THUMB78-NEXT: bx lr
1107 %t0 = lshr i8 128, %y
1108 %t1 = and i8 %t0, %x
1109 %res = icmp ne i8 %t1, 0 ; we are perfectly happy with 'ne' predicate
1110 ret i1 %res
1111 }
1113 ;------------------------------------------------------------------------------;
1114 ; What if X is a constant too?
1115 ;------------------------------------------------------------------------------;
1117 define i1 @scalar_i32_x_is_const_eq(i32 %y) nounwind {
1118 ; ARM6-LABEL: scalar_i32_x_is_const_eq:
1119 ; ARM6: @ %bb.0:
1120 ; ARM6-NEXT: ldr r1, .LCPI18_0
1121 ; ARM6-NEXT: mov r2, #1
1122 ; ARM6-NEXT: bic r0, r2, r1, lsr r0
1123 ; ARM6-NEXT: bx lr
1124 ; ARM6-NEXT: .p2align 2
1125 ; ARM6-NEXT: @ %bb.1:
1126 ; ARM6-NEXT: .LCPI18_0:
1127 ; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
1128 ;
1129 ; ARM78-LABEL: scalar_i32_x_is_const_eq:
1130 ; ARM78: @ %bb.0:
1131 ; ARM78-NEXT: movw r1, #43605
1132 ; ARM78-NEXT: mov r2, #1
1133 ; ARM78-NEXT: movt r1, #43605
1134 ; ARM78-NEXT: bic r0, r2, r1, lsr r0
1135 ; ARM78-NEXT: bx lr
1136 ;
1137 ; THUMB6-LABEL: scalar_i32_x_is_const_eq:
1138 ; THUMB6: @ %bb.0:
1139 ; THUMB6-NEXT: ldr r1, .LCPI18_0
1140 ; THUMB6-NEXT: lsrs r1, r0
1141 ; THUMB6-NEXT: movs r2, #1
1142 ; THUMB6-NEXT: ands r2, r1
1143 ; THUMB6-NEXT: rsbs r0, r2, #0
1144 ; THUMB6-NEXT: adcs r0, r2
1145 ; THUMB6-NEXT: bx lr
1146 ; THUMB6-NEXT: .p2align 2
1147 ; THUMB6-NEXT: @ %bb.1:
1148 ; THUMB6-NEXT: .LCPI18_0:
1149 ; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
1150 ;
1151 ; THUMB78-LABEL: scalar_i32_x_is_const_eq:
1152 ; THUMB78: @ %bb.0:
1153 ; THUMB78-NEXT: movw r1, #43605
1154 ; THUMB78-NEXT: movt r1, #43605
1155 ; THUMB78-NEXT: lsr.w r0, r1, r0
1156 ; THUMB78-NEXT: movs r1, #1
1157 ; THUMB78-NEXT: bic.w r0, r1, r0
1158 ; THUMB78-NEXT: bx lr
1159 %t0 = lshr i32 2857740885, %y
1160 %t1 = and i32 %t0, 1
1161 %res = icmp eq i32 %t1, 0
1162 ret i1 %res
1163 }
1164 define i1 @scalar_i32_x_is_const2_eq(i32 %y) nounwind {
1165 ; ARM6-LABEL: scalar_i32_x_is_const2_eq:
1166 ; ARM6: @ %bb.0:
1167 ; ARM6-NEXT: ldr r2, .LCPI19_0
1168 ; ARM6-NEXT: mov r1, #1
1169 ; ARM6-NEXT: and r0, r2, r1, lsr r0
1170 ; ARM6-NEXT: clz r0, r0
1171 ; ARM6-NEXT: lsr r0, r0, #5
1172 ; ARM6-NEXT: bx lr
1173 ; ARM6-NEXT: .p2align 2
1174 ; ARM6-NEXT: @ %bb.1:
1175 ; ARM6-NEXT: .LCPI19_0:
1176 ; ARM6-NEXT: .long 2857740885 @ 0xaa55aa55
1177 ;
1178 ; ARM78-LABEL: scalar_i32_x_is_const2_eq:
1179 ; ARM78: @ %bb.0:
1180 ; ARM78-NEXT: movw r1, #43605
1181 ; ARM78-NEXT: mov r2, #1
1182 ; ARM78-NEXT: movt r1, #43605
1183 ; ARM78-NEXT: and r0, r1, r2, lsr r0
1184 ; ARM78-NEXT: clz r0, r0
1185 ; ARM78-NEXT: lsr r0, r0, #5
1186 ; ARM78-NEXT: bx lr
1187 ;
1188 ; THUMB6-LABEL: scalar_i32_x_is_const2_eq:
1189 ; THUMB6: @ %bb.0:
1190 ; THUMB6-NEXT: movs r1, #1
1191 ; THUMB6-NEXT: lsrs r1, r0
1192 ; THUMB6-NEXT: ldr r2, .LCPI19_0
1193 ; THUMB6-NEXT: ands r2, r1
1194 ; THUMB6-NEXT: rsbs r0, r2, #0
1195 ; THUMB6-NEXT: adcs r0, r2
1196 ; THUMB6-NEXT: bx lr
1197 ; THUMB6-NEXT: .p2align 2
1198 ; THUMB6-NEXT: @ %bb.1:
1199 ; THUMB6-NEXT: .LCPI19_0:
1200 ; THUMB6-NEXT: .long 2857740885 @ 0xaa55aa55
1201 ;
1202 ; THUMB78-LABEL: scalar_i32_x_is_const2_eq:
1203 ; THUMB78: @ %bb.0:
1204 ; THUMB78-NEXT: movs r1, #1
1205 ; THUMB78-NEXT: lsr.w r0, r1, r0
1206 ; THUMB78-NEXT: movw r1, #43605
1207 ; THUMB78-NEXT: movt r1, #43605
1208 ; THUMB78-NEXT: ands r0, r1
1209 ; THUMB78-NEXT: clz r0, r0
1210 ; THUMB78-NEXT: lsrs r0, r0, #5
1211 ; THUMB78-NEXT: bx lr
1212 %t0 = lshr i32 1, %y
1213 %t1 = and i32 %t0, 2857740885
1214 %res = icmp eq i32 %t1, 0
1215 ret i1 %res
1216 }
1218 ;------------------------------------------------------------------------------;
1219 ; A few negative tests
1220 ;------------------------------------------------------------------------------;
1222 define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
1223 ; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1224 ; ARM6: @ %bb.0:
1225 ; ARM6-NEXT: uxtb r1, r1
1226 ; ARM6-NEXT: mov r2, #24
1227 ; ARM6-NEXT: and r0, r0, r2, lsr r1
1228 ; ARM6-NEXT: sxtb r1, r0
1229 ; ARM6-NEXT: mov r0, #0
1230 ; ARM6-NEXT: cmp r1, #0
1231 ; ARM6-NEXT: movmi r0, #1
1232 ; ARM6-NEXT: bx lr
1233 ;
1234 ; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1235 ; ARM78: @ %bb.0:
1236 ; ARM78-NEXT: uxtb r1, r1
1237 ; ARM78-NEXT: mov r2, #24
1238 ; ARM78-NEXT: and r0, r0, r2, lsr r1
1239 ; ARM78-NEXT: sxtb r1, r0
1240 ; ARM78-NEXT: mov r0, #0
1241 ; ARM78-NEXT: cmp r1, #0
1242 ; ARM78-NEXT: movwmi r0, #1
1243 ; ARM78-NEXT: bx lr
1244 ;
1245 ; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1246 ; THUMB6: @ %bb.0:
1247 ; THUMB6-NEXT: uxtb r1, r1
1248 ; THUMB6-NEXT: movs r2, #24
1249 ; THUMB6-NEXT: lsrs r2, r1
1250 ; THUMB6-NEXT: ands r2, r0
1251 ; THUMB6-NEXT: sxtb r0, r2
1252 ; THUMB6-NEXT: cmp r0, #0
1253 ; THUMB6-NEXT: bmi .LBB20_2
1254 ; THUMB6-NEXT: @ %bb.1:
1255 ; THUMB6-NEXT: movs r0, #0
1256 ; THUMB6-NEXT: bx lr
1257 ; THUMB6-NEXT: .LBB20_2:
1258 ; THUMB6-NEXT: movs r0, #1
1259 ; THUMB6-NEXT: bx lr
1260 ;
1261 ; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
1262 ; THUMB78: @ %bb.0:
1263 ; THUMB78-NEXT: uxtb r1, r1
1264 ; THUMB78-NEXT: movs r2, #24
1265 ; THUMB78-NEXT: lsr.w r1, r2, r1
1266 ; THUMB78-NEXT: ands r0, r1
1267 ; THUMB78-NEXT: sxtb r1, r0
1268 ; THUMB78-NEXT: movs r0, #0
1269 ; THUMB78-NEXT: cmp r1, #0
1270 ; THUMB78-NEXT: it mi
1271 ; THUMB78-NEXT: movmi r0, #1
1272 ; THUMB78-NEXT: bx lr
1273 %t0 = lshr i8 24, %y
1274 %t1 = and i8 %t0, %x
1275 %res = icmp slt i8 %t1, 0
1276 ret i1 %res
1277 }
1279 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
1280 ; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:
1281 ; ARM: @ %bb.0:
1282 ; ARM-NEXT: uxtb r1, r1
1283 ; ARM-NEXT: mov r2, #128
1284 ; ARM-NEXT: and r0, r0, r2, lsr r1
1285 ; ARM-NEXT: mvn r1, #0
1286 ; ARM-NEXT: uxtab r0, r1, r0
1287 ; ARM-NEXT: clz r0, r0
1288 ; ARM-NEXT: lsr r0, r0, #5
1289 ; ARM-NEXT: bx lr
1290 ;
1291 ; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:
1292 ; THUMB6: @ %bb.0:
1293 ; THUMB6-NEXT: uxtb r1, r1
1294 ; THUMB6-NEXT: movs r2, #128
1295 ; THUMB6-NEXT: lsrs r2, r1
1296 ; THUMB6-NEXT: ands r2, r0
1297 ; THUMB6-NEXT: uxtb r0, r2
1298 ; THUMB6-NEXT: subs r1, r0, #1
1299 ; THUMB6-NEXT: rsbs r0, r1, #0
1300 ; THUMB6-NEXT: adcs r0, r1
1301 ; THUMB6-NEXT: bx lr
1302 ;
1303 ; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:
1304 ; THUMB78: @ %bb.0:
1305 ; THUMB78-NEXT: uxtb r1, r1
1306 ; THUMB78-NEXT: movs r2, #128
1307 ; THUMB78-NEXT: lsr.w r1, r2, r1
1308 ; THUMB78-NEXT: ands r0, r1
1309 ; THUMB78-NEXT: mov.w r1, #-1
1310 ; THUMB78-NEXT: uxtab r0, r1, r0
1311 ; THUMB78-NEXT: clz r0, r0
1312 ; THUMB78-NEXT: lsrs r0, r0, #5
1313 ; THUMB78-NEXT: bx lr
1314 %t0 = lshr i8 128, %y
1315 %t1 = and i8 %t0, %x
1316 %res = icmp eq i8 %t1, 1 ; should be comparing with 0
1317 ret i1 %res
1318 }