1 ; The failure is caused by ARM LDRcp/PICADD pairs. In PIC mode, the constant pool
2 ; need a label to do address computation. This label is emitted when backend emits
3 ; PICADD. When the target becomes dead, PICADD will be deleted. without this patch
4 ; LDRcp is dead but not being deleted. This will cause a dead contant pool entry
5 ; using a non existing label. This will cause an error in MC object emitting pass.
7 ; RUN: llc -relocation-model=pic -mcpu=cortex-a53 %s -filetype=obj -o - | llvm-nm - | FileCheck %s
9 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
10 target triple = "armv8-unknown-linux-android"
12 @_ZN15UsecaseSelector25AllowedImplDefinedFormatsE = external dso_local unnamed_addr constant <{ i32, i32, i32, i32, [12 x i32] }>, align 4
14 ; Function Attrs: noinline nounwind optnone sspstrong uwtable
15 define dso_local fastcc void @_ZN15UsecaseSelector26IsAllowedImplDefinedFormatE15ChiBufferFormatj() unnamed_addr #1 align 2 {
18 ; <label>:1: ; preds = %13, %0
19 %2 = icmp ult i32 undef, 4
20 br i1 %2, label %3, label %14
22 ; <label>:3: ; preds = %1
23 br i1 undef, label %4, label %13
25 ; <label>:4: ; preds = %3
26 %5 = getelementptr inbounds [16 x i32], [16 x i32]* bitcast (<{ i32, i32, i32, i32, [12 x i32] }>* @_ZN15UsecaseSelector25AllowedImplDefinedFormatsE to [16 x i32]*), i32 0, i32 undef
27 %6 = load i32, i32* %5, align 4
28 %7 = icmp eq i32 10, %6
29 br i1 %7, label %9, label %8
31 ; <label>:8: ; preds = %4
32 br i1 undef, label %9, label %12
34 ; <label>:9: ; preds = %8, %4
35 br i1 undef, label %10, label %13
37 ; <label>:10: ; preds = %9
38 br i1 undef, label %11, label %13
40 ; <label>:11: ; preds = %10
43 ; <label>:12: ; preds = %8
46 ; <label>:13: ; preds = %10, %9, %3
49 ; <label>:14: ; preds = %12, %11, %1
53 attributes #1 = { noinline optnone }
55 ; CHECK: _ZN15UsecaseSelector26IsAllowedImplDefinedFormatE15ChiBufferFormatj