| blob | 565e26537c1634ca781b1ad3d1ce427036f2d383 |
1 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-LE
2 ; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-V7-LE
3 ; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
4 ; RUN: llc -mtriple=armebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V7-BE
5 ; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6-THUMB
6 ; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2-DSP
7 ; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2-DSP
8 ; RUN: llc -mtriple=thumbebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V7-THUMB-BE
9 ; RUN: llc -mtriple=thumbv6m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6M-THUMB
10 ; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V7M-THUMB
11 ; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-T2-DSP
12 ; RUN: llc -mtriple=armv5te-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V5TE
13 ; Check generated signed and unsigned multiply accumulate long.
15 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
16 ;CHECK-LABEL: MACLongTest1:
17 ;CHECK-V6-THUMB-NOT: umlal
18 ;CHECK-LE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
19 ;CHECK-LE: mov r0, [[RDLO]]
20 ;CHECK-LE: mov r1, [[RDHI]]
21 ;CHECK-BE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
22 ;CHECK-BE: mov r0, [[RDHI]]
23 ;CHECK-BE: mov r1, [[RDLO]]
24 ;CHECK-T2-DSP: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
25 ;CHECK-T2-DSP-NEXT: mov r0, [[RDLO]]
26 ;CHECK-T2-DSP-NEXT: mov r1, [[RDHI]]
27 ;CHECK-V7-THUMB-BE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
28 ;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
29 ;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
30 %conv = zext i32 %a to i64
31 %conv1 = zext i32 %b to i64
32 %mul = mul i64 %conv1, %conv
33 %add = add i64 %mul, %c
34 ret i64 %add
35 }
37 define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c) {
38 ;CHECK-LABEL: MACLongTest2:
39 ;CHECK-LE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
40 ;CHECK-LE: mov r0, [[RDLO]]
41 ;CHECK-LE: mov r1, [[RDHI]]
42 ;CHECK-BE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
43 ;CHECK-BE: mov r0, [[RDHI]]
44 ;CHECK-BE: mov r1, [[RDLO]]
45 ;CHECK-T2-DSP: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
46 ;CHECK-T2-DSP-NEXT: mov r0, [[RDLO]]
47 ;CHECK-T2-DSP-NEXT: mov r1, [[RDHI]]
48 ;CHECK-V7-THUMB-BE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
49 ;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
50 ;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
51 %conv = sext i32 %a to i64
52 %conv1 = sext i32 %b to i64
53 %mul = mul nsw i64 %conv1, %conv
54 %add = add nsw i64 %mul, %c
55 ret i64 %add
56 }
58 ; Two things to check here: the @earlyclobber constraint (on <= v5) and the "$Rd = $R" ones.
59 ; + Without @earlyclobber the v7 code is natural. With it, the first two
60 ; registers must be distinct from the third.
61 ; + Without "$Rd = $R", this can be satisfied without a mov before the umlal
62 ; by trying to use 6 different registers in the MachineInstr. The natural
63 ; evolution of this attempt currently leaves only two movs in the final
64 ; function, both after the umlal. With it, *some* move has to happen
65 ; before the umlal.
66 define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
67 ;CHECK-LABEL: MACLongTest3:
68 ;CHECK-LE: mov [[RDHI:r[0-9]+]], #0
69 ;CHECK-LE: umlal [[RDLO:r[0-9]+]], [[RDHI]], r1, r0
70 ;CHECK-LE: mov r0, [[RDLO]]
71 ;CHECK-LE: mov r1, [[RDHI]]
72 ;CHECK-BE: mov [[RDHI:r[0-9]+]], #0
73 ;CHECK-BE: umlal [[RDLO:r[0-9]+]], [[RDHI]], r1, r0
74 ;CHECK-BE: mov r0, [[RDHI]]
75 ;CHECK-BE: mov r1, [[RDLO]]
76 ;CHECK-T2-DSP: umlal
77 ;CHECK-V6-THUMB-NOT: umlal
78 %conv = zext i32 %b to i64
79 %conv1 = zext i32 %a to i64
80 %mul = mul i64 %conv, %conv1
81 %conv2 = zext i32 %c to i64
82 %add = add i64 %mul, %conv2
83 ret i64 %add
84 }
86 define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
87 ;CHECK-LABEL: MACLongTest4:
88 ;CHECK-V6-THUMB-NOT: smlal
89 ;CHECK-T2-DSP: smlal
90 ;CHECK-LE: asr [[RDHI:r[0-9]+]], [[RDLO:r[0-9]+]], #31
91 ;CHECK-LE: smlal [[RDLO]], [[RDHI]], r1, r0
92 ;CHECK-LE: mov r0, [[RDLO]]
93 ;CHECK-LE: mov r1, [[RDHI]]
94 ;CHECK-BE: asr [[RDHI:r[0-9]+]], [[RDLO:r[0-9]+]], #31
95 ;CHECK-BE: smlal [[RDLO]], [[RDHI]], r1, r0
96 ;CHECK-BE: mov r0, [[RDHI]]
97 ;CHECK-BE: mov r1, [[RDLO]]
98 %conv = sext i32 %b to i64
99 %conv1 = sext i32 %a to i64
100 %mul = mul nsw i64 %conv, %conv1
101 %conv2 = sext i32 %c to i64
102 %add = add nsw i64 %mul, %conv2
103 ret i64 %add
104 }
106 define i64 @MACLongTest6(i32 %a, i32 %b, i32 %c, i32 %d) {
107 ;CHECK-LABEL: MACLongTest6:
108 ;CHECK-V6-THUMB-NOT: smull
109 ;CHECK-V6-THUMB-NOT: smlal
110 ;CHECK-LE: smull r12, lr, r1, r0
111 ;CHECK-LE: smlal r12, lr, r3, r2
112 ;CHECK-V7: smull [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], r1, r0
113 ;CHECK-V7: smlal [[RDLO]], [[RDHI]], [[Rn:r[0-9]+]], [[Rm:r[0-9]+]]
114 ;CHECK-T2-DSP: smull [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], r1, r0
115 ;CHECK-T2-DSP: smlal [[RDLO]], [[RDHI]], [[Rn:r[0-9]+]], [[Rm:r[0-9]+]]
116 %conv = sext i32 %a to i64
117 %conv1 = sext i32 %b to i64
118 %mul = mul nsw i64 %conv1, %conv
119 %conv2 = sext i32 %c to i64
120 %conv3 = sext i32 %d to i64
121 %mul4 = mul nsw i64 %conv3, %conv2
122 %add = add nsw i64 %mul4, %mul
123 ret i64 %add
124 }
126 define i64 @MACLongTest7(i64 %acc, i32 %lhs, i32 %rhs) {
127 ;CHECK-LABEL: MACLongTest7:
128 ;CHECK-NOT: smlal
129 ;CHECK-V6-THUMB2-NOT: smlal
130 ;CHECK-V7-THUMB-NOT: smlal
131 ;CHECK-V6-THUMB-NOT: smlal
132 %conv = sext i32 %lhs to i64
133 %conv1 = sext i32 %rhs to i64
134 %mul = mul nsw i64 %conv1, %conv
135 %shl = shl i64 %mul, 32
136 %shr = lshr i64 %mul, 32
137 %or = or i64 %shl, %shr
138 %add = add i64 %or, %acc
139 ret i64 %add
140 }
142 define i64 @MACLongTest8(i64 %acc, i32 %lhs, i32 %rhs) {
143 ;CHECK-LABEL: MACLongTest8:
144 ;CHECK-NOT: smlal
145 ;CHECK-V6-THUMB2-NOT: smlal
146 ;CHECK-V7-THUMB-NOT: smlal
147 ;CHECK-V6-THUMB-NOT: smlal
148 %conv = zext i32 %lhs to i64
149 %conv1 = zext i32 %rhs to i64
150 %mul = mul nuw i64 %conv1, %conv
151 %and = and i64 %mul, 4294967295
152 %shl = shl i64 %mul, 32
153 %or = or i64 %and, %shl
154 %add = add i64 %or, %acc
155 ret i64 %add
156 }
158 define i64 @MACLongTest9(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {
159 ;CHECK-LABEL: MACLongTest9:
160 ;CHECK-V7-LE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
161 ;CHECK-V7-LE: mov r0, [[RDLO]]
162 ;CHECK-V7-LE: mov r1, [[RDHI]]
163 ;CHECK-V7-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
164 ;CHECK-V7-BE: mov r0, [[RDHI]]
165 ;CHECK-V7-BE: mov r1, [[RDLO]]
166 ;CHECK-T2-DSP: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
167 ;CHECK-T2-DSP-NEXT: mov r0, [[RDLO]]
168 ;CHECK-T2-DSP-NEXT: mov r1, [[RDHI]]
169 ;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
170 ;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
171 ;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
172 ;CHECK-NOT:umaal
173 ;CHECK-V6-THUMB-NOT: umaal
174 ;CHECK-V6M-THUMB-NOT: umaal
175 ;CHECK-V7M-THUMB-NOT: umaal
176 %conv = zext i32 %lhs to i64
177 %conv1 = zext i32 %rhs to i64
178 %mul = mul nuw i64 %conv1, %conv
179 %conv2 = zext i32 %lo to i64
180 %add = add i64 %mul, %conv2
181 %conv3 = zext i32 %hi to i64
182 %add2 = add i64 %add, %conv3
183 ret i64 %add2
184 }
186 define i64 @MACLongTest10(i32 %lhs, i32 %rhs, i32 %lo, i32 %hi) {
187 ;CHECK-LABEL: MACLongTest10:
188 ;CHECK-V7-LE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
189 ;CHECK-V7-LE: mov r0, [[RDLO]]
190 ;CHECK-V7-LE: mov r1, [[RDHI]]
191 ;CHECK-V7-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
192 ;CHECK-V7-BE: mov r0, [[RDHI]]
193 ;CHECK-V7-BE: mov r1, [[RDLO]]
194 ;CHECK-T2-DSP: umaal r2, r3, r1, r0
195 ;CHECK-T2-DSP-NEXT: mov r0, r2
196 ;CHECK-T2-DSP-NEXT: mov r1, r3
197 ;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
198 ;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
199 ;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
200 ;CHECK-NOT:umaal
201 ;CHECK-V6-THUMB-NOT:umaal
202 ;CHECK-V6M-THUMB-NOT: umaal
203 ;CHECK-V7M-THUMB-NOT: umaal
204 %conv = zext i32 %lhs to i64
205 %conv1 = zext i32 %rhs to i64
206 %mul = mul nuw i64 %conv1, %conv
207 %conv2 = zext i32 %lo to i64
208 %conv3 = zext i32 %hi to i64
209 %add = add i64 %conv2, %conv3
210 %add2 = add i64 %add, %mul
211 ret i64 %add2
212 }
214 define i64 @MACLongTest11(i16 %a, i16 %b, i64 %c) {
215 ;CHECK-LABEL: MACLongTest11:
216 ;CHECK-T2-DSP-NOT: sxth
217 ;CHECK-T2-DSP: smlalbb r2, r3
218 ;CHECK-T2-DSP-NEXT: mov r0, r2
219 ;CHECK-T2-DSP-NEXT: mov r1, r3
220 ;CHECK-V5TE-NOT: sxth
221 ;CHECK-V5TE: smlalbb r2, r3
222 ;CHECK-V5TE-NEXT: mov r0, r2
223 ;CHECK-V5TE-NEXT: mov r1, r3
224 ;CHECK-V7-LE-NOT: sxth
225 ;CHECK-V7-LE: smlalbb r2, r3
226 ;CHECK-V7-LE-NEXT: mov r0, r2
227 ;CHECK-V7-LE-NEXT: mov r1, r3
228 ;CHECK-V7-THUMB-BE: smlalbb r3, r2
229 ;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
230 ;CHECK-V7-THUMB-BE-NEXT: mov r1, r3
231 ;CHECK-LE-NOT: smlalbb
232 ;CHECK-BE-NOT: smlalbb
233 ;CHECK-V6M-THUMB-NOT: smlalbb
234 ;CHECK-V7M-THUMB-NOT: smlalbb
235 %conv = sext i16 %a to i32
236 %conv1 = sext i16 %b to i32
237 %mul = mul nsw i32 %conv1, %conv
238 %conv2 = sext i32 %mul to i64
239 %add = add nsw i64 %conv2, %c
240 ret i64 %add
241 }
243 define i64 @MACLongTest12(i16 %b, i32 %t, i64 %c) {
244 ;CHECK-LABEL: MACLongTest12:
245 ;CHECK-T2-DSP-NOT: sxth
246 ;CHECK-T2-DSP-NOT: {{asr|lsr}}
247 ;CHECK-T2-DSP: smlalbt r2, r3, r0, r1
248 ;CHECK-T2-DSP-NEXT: mov r0, r2
249 ;CHECK-T2-DSP-NEXT: mov r1, r3
250 ;CHECK-T2-DSP-NOT: sxth
251 ;CHECK-V5TE-NOT: sxth
252 ;CHECK-V5TE-NOT: {{asr|lsr}}
253 ;CHECK-V5TE: smlalbt r2, r3, r0, r1
254 ;CHECK-V5TE-NEXT: mov r0, r2
255 ;CHECK-V5TE-NEXT: mov r1, r3
256 ;CHECK-V7-LE-NOT: sxth
257 ;CHECK-V7-LE-NOT: {{asr|lsr}}
258 ;CHECK-V7-LE: smlalbt r2, r3, r0, r1
259 ;CHECK-V7-LE-NEXT: mov r0, r2
260 ;CHECK-V7-LE-NEXT: mov r1, r3
261 ;CHECK-V7-THUMB-BE: smlalbt r3, r2,
262 ;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
263 ;CHECK-V7-THUMB-BE-NEXT: mov r1, r3
264 ;CHECK-LE-NOT: smlalbt
265 ;CHECK-BE-NOT: smlalbt
266 ;CHECK-V6M-THUMB-NOT: smlalbt
267 ;CHECK-V7M-THUMB-NOT: smlalbt
268 %conv0 = sext i16 %b to i32
269 %conv1 = ashr i32 %t, 16
270 %mul = mul nsw i32 %conv0, %conv1
271 %conv2 = sext i32 %mul to i64
272 %add = add nsw i64 %conv2, %c
273 ret i64 %add
274 }
276 define i64 @MACLongTest13(i32 %t, i16 %b, i64 %c) {
277 ;CHECK-LABEL: MACLongTest13:
278 ;CHECK-T2-DSP-NOT: sxth
279 ;CHECK-T2-DSP-NOT: {{asr|lsr}}
280 ;CHECK-T2-DSP: smlaltb r2, r3, r0, r1
281 ;CHECK-T2-DSP-NEXT: mov r0, r2
282 ;CHECK-T2-DSP-NEXT: mov r1, r3
283 ;CHECK-V5TE-NOT: sxth
284 ;CHECK-V5TE-NOT: {{asr|lsr}}
285 ;CHECK-V5TE: smlaltb r2, r3, r0, r1
286 ;CHECK-V5TE-NEXT: mov r0, r2
287 ;CHECK-V5TE-NEXT: mov r1, r3
288 ;CHECK-V7-LE-NOT: sxth
289 ;CHECK-V7-LE-NOT: {{asr|lsr}}
290 ;CHECK-V7-LE: smlaltb r2, r3, r0, r1
291 ;CHECK-V7-LE-NEXT: mov r0, r2
292 ;CHECK-V7-LE-NEXT: mov r1, r3
293 ;CHECK-V7-THUMB-BE: smlaltb r3, r2, r0, r1
294 ;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
295 ;CHECK-V7-THUMB-BE-NEXT: mov r1, r3
296 ;CHECK-LE-NOT: smlaltb
297 ;CHECK-BE-NOT: smlaltb
298 ;CHECK-V6M-THUMB-NOT: smlaltb
299 ;CHECK-V7M-THUMB-NOT: smlaltb
300 %conv0 = ashr i32 %t, 16
301 %conv1= sext i16 %b to i32
302 %mul = mul nsw i32 %conv0, %conv1
303 %conv2 = sext i32 %mul to i64
304 %add = add nsw i64 %conv2, %c
305 ret i64 %add
306 }
308 define i64 @MACLongTest14(i32 %a, i32 %b, i64 %c) {
309 ;CHECK-LABEL: MACLongTest14:
310 ;CHECK-T2-DSP-NOT: {{asr|lsr}}
311 ;CHECK-T2-DSP: smlaltt r2, r3,
312 ;CHECK-T2-DSP-NEXT: mov r0, r2
313 ;CHECK-T2-DSP-NEXT: mov r1, r3
314 ;CHECK-V5TE-NOT: {{asr|lsr}}
315 ;CHECK-V5TE: smlaltt r2, r3,
316 ;CHECK-V5TE-NEXT: mov r0, r2
317 ;CHECK-V5TE-NEXT: mov r1, r3
318 ;CHECK-V7-LE-NOT: {{asr|lsr}}
319 ;CHECK-V7-LE: smlaltt r2, r3,
320 ;CHECK-V7-LE-NEXT: mov r0, r2
321 ;CHECK-V7-LE-NEXT: mov r1, r3
322 ;CHECK-V7-THUMB-BE: smlaltt r3, r2,
323 ;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
324 ;CHECK-V7-THUMB-BE-NEXT: mov r1, r3
325 ;CHECK-LE-NOT: smlaltt
326 ;CHECK-BE-NOT: smlaltt
327 ;CHECK-V6M-THUMB-NOT: smlaltt
328 ;CHECK-V7M-THUMB-NOT: smlaltt
329 %conv0 = ashr i32 %a, 16
330 %conv1 = ashr i32 %b, 16
331 %mul = mul nsw i32 %conv1, %conv0
332 %conv2 = sext i32 %mul to i64
333 %add = add nsw i64 %conv2, %c
334 ret i64 %add
335 }
337 @global_b = external global i16, align 2
338 ;CHECK-LABEL: MACLongTest15
339 ;CHECK-T2-DSP-NOT: {{asr|lsr}}
340 ;CHECK-T2-DSP: mov r1, r3
341 ;CHECK-T2-DSP: smlaltb r2, r1, r0, r3
342 ;CHECK-T2-DSP-NEXT: mov r0, r2
343 ;CHECK-V5TE-NOT: {{asr|lsr}}
344 ;CHECK-V5TE: mov r1, r3
345 ;CHECK-V5TE: smlaltb r2, r1, r0, r3
346 ;CHECK-V5TE-NEXT: mov r0, r2
347 ;CHECK-V7-LE-NOT: {{asr|lsr}}
348 ;CHECK-V7-LE: mov r1, r3
349 ;CHECK-V7-LE: smlaltb r2, r1, r0, r3
350 ;CHECK-V7-LE-NEXT: mov r0, r2
351 ;CHECK-V7-THUMB-BE: mov r1, r3
352 ;CHECK-V7-THUMB-BE: smlaltb r1, r2, r0, r3
353 ;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
354 ;CHECK-LE-NOT: smlaltb
355 ;CHECK-BE-NOT: smlaltb
356 ;CHECK-V6M-THUMB-NOT: smlaltb
357 ;CHECK-V7M-THUMB-NOT: smlaltb
358 define i64 @MACLongTest15(i32 %t, i64 %acc) {
359 entry:
360 %0 = load i16, i16* @global_b, align 2
361 %conv = sext i16 %0 to i32
362 %shr = ashr i32 %t, 16
363 %mul = mul nsw i32 %shr, %conv
364 %conv1 = sext i32 %mul to i64
365 %add = add nsw i64 %conv1, %acc
366 ret i64 %add
367 }
369 ;CHECK-LABEL: MACLongTest16
370 ;CHECK-T2-DSP-NOT: {{asr|lsr}}
371 ;CHECK-T2-DSP: mov r1, r3
372 ;CHECK-T2-DSP: smlalbt r2, r1, r3, r0
373 ;CHECK-T2-DSP-NEXT: mov r0, r2
374 ;CHECK-V5TE-NOT: {{asr|lsr}}
375 ;CHECK-V5TE: mov r1, r3
376 ;CHECK-V5TE: smlalbt r2, r1, r3, r0
377 ;CHECK-V5TE-NEXT: mov r0, r2
378 ;CHECK-V7-LE: mov r1, r3
379 ;CHECK-V7-LE: smlalbt r2, r1, r3, r0
380 ;CHECK-V7-LE-NEXT: mov r0, r2
381 ;CHECK-V7-THUMB-BE: mov r1, r3
382 ;CHECK-V7-THUMB-BE: smlalbt r1, r2, r3, r0
383 ;CHECK-V7-THUMB-BE-NEXT: mov r0, r2
384 ;CHECK-LE-NOT: smlalbt
385 ;CHECK-BE-NOT: smlalbt
386 ;CHECK-V6M-THUMB-NOT: smlalbt
387 ;CHECK-V7M-THUMB-NOT: smlalbt
388 define i64 @MACLongTest16(i32 %t, i64 %acc) {
389 entry:
390 %0 = load i16, i16* @global_b, align 2
391 %conv = sext i16 %0 to i32
392 %shr = ashr i32 %t, 16
393 %mul = mul nsw i32 %conv, %shr
394 %conv1 = sext i32 %mul to i64
395 %add = add nsw i64 %conv1, %acc
396 ret i64 %add
397 }