1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx \
3 ; RUN: -enable-legalize-types-checking | FileCheck %s
4 ; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx \
5 ; RUN: -enable-legalize-types-checking | FileCheck %s
7 define i32 @TestComp128GT(fp128 %d1, fp128 %d2) {
8 ; CHECK-LABEL: TestComp128GT:
9 ; CHECK: # %bb.0: # %entry
10 ; CHECK-NEXT: pushq %rax
11 ; CHECK-NEXT: .cfi_def_cfa_offset 16
12 ; CHECK-NEXT: callq __gttf2
13 ; CHECK-NEXT: xorl %ecx, %ecx
14 ; CHECK-NEXT: testl %eax, %eax
15 ; CHECK-NEXT: setg %cl
16 ; CHECK-NEXT: movl %ecx, %eax
17 ; CHECK-NEXT: popq %rcx
18 ; CHECK-NEXT: .cfi_def_cfa_offset 8
21 %cmp = fcmp ogt fp128 %d1, %d2
22 %conv = zext i1 %cmp to i32
26 define i32 @TestComp128GE(fp128 %d1, fp128 %d2) {
27 ; CHECK-LABEL: TestComp128GE:
28 ; CHECK: # %bb.0: # %entry
29 ; CHECK-NEXT: pushq %rax
30 ; CHECK-NEXT: .cfi_def_cfa_offset 16
31 ; CHECK-NEXT: callq __getf2
32 ; CHECK-NEXT: xorl %ecx, %ecx
33 ; CHECK-NEXT: testl %eax, %eax
34 ; CHECK-NEXT: setns %cl
35 ; CHECK-NEXT: movl %ecx, %eax
36 ; CHECK-NEXT: popq %rcx
37 ; CHECK-NEXT: .cfi_def_cfa_offset 8
40 %cmp = fcmp oge fp128 %d1, %d2
41 %conv = zext i1 %cmp to i32
45 define i32 @TestComp128LT(fp128 %d1, fp128 %d2) {
46 ; CHECK-LABEL: TestComp128LT:
47 ; CHECK: # %bb.0: # %entry
48 ; CHECK-NEXT: pushq %rax
49 ; CHECK-NEXT: .cfi_def_cfa_offset 16
50 ; CHECK-NEXT: callq __lttf2
51 ; CHECK-NEXT: shrl $31, %eax
52 ; CHECK-NEXT: popq %rcx
53 ; CHECK-NEXT: .cfi_def_cfa_offset 8
56 %cmp = fcmp olt fp128 %d1, %d2
57 %conv = zext i1 %cmp to i32
59 ; The 'shrl' is a special optimization in llvm to combine
60 ; the effect of 'fcmp olt' and 'zext'. The main purpose is
61 ; to test soften call to __lttf2.
64 define i32 @TestComp128LE(fp128 %d1, fp128 %d2) {
65 ; CHECK-LABEL: TestComp128LE:
66 ; CHECK: # %bb.0: # %entry
67 ; CHECK-NEXT: pushq %rax
68 ; CHECK-NEXT: .cfi_def_cfa_offset 16
69 ; CHECK-NEXT: callq __letf2
70 ; CHECK-NEXT: xorl %ecx, %ecx
71 ; CHECK-NEXT: testl %eax, %eax
72 ; CHECK-NEXT: setle %cl
73 ; CHECK-NEXT: movl %ecx, %eax
74 ; CHECK-NEXT: popq %rcx
75 ; CHECK-NEXT: .cfi_def_cfa_offset 8
78 %cmp = fcmp ole fp128 %d1, %d2
79 %conv = zext i1 %cmp to i32
83 define i32 @TestComp128EQ(fp128 %d1, fp128 %d2) {
84 ; CHECK-LABEL: TestComp128EQ:
85 ; CHECK: # %bb.0: # %entry
86 ; CHECK-NEXT: pushq %rax
87 ; CHECK-NEXT: .cfi_def_cfa_offset 16
88 ; CHECK-NEXT: callq __eqtf2
89 ; CHECK-NEXT: xorl %ecx, %ecx
90 ; CHECK-NEXT: testl %eax, %eax
91 ; CHECK-NEXT: sete %cl
92 ; CHECK-NEXT: movl %ecx, %eax
93 ; CHECK-NEXT: popq %rcx
94 ; CHECK-NEXT: .cfi_def_cfa_offset 8
97 %cmp = fcmp oeq fp128 %d1, %d2
98 %conv = zext i1 %cmp to i32
102 define i32 @TestComp128NE(fp128 %d1, fp128 %d2) {
103 ; CHECK-LABEL: TestComp128NE:
104 ; CHECK: # %bb.0: # %entry
105 ; CHECK-NEXT: pushq %rax
106 ; CHECK-NEXT: .cfi_def_cfa_offset 16
107 ; CHECK-NEXT: callq __netf2
108 ; CHECK-NEXT: xorl %ecx, %ecx
109 ; CHECK-NEXT: testl %eax, %eax
110 ; CHECK-NEXT: setne %cl
111 ; CHECK-NEXT: movl %ecx, %eax
112 ; CHECK-NEXT: popq %rcx
113 ; CHECK-NEXT: .cfi_def_cfa_offset 8
116 %cmp = fcmp une fp128 %d1, %d2
117 %conv = zext i1 %cmp to i32
121 define fp128 @TestMax(fp128 %x, fp128 %y) {
122 ; CHECK-LABEL: TestMax:
123 ; CHECK: # %bb.0: # %entry
124 ; CHECK-NEXT: subq $40, %rsp
125 ; CHECK-NEXT: .cfi_def_cfa_offset 48
126 ; CHECK-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
127 ; CHECK-NEXT: movaps %xmm1, (%rsp) # 16-byte Spill
128 ; CHECK-NEXT: callq __gttf2
129 ; CHECK-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
130 ; CHECK-NEXT: testl %eax, %eax
131 ; CHECK-NEXT: jg .LBB6_2
132 ; CHECK-NEXT: # %bb.1: # %entry
133 ; CHECK-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
134 ; CHECK-NEXT: .LBB6_2: # %entry
135 ; CHECK-NEXT: addq $40, %rsp
136 ; CHECK-NEXT: .cfi_def_cfa_offset 8
139 %cmp = fcmp ogt fp128 %x, %y
140 %cond = select i1 %cmp, fp128 %x, fp128 %y