| blob | ebcbd62b82c4a5c05c359e2b0999e38c66422739 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE42
4 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
7 ; PR6399
9 define <2 x i32> @_mul2xi32a(<2 x i32>, <2 x i32>) {
10 ; SSE-LABEL: _mul2xi32a:
11 ; SSE: # %bb.0:
12 ; SSE-NEXT: pmuludq %xmm1, %xmm0
13 ; SSE-NEXT: retq
14 ;
15 ; AVX-LABEL: _mul2xi32a:
16 ; AVX: # %bb.0:
17 ; AVX-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
18 ; AVX-NEXT: retq
19 %r = mul <2 x i32> %0, %1
20 ret <2 x i32> %r
21 }
23 define <2 x i32> @_mul2xi32b(<2 x i32>, <2 x i32>) {
24 ; SSE2-LABEL: _mul2xi32b:
25 ; SSE2: # %bb.0:
26 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
27 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
28 ; SSE2-NEXT: retq
29 ;
30 ; SSE42-LABEL: _mul2xi32b:
31 ; SSE42: # %bb.0:
32 ; SSE42-NEXT: pmuludq %xmm1, %xmm0
33 ; SSE42-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
34 ; SSE42-NEXT: retq
35 ;
36 ; AVX-LABEL: _mul2xi32b:
37 ; AVX: # %bb.0:
38 ; AVX-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
39 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
40 ; AVX-NEXT: retq
41 %factor0 = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
42 %factor1 = shufflevector <2 x i32> %1, <2 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
43 %product64 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %factor0, <4 x i32> %factor1) readnone
44 %product = bitcast <2 x i64> %product64 to <4 x i32>
45 %r = shufflevector <4 x i32> %product, <4 x i32> undef, <2 x i32> <i32 0, i32 4>
46 ret <2 x i32> %r
47 }
49 define <4 x i32> @_mul4xi32a(<4 x i32>, <4 x i32>) {
50 ; SSE2-LABEL: _mul4xi32a:
51 ; SSE2: # %bb.0:
52 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
53 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
54 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
55 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
56 ; SSE2-NEXT: pmuludq %xmm2, %xmm1
57 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
58 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
59 ; SSE2-NEXT: retq
60 ;
61 ; SSE42-LABEL: _mul4xi32a:
62 ; SSE42: # %bb.0:
63 ; SSE42-NEXT: pmulld %xmm1, %xmm0
64 ; SSE42-NEXT: retq
65 ;
66 ; AVX-LABEL: _mul4xi32a:
67 ; AVX: # %bb.0:
68 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
69 ; AVX-NEXT: retq
70 %r = mul <4 x i32> %0, %1
71 ret <4 x i32> %r
72 }
74 define <4 x i32> @_mul4xi32b(<4 x i32>, <4 x i32>) {
75 ; SSE2-LABEL: _mul4xi32b:
76 ; SSE2: # %bb.0:
77 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
78 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
79 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
80 ; SSE2-NEXT: pmuludq %xmm2, %xmm1
81 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
82 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
83 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
84 ; SSE2-NEXT: retq
85 ;
86 ; SSE42-LABEL: _mul4xi32b:
87 ; SSE42: # %bb.0:
88 ; SSE42-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
89 ; SSE42-NEXT: pmuludq %xmm1, %xmm0
90 ; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
91 ; SSE42-NEXT: pmuludq %xmm2, %xmm1
92 ; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,2,2]
93 ; SSE42-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
94 ; SSE42-NEXT: retq
95 ;
96 ; AVX1-LABEL: _mul4xi32b:
97 ; AVX1: # %bb.0:
98 ; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
99 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
100 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
101 ; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
102 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
103 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]
104 ; AVX1-NEXT: retq
105 ;
106 ; AVX2-LABEL: _mul4xi32b:
107 ; AVX2: # %bb.0:
108 ; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
109 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
110 ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
111 ; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
112 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,2,2]
113 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]
114 ; AVX2-NEXT: retq
115 %even0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
116 %even1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
117 %evenMul64 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %even0, <4 x i32> %even1) readnone
118 %evenMul = bitcast <2 x i64> %evenMul64 to <4 x i32>
119 %odd0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
120 %odd1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
121 %oddMul64 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %odd0, <4 x i32> %odd1) readnone
122 %oddMul = bitcast <2 x i64> %oddMul64 to <4 x i32>
123 %r = shufflevector <4 x i32> %evenMul, <4 x i32> %oddMul, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
124 ret <4 x i32> %r
125 }
127 ; the following extractelement's and insertelement's
128 ; are just an unrolled 'zext' on a vector
129 ; %ext0 = zext <4 x i32> %0 to <4 x i64>
130 ; %ext1 = zext <4 x i32> %1 to <4 x i64>
131 define <4 x i64> @_mul4xi32toi64a(<4 x i32>, <4 x i32>) {
132 ; SSE2-LABEL: _mul4xi32toi64a:
133 ; SSE2: # %bb.0:
134 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[0,1,1,3]
135 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3]
136 ; SSE2-NEXT: pmuludq %xmm3, %xmm2
137 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,1,3,3]
138 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,1,3,3]
139 ; SSE2-NEXT: pmuludq %xmm3, %xmm1
140 ; SSE2-NEXT: movdqa %xmm2, %xmm0
141 ; SSE2-NEXT: retq
142 ;
143 ; SSE42-LABEL: _mul4xi32toi64a:
144 ; SSE42: # %bb.0:
145 ; SSE42-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
146 ; SSE42-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
147 ; SSE42-NEXT: pmuludq %xmm3, %xmm2
148 ; SSE42-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,2,3,3]
149 ; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,2,3,3]
150 ; SSE42-NEXT: pmuludq %xmm3, %xmm1
151 ; SSE42-NEXT: movdqa %xmm2, %xmm0
152 ; SSE42-NEXT: retq
153 ;
154 ; AVX1-LABEL: _mul4xi32toi64a:
155 ; AVX1: # %bb.0:
156 ; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
157 ; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[2,2,3,3]
158 ; AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
159 ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
160 ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
161 ; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
162 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
163 ; AVX1-NEXT: retq
164 ;
165 ; AVX2-LABEL: _mul4xi32toi64a:
166 ; AVX2: # %bb.0:
167 ; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
168 ; AVX2-NEXT: vpmovzxdq {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
169 ; AVX2-NEXT: vpmuludq %ymm1, %ymm0, %ymm0
170 ; AVX2-NEXT: retq
171 %f00 = extractelement <4 x i32> %0, i32 0
172 %f01 = extractelement <4 x i32> %0, i32 1
173 %f02 = extractelement <4 x i32> %0, i32 2
174 %f03 = extractelement <4 x i32> %0, i32 3
175 %f10 = extractelement <4 x i32> %1, i32 0
176 %f11 = extractelement <4 x i32> %1, i32 1
177 %f12 = extractelement <4 x i32> %1, i32 2
178 %f13 = extractelement <4 x i32> %1, i32 3
179 %ext00 = zext i32 %f00 to i64
180 %ext01 = zext i32 %f01 to i64
181 %ext02 = zext i32 %f02 to i64
182 %ext03 = zext i32 %f03 to i64
183 %ext10 = zext i32 %f10 to i64
184 %ext11 = zext i32 %f11 to i64
185 %ext12 = zext i32 %f12 to i64
186 %ext13 = zext i32 %f13 to i64
187 %extv00 = insertelement <4 x i64> undef, i64 %ext00, i32 0
188 %extv01 = insertelement <4 x i64> %extv00, i64 %ext01, i32 1
189 %extv02 = insertelement <4 x i64> %extv01, i64 %ext02, i32 2
190 %extv03 = insertelement <4 x i64> %extv02, i64 %ext03, i32 3
191 %extv10 = insertelement <4 x i64> undef, i64 %ext10, i32 0
192 %extv11 = insertelement <4 x i64> %extv10, i64 %ext11, i32 1
193 %extv12 = insertelement <4 x i64> %extv11, i64 %ext12, i32 2
194 %extv13 = insertelement <4 x i64> %extv12, i64 %ext13, i32 3
195 %r = mul <4 x i64> %extv03, %extv13
196 ret <4 x i64> %r
197 }
199 ; very similar to mul4xi32 above
200 ; there is no bitcast and the final shuffle is a little different
201 define <4 x i64> @_mul4xi32toi64b(<4 x i32>, <4 x i32>) {
202 ; SSE-LABEL: _mul4xi32toi64b:
203 ; SSE: # %bb.0:
204 ; SSE-NEXT: movdqa %xmm0, %xmm2
205 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
206 ; SSE-NEXT: pmuludq %xmm1, %xmm2
207 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
208 ; SSE-NEXT: pmuludq %xmm0, %xmm1
209 ; SSE-NEXT: movdqa %xmm2, %xmm0
210 ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
211 ; SSE-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm1[1]
212 ; SSE-NEXT: movdqa %xmm2, %xmm1
213 ; SSE-NEXT: retq
214 ;
215 ; AVX1-LABEL: _mul4xi32toi64b:
216 ; AVX1: # %bb.0:
217 ; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
218 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
219 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
220 ; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
221 ; AVX1-NEXT: vpunpckhqdq {{.*#+}} xmm1 = xmm2[1],xmm0[1]
222 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
223 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
224 ; AVX1-NEXT: retq
225 ;
226 ; AVX2-LABEL: _mul4xi32toi64b:
227 ; AVX2: # %bb.0:
228 ; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
229 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
230 ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
231 ; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
232 ; AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm1 = xmm2[1],xmm0[1]
233 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
234 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
235 ; AVX2-NEXT: retq
236 %even0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
237 %even1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 2, i32 undef>
238 %evenMul = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %even0, <4 x i32> %even1) readnone
239 %odd0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
240 %odd1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 3, i32 undef>
241 %oddMul = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %odd0, <4 x i32> %odd1) readnone
242 %r = shufflevector <2 x i64> %evenMul, <2 x i64> %oddMul, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
243 ret <4 x i64> %r
244 }
246 ; Here we do not split into even and odd indexed elements
247 ; but into the lower and the upper half of the factor vectors.
248 ; This makes the initial shuffle more complicated,
249 ; but the final shuffle is a no-op.
250 define <4 x i64> @_mul4xi32toi64c(<4 x i32>, <4 x i32>) {
251 ; SSE2-LABEL: _mul4xi32toi64c:
252 ; SSE2: # %bb.0:
253 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,1,1,3]
254 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,1,1,3]
255 ; SSE2-NEXT: pmuludq %xmm3, %xmm2
256 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,3,3]
257 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
258 ; SSE2-NEXT: pmuludq %xmm0, %xmm1
259 ; SSE2-NEXT: movdqa %xmm2, %xmm0
260 ; SSE2-NEXT: retq
261 ;
262 ; SSE42-LABEL: _mul4xi32toi64c:
263 ; SSE42: # %bb.0:
264 ; SSE42-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm0[0],zero,xmm0[1],zero
265 ; SSE42-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero
266 ; SSE42-NEXT: pmuludq %xmm3, %xmm2
267 ; SSE42-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
268 ; SSE42-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
269 ; SSE42-NEXT: pmuludq %xmm0, %xmm1
270 ; SSE42-NEXT: movdqa %xmm2, %xmm0
271 ; SSE42-NEXT: retq
272 ;
273 ; AVX1-LABEL: _mul4xi32toi64c:
274 ; AVX1: # %bb.0:
275 ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
276 ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
277 ; AVX1-NEXT: vpmuludq %xmm3, %xmm2, %xmm2
278 ; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
279 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
280 ; AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
281 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0
282 ; AVX1-NEXT: retq
283 ;
284 ; AVX2-LABEL: _mul4xi32toi64c:
285 ; AVX2: # %bb.0:
286 ; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm0[0],zero,xmm0[1],zero
287 ; AVX2-NEXT: vpmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
288 ; AVX2-NEXT: vpmuludq %xmm3, %xmm2, %xmm2
289 ; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
290 ; AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
291 ; AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
292 ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm2, %ymm0
293 ; AVX2-NEXT: retq
294 %lower0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>
295 %lower1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 undef>
296 %lowerMul = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %lower0, <4 x i32> %lower1) readnone
297 %upper0 = shufflevector <4 x i32> %0, <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 3, i32 undef>
298 %upper1 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 undef, i32 3, i32 undef>
299 %upperMul = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %upper0, <4 x i32> %upper1) readnone
300 %r = shufflevector <2 x i64> %lowerMul, <2 x i64> %upperMul, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
301 ret <4 x i64> %r
302 }
304 ; If we know, that the most significant half of i64 elements are zero,
305 ; then multiplication can be simplified drastically.
306 ; In the following example I assert a zero upper half
307 ; by 'trunc' followed by 'zext'.
308 ;
309 ; the following extractelement's and insertelement's
310 ; are just an unrolled 'trunc' plus 'zext' on a vector
311 ; %trunc0 = trunc <2 x i64> %0 to <2 x i32>
312 ; %trunc1 = trunc <2 x i64> %1 to <2 x i32>
313 ; %ext0 = zext <2 x i32> %0 to <2 x i64>
314 ; %ext1 = zext <2 x i32> %1 to <2 x i64>
315 define <2 x i64> @_mul2xi64toi64a(<2 x i64>, <2 x i64>) {
316 ; SSE-LABEL: _mul2xi64toi64a:
317 ; SSE: # %bb.0:
318 ; SSE-NEXT: pmuludq %xmm1, %xmm0
319 ; SSE-NEXT: retq
320 ;
321 ; AVX-LABEL: _mul2xi64toi64a:
322 ; AVX: # %bb.0:
323 ; AVX-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
324 ; AVX-NEXT: retq
325 %f00 = extractelement <2 x i64> %0, i32 0
326 %f01 = extractelement <2 x i64> %0, i32 1
327 %f10 = extractelement <2 x i64> %1, i32 0
328 %f11 = extractelement <2 x i64> %1, i32 1
329 %trunc00 = trunc i64 %f00 to i32
330 %trunc01 = trunc i64 %f01 to i32
331 %ext00 = zext i32 %trunc00 to i64
332 %ext01 = zext i32 %trunc01 to i64
333 %trunc10 = trunc i64 %f10 to i32
334 %trunc11 = trunc i64 %f11 to i32
335 %ext10 = zext i32 %trunc10 to i64
336 %ext11 = zext i32 %trunc11 to i64
337 %extv00 = insertelement <2 x i64> undef, i64 %ext00, i32 0
338 %extv01 = insertelement <2 x i64> %extv00, i64 %ext01, i32 1
339 %extv10 = insertelement <2 x i64> undef, i64 %ext10, i32 0
340 %extv11 = insertelement <2 x i64> %extv10, i64 %ext11, i32 1
341 %r = mul <2 x i64> %extv01, %extv11
342 ret <2 x i64> %r
343 }
345 define <2 x i64> @_mul2xi64toi64b(<2 x i64>, <2 x i64>) {
346 ; SSE-LABEL: _mul2xi64toi64b:
347 ; SSE: # %bb.0:
348 ; SSE-NEXT: pmuludq %xmm1, %xmm0
349 ; SSE-NEXT: retq
350 ;
351 ; AVX-LABEL: _mul2xi64toi64b:
352 ; AVX: # %bb.0:
353 ; AVX-NEXT: vpmuludq %xmm1, %xmm0, %xmm0
354 ; AVX-NEXT: retq
355 %f0 = bitcast <2 x i64> %0 to <4 x i32>
356 %f1 = bitcast <2 x i64> %1 to <4 x i32>
357 %r = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %f0, <4 x i32> %f1) readnone
358 ret <2 x i64> %r
359 }
361 declare <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32>, <4 x i32>) nounwind readnone