| blob | d4703d894bb9dd9b6257ea809c3b0c1967043887 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=ALL,X64
3 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=ALL,X32
5 ; shift left
7 define i32 @and_signbit_shl(i32 %x, i32* %dst) {
8 ; X64-LABEL: and_signbit_shl:
9 ; X64: # %bb.0:
10 ; X64-NEXT: movl %edi, %eax
11 ; X64-NEXT: shll $8, %eax
12 ; X64-NEXT: andl $-16777216, %eax # imm = 0xFF000000
13 ; X64-NEXT: movl %eax, (%rsi)
14 ; X64-NEXT: retq
15 ;
16 ; X32-LABEL: and_signbit_shl:
17 ; X32: # %bb.0:
18 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
19 ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
20 ; X32-NEXT: shll $24, %eax
21 ; X32-NEXT: movl %eax, (%ecx)
22 ; X32-NEXT: retl
23 %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
24 %r = shl i32 %t0, 8
25 store i32 %r, i32* %dst
26 ret i32 %r
27 }
28 define i32 @and_nosignbit_shl(i32 %x, i32* %dst) {
29 ; X64-LABEL: and_nosignbit_shl:
30 ; X64: # %bb.0:
31 ; X64-NEXT: movl %edi, %eax
32 ; X64-NEXT: shll $8, %eax
33 ; X64-NEXT: andl $-16777216, %eax # imm = 0xFF000000
34 ; X64-NEXT: movl %eax, (%rsi)
35 ; X64-NEXT: retq
36 ;
37 ; X32-LABEL: and_nosignbit_shl:
38 ; X32: # %bb.0:
39 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
40 ; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
41 ; X32-NEXT: shll $24, %eax
42 ; X32-NEXT: movl %eax, (%ecx)
43 ; X32-NEXT: retl
44 %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
45 %r = shl i32 %t0, 8
46 store i32 %r, i32* %dst
47 ret i32 %r
48 }
50 define i32 @or_signbit_shl(i32 %x, i32* %dst) {
51 ; X64-LABEL: or_signbit_shl:
52 ; X64: # %bb.0:
53 ; X64-NEXT: movl %edi, %eax
54 ; X64-NEXT: shll $8, %eax
55 ; X64-NEXT: orl $-16777216, %eax # imm = 0xFF000000
56 ; X64-NEXT: movl %eax, (%rsi)
57 ; X64-NEXT: retq
58 ;
59 ; X32-LABEL: or_signbit_shl:
60 ; X32: # %bb.0:
61 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
62 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
63 ; X32-NEXT: shll $8, %eax
64 ; X32-NEXT: orl $-16777216, %eax # imm = 0xFF000000
65 ; X32-NEXT: movl %eax, (%ecx)
66 ; X32-NEXT: retl
67 %t0 = or i32 %x, 4294901760 ; 0xFFFF0000
68 %r = shl i32 %t0, 8
69 store i32 %r, i32* %dst
70 ret i32 %r
71 }
72 define i32 @or_nosignbit_shl(i32 %x, i32* %dst) {
73 ; X64-LABEL: or_nosignbit_shl:
74 ; X64: # %bb.0:
75 ; X64-NEXT: movl %edi, %eax
76 ; X64-NEXT: shll $8, %eax
77 ; X64-NEXT: orl $-16777216, %eax # imm = 0xFF000000
78 ; X64-NEXT: movl %eax, (%rsi)
79 ; X64-NEXT: retq
80 ;
81 ; X32-LABEL: or_nosignbit_shl:
82 ; X32: # %bb.0:
83 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
84 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
85 ; X32-NEXT: shll $8, %eax
86 ; X32-NEXT: orl $-16777216, %eax # imm = 0xFF000000
87 ; X32-NEXT: movl %eax, (%ecx)
88 ; X32-NEXT: retl
89 %t0 = or i32 %x, 2147418112 ; 0x7FFF0000
90 %r = shl i32 %t0, 8
91 store i32 %r, i32* %dst
92 ret i32 %r
93 }
95 define i32 @xor_signbit_shl(i32 %x, i32* %dst) {
96 ; X64-LABEL: xor_signbit_shl:
97 ; X64: # %bb.0:
98 ; X64-NEXT: movl %edi, %eax
99 ; X64-NEXT: shll $8, %eax
100 ; X64-NEXT: xorl $-16777216, %eax # imm = 0xFF000000
101 ; X64-NEXT: movl %eax, (%rsi)
102 ; X64-NEXT: retq
103 ;
104 ; X32-LABEL: xor_signbit_shl:
105 ; X32: # %bb.0:
106 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
107 ; X32-NEXT: movl $16711680, %eax # imm = 0xFF0000
108 ; X32-NEXT: xorl {{[0-9]+}}(%esp), %eax
109 ; X32-NEXT: shll $8, %eax
110 ; X32-NEXT: movl %eax, (%ecx)
111 ; X32-NEXT: retl
112 %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
113 %r = shl i32 %t0, 8
114 store i32 %r, i32* %dst
115 ret i32 %r
116 }
117 define i32 @xor_nosignbit_shl(i32 %x, i32* %dst) {
118 ; X64-LABEL: xor_nosignbit_shl:
119 ; X64: # %bb.0:
120 ; X64-NEXT: movl %edi, %eax
121 ; X64-NEXT: shll $8, %eax
122 ; X64-NEXT: xorl $-16777216, %eax # imm = 0xFF000000
123 ; X64-NEXT: movl %eax, (%rsi)
124 ; X64-NEXT: retq
125 ;
126 ; X32-LABEL: xor_nosignbit_shl:
127 ; X32: # %bb.0:
128 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
129 ; X32-NEXT: movl $16711680, %eax # imm = 0xFF0000
130 ; X32-NEXT: xorl {{[0-9]+}}(%esp), %eax
131 ; X32-NEXT: shll $8, %eax
132 ; X32-NEXT: movl %eax, (%ecx)
133 ; X32-NEXT: retl
134 %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
135 %r = shl i32 %t0, 8
136 store i32 %r, i32* %dst
137 ret i32 %r
138 }
140 define i32 @add_signbit_shl(i32 %x, i32* %dst) {
141 ; X64-LABEL: add_signbit_shl:
142 ; X64: # %bb.0:
143 ; X64-NEXT: movl %edi, %eax
144 ; X64-NEXT: shll $8, %eax
145 ; X64-NEXT: addl $-16777216, %eax # imm = 0xFF000000
146 ; X64-NEXT: movl %eax, (%rsi)
147 ; X64-NEXT: retq
148 ;
149 ; X32-LABEL: add_signbit_shl:
150 ; X32: # %bb.0:
151 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
152 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
153 ; X32-NEXT: shll $8, %eax
154 ; X32-NEXT: addl $-16777216, %eax # imm = 0xFF000000
155 ; X32-NEXT: movl %eax, (%ecx)
156 ; X32-NEXT: retl
157 %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
158 %r = shl i32 %t0, 8
159 store i32 %r, i32* %dst
160 ret i32 %r
161 }
162 define i32 @add_nosignbit_shl(i32 %x, i32* %dst) {
163 ; X64-LABEL: add_nosignbit_shl:
164 ; X64: # %bb.0:
165 ; X64-NEXT: movl %edi, %eax
166 ; X64-NEXT: shll $8, %eax
167 ; X64-NEXT: addl $-16777216, %eax # imm = 0xFF000000
168 ; X64-NEXT: movl %eax, (%rsi)
169 ; X64-NEXT: retq
170 ;
171 ; X32-LABEL: add_nosignbit_shl:
172 ; X32: # %bb.0:
173 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
174 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
175 ; X32-NEXT: shll $8, %eax
176 ; X32-NEXT: addl $-16777216, %eax # imm = 0xFF000000
177 ; X32-NEXT: movl %eax, (%ecx)
178 ; X32-NEXT: retl
179 %t0 = add i32 %x, 2147418112 ; 0x7FFF0000
180 %r = shl i32 %t0, 8
181 store i32 %r, i32* %dst
182 ret i32 %r
183 }
185 ; logical shift right
187 define i32 @and_signbit_lshr(i32 %x, i32* %dst) {
188 ; X64-LABEL: and_signbit_lshr:
189 ; X64: # %bb.0:
190 ; X64-NEXT: movl %edi, %eax
191 ; X64-NEXT: shrl $8, %eax
192 ; X64-NEXT: andl $16776960, %eax # imm = 0xFFFF00
193 ; X64-NEXT: movl %eax, (%rsi)
194 ; X64-NEXT: retq
195 ;
196 ; X32-LABEL: and_signbit_lshr:
197 ; X32: # %bb.0:
198 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
199 ; X32-NEXT: shll $16, %eax
200 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
201 ; X32-NEXT: shrl $8, %eax
202 ; X32-NEXT: movl %eax, (%ecx)
203 ; X32-NEXT: retl
204 %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
205 %r = lshr i32 %t0, 8
206 store i32 %r, i32* %dst
207 ret i32 %r
208 }
209 define i32 @and_nosignbit_lshr(i32 %x, i32* %dst) {
210 ; X64-LABEL: and_nosignbit_lshr:
211 ; X64: # %bb.0:
212 ; X64-NEXT: movl %edi, %eax
213 ; X64-NEXT: shrl $8, %eax
214 ; X64-NEXT: andl $8388352, %eax # imm = 0x7FFF00
215 ; X64-NEXT: movl %eax, (%rsi)
216 ; X64-NEXT: retq
217 ;
218 ; X32-LABEL: and_nosignbit_lshr:
219 ; X32: # %bb.0:
220 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
221 ; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000
222 ; X32-NEXT: andl {{[0-9]+}}(%esp), %eax
223 ; X32-NEXT: shrl $8, %eax
224 ; X32-NEXT: movl %eax, (%ecx)
225 ; X32-NEXT: retl
226 %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
227 %r = lshr i32 %t0, 8
228 store i32 %r, i32* %dst
229 ret i32 %r
230 }
232 define i32 @or_signbit_lshr(i32 %x, i32* %dst) {
233 ; X64-LABEL: or_signbit_lshr:
234 ; X64: # %bb.0:
235 ; X64-NEXT: movl %edi, %eax
236 ; X64-NEXT: shrl $8, %eax
237 ; X64-NEXT: orl $16776960, %eax # imm = 0xFFFF00
238 ; X64-NEXT: movl %eax, (%rsi)
239 ; X64-NEXT: retq
240 ;
241 ; X32-LABEL: or_signbit_lshr:
242 ; X32: # %bb.0:
243 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
244 ; X32-NEXT: movl $-65536, %eax # imm = 0xFFFF0000
245 ; X32-NEXT: orl {{[0-9]+}}(%esp), %eax
246 ; X32-NEXT: shrl $8, %eax
247 ; X32-NEXT: movl %eax, (%ecx)
248 ; X32-NEXT: retl
249 %t0 = or i32 %x, 4294901760 ; 0xFFFF0000
250 %r = lshr i32 %t0, 8
251 store i32 %r, i32* %dst
252 ret i32 %r
253 }
254 define i32 @or_nosignbit_lshr(i32 %x, i32* %dst) {
255 ; X64-LABEL: or_nosignbit_lshr:
256 ; X64: # %bb.0:
257 ; X64-NEXT: movl %edi, %eax
258 ; X64-NEXT: shrl $8, %eax
259 ; X64-NEXT: orl $8388352, %eax # imm = 0x7FFF00
260 ; X64-NEXT: movl %eax, (%rsi)
261 ; X64-NEXT: retq
262 ;
263 ; X32-LABEL: or_nosignbit_lshr:
264 ; X32: # %bb.0:
265 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
266 ; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000
267 ; X32-NEXT: orl {{[0-9]+}}(%esp), %eax
268 ; X32-NEXT: shrl $8, %eax
269 ; X32-NEXT: movl %eax, (%ecx)
270 ; X32-NEXT: retl
271 %t0 = or i32 %x, 2147418112 ; 0x7FFF0000
272 %r = lshr i32 %t0, 8
273 store i32 %r, i32* %dst
274 ret i32 %r
275 }
277 define i32 @xor_signbit_lshr(i32 %x, i32* %dst) {
278 ; X64-LABEL: xor_signbit_lshr:
279 ; X64: # %bb.0:
280 ; X64-NEXT: movl %edi, %eax
281 ; X64-NEXT: shrl $8, %eax
282 ; X64-NEXT: xorl $16776960, %eax # imm = 0xFFFF00
283 ; X64-NEXT: movl %eax, (%rsi)
284 ; X64-NEXT: retq
285 ;
286 ; X32-LABEL: xor_signbit_lshr:
287 ; X32: # %bb.0:
288 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
289 ; X32-NEXT: movl $-65536, %eax # imm = 0xFFFF0000
290 ; X32-NEXT: xorl {{[0-9]+}}(%esp), %eax
291 ; X32-NEXT: shrl $8, %eax
292 ; X32-NEXT: movl %eax, (%ecx)
293 ; X32-NEXT: retl
294 %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
295 %r = lshr i32 %t0, 8
296 store i32 %r, i32* %dst
297 ret i32 %r
298 }
299 define i32 @xor_nosignbit_lshr(i32 %x, i32* %dst) {
300 ; X64-LABEL: xor_nosignbit_lshr:
301 ; X64: # %bb.0:
302 ; X64-NEXT: movl %edi, %eax
303 ; X64-NEXT: shrl $8, %eax
304 ; X64-NEXT: xorl $8388352, %eax # imm = 0x7FFF00
305 ; X64-NEXT: movl %eax, (%rsi)
306 ; X64-NEXT: retq
307 ;
308 ; X32-LABEL: xor_nosignbit_lshr:
309 ; X32: # %bb.0:
310 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
311 ; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000
312 ; X32-NEXT: xorl {{[0-9]+}}(%esp), %eax
313 ; X32-NEXT: shrl $8, %eax
314 ; X32-NEXT: movl %eax, (%ecx)
315 ; X32-NEXT: retl
316 %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
317 %r = lshr i32 %t0, 8
318 store i32 %r, i32* %dst
319 ret i32 %r
320 }
322 define i32 @add_signbit_lshr(i32 %x, i32* %dst) {
323 ; X64-LABEL: add_signbit_lshr:
324 ; X64: # %bb.0:
325 ; X64-NEXT: movl %edi, %eax
326 ; X64-NEXT: addl $-65536, %eax # imm = 0xFFFF0000
327 ; X64-NEXT: shrl $8, %eax
328 ; X64-NEXT: movl %eax, (%rsi)
329 ; X64-NEXT: retq
330 ;
331 ; X32-LABEL: add_signbit_lshr:
332 ; X32: # %bb.0:
333 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
334 ; X32-NEXT: movl $-65536, %eax # imm = 0xFFFF0000
335 ; X32-NEXT: addl {{[0-9]+}}(%esp), %eax
336 ; X32-NEXT: shrl $8, %eax
337 ; X32-NEXT: movl %eax, (%ecx)
338 ; X32-NEXT: retl
339 %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
340 %r = lshr i32 %t0, 8
341 store i32 %r, i32* %dst
342 ret i32 %r
343 }
344 define i32 @add_nosignbit_lshr(i32 %x, i32* %dst) {
345 ; X64-LABEL: add_nosignbit_lshr:
346 ; X64: # %bb.0:
347 ; X64-NEXT: movl %edi, %eax
348 ; X64-NEXT: addl $2147418112, %eax # imm = 0x7FFF0000
349 ; X64-NEXT: shrl $8, %eax
350 ; X64-NEXT: movl %eax, (%rsi)
351 ; X64-NEXT: retq
352 ;
353 ; X32-LABEL: add_nosignbit_lshr:
354 ; X32: # %bb.0:
355 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
356 ; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000
357 ; X32-NEXT: addl {{[0-9]+}}(%esp), %eax
358 ; X32-NEXT: shrl $8, %eax
359 ; X32-NEXT: movl %eax, (%ecx)
360 ; X32-NEXT: retl
361 %t0 = add i32 %x, 2147418112 ; 0x7FFF0000
362 %r = lshr i32 %t0, 8
363 store i32 %r, i32* %dst
364 ret i32 %r
365 }
367 ; arithmetic shift right
369 define i32 @and_signbit_ashr(i32 %x, i32* %dst) {
370 ; X64-LABEL: and_signbit_ashr:
371 ; X64: # %bb.0:
372 ; X64-NEXT: movl %edi, %eax
373 ; X64-NEXT: sarl $8, %eax
374 ; X64-NEXT: andl $-256, %eax
375 ; X64-NEXT: movl %eax, (%rsi)
376 ; X64-NEXT: retq
377 ;
378 ; X32-LABEL: and_signbit_ashr:
379 ; X32: # %bb.0:
380 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
381 ; X32-NEXT: movswl {{[0-9]+}}(%esp), %eax
382 ; X32-NEXT: shll $8, %eax
383 ; X32-NEXT: movl %eax, (%ecx)
384 ; X32-NEXT: retl
385 %t0 = and i32 %x, 4294901760 ; 0xFFFF0000
386 %r = ashr i32 %t0, 8
387 store i32 %r, i32* %dst
388 ret i32 %r
389 }
390 define i32 @and_nosignbit_ashr(i32 %x, i32* %dst) {
391 ; X64-LABEL: and_nosignbit_ashr:
392 ; X64: # %bb.0:
393 ; X64-NEXT: movl %edi, %eax
394 ; X64-NEXT: shrl $8, %eax
395 ; X64-NEXT: andl $8388352, %eax # imm = 0x7FFF00
396 ; X64-NEXT: movl %eax, (%rsi)
397 ; X64-NEXT: retq
398 ;
399 ; X32-LABEL: and_nosignbit_ashr:
400 ; X32: # %bb.0:
401 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
402 ; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000
403 ; X32-NEXT: andl {{[0-9]+}}(%esp), %eax
404 ; X32-NEXT: shrl $8, %eax
405 ; X32-NEXT: movl %eax, (%ecx)
406 ; X32-NEXT: retl
407 %t0 = and i32 %x, 2147418112 ; 0x7FFF0000
408 %r = ashr i32 %t0, 8
409 store i32 %r, i32* %dst
410 ret i32 %r
411 }
413 define i32 @or_signbit_ashr(i32 %x, i32* %dst) {
414 ; X64-LABEL: or_signbit_ashr:
415 ; X64: # %bb.0:
416 ; X64-NEXT: movl %edi, %eax
417 ; X64-NEXT: shrl $8, %eax
418 ; X64-NEXT: orl $-256, %eax
419 ; X64-NEXT: movl %eax, (%rsi)
420 ; X64-NEXT: retq
421 ;
422 ; X32-LABEL: or_signbit_ashr:
423 ; X32: # %bb.0:
424 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
425 ; X32-NEXT: movl $-65536, %eax # imm = 0xFFFF0000
426 ; X32-NEXT: orl {{[0-9]+}}(%esp), %eax
427 ; X32-NEXT: sarl $8, %eax
428 ; X32-NEXT: movl %eax, (%ecx)
429 ; X32-NEXT: retl
430 %t0 = or i32 %x, 4294901760 ; 0xFFFF0000
431 %r = ashr i32 %t0, 8
432 store i32 %r, i32* %dst
433 ret i32 %r
434 }
435 define i32 @or_nosignbit_ashr(i32 %x, i32* %dst) {
436 ; X64-LABEL: or_nosignbit_ashr:
437 ; X64: # %bb.0:
438 ; X64-NEXT: movl %edi, %eax
439 ; X64-NEXT: sarl $8, %eax
440 ; X64-NEXT: orl $8388352, %eax # imm = 0x7FFF00
441 ; X64-NEXT: movl %eax, (%rsi)
442 ; X64-NEXT: retq
443 ;
444 ; X32-LABEL: or_nosignbit_ashr:
445 ; X32: # %bb.0:
446 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
447 ; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000
448 ; X32-NEXT: orl {{[0-9]+}}(%esp), %eax
449 ; X32-NEXT: sarl $8, %eax
450 ; X32-NEXT: movl %eax, (%ecx)
451 ; X32-NEXT: retl
452 %t0 = or i32 %x, 2147418112 ; 0x7FFF0000
453 %r = ashr i32 %t0, 8
454 store i32 %r, i32* %dst
455 ret i32 %r
456 }
458 define i32 @xor_signbit_ashr(i32 %x, i32* %dst) {
459 ; X64-LABEL: xor_signbit_ashr:
460 ; X64: # %bb.0:
461 ; X64-NEXT: movl %edi, %eax
462 ; X64-NEXT: sarl $8, %eax
463 ; X64-NEXT: xorl $-256, %eax
464 ; X64-NEXT: movl %eax, (%rsi)
465 ; X64-NEXT: retq
466 ;
467 ; X32-LABEL: xor_signbit_ashr:
468 ; X32: # %bb.0:
469 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
470 ; X32-NEXT: movl $-65536, %eax # imm = 0xFFFF0000
471 ; X32-NEXT: xorl {{[0-9]+}}(%esp), %eax
472 ; X32-NEXT: sarl $8, %eax
473 ; X32-NEXT: movl %eax, (%ecx)
474 ; X32-NEXT: retl
475 %t0 = xor i32 %x, 4294901760 ; 0xFFFF0000
476 %r = ashr i32 %t0, 8
477 store i32 %r, i32* %dst
478 ret i32 %r
479 }
480 define i32 @xor_nosignbit_ashr(i32 %x, i32* %dst) {
481 ; X64-LABEL: xor_nosignbit_ashr:
482 ; X64: # %bb.0:
483 ; X64-NEXT: movl %edi, %eax
484 ; X64-NEXT: sarl $8, %eax
485 ; X64-NEXT: xorl $8388352, %eax # imm = 0x7FFF00
486 ; X64-NEXT: movl %eax, (%rsi)
487 ; X64-NEXT: retq
488 ;
489 ; X32-LABEL: xor_nosignbit_ashr:
490 ; X32: # %bb.0:
491 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
492 ; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000
493 ; X32-NEXT: xorl {{[0-9]+}}(%esp), %eax
494 ; X32-NEXT: sarl $8, %eax
495 ; X32-NEXT: movl %eax, (%ecx)
496 ; X32-NEXT: retl
497 %t0 = xor i32 %x, 2147418112 ; 0x7FFF0000
498 %r = ashr i32 %t0, 8
499 store i32 %r, i32* %dst
500 ret i32 %r
501 }
503 define i32 @add_signbit_ashr(i32 %x, i32* %dst) {
504 ; X64-LABEL: add_signbit_ashr:
505 ; X64: # %bb.0:
506 ; X64-NEXT: movl %edi, %eax
507 ; X64-NEXT: addl $-65536, %eax # imm = 0xFFFF0000
508 ; X64-NEXT: sarl $8, %eax
509 ; X64-NEXT: movl %eax, (%rsi)
510 ; X64-NEXT: retq
511 ;
512 ; X32-LABEL: add_signbit_ashr:
513 ; X32: # %bb.0:
514 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
515 ; X32-NEXT: movl $-65536, %eax # imm = 0xFFFF0000
516 ; X32-NEXT: addl {{[0-9]+}}(%esp), %eax
517 ; X32-NEXT: sarl $8, %eax
518 ; X32-NEXT: movl %eax, (%ecx)
519 ; X32-NEXT: retl
520 %t0 = add i32 %x, 4294901760 ; 0xFFFF0000
521 %r = ashr i32 %t0, 8
522 store i32 %r, i32* %dst
523 ret i32 %r
524 }
525 define i32 @add_nosignbit_ashr(i32 %x, i32* %dst) {
526 ; X64-LABEL: add_nosignbit_ashr:
527 ; X64: # %bb.0:
528 ; X64-NEXT: movl %edi, %eax
529 ; X64-NEXT: addl $2147418112, %eax # imm = 0x7FFF0000
530 ; X64-NEXT: sarl $8, %eax
531 ; X64-NEXT: movl %eax, (%rsi)
532 ; X64-NEXT: retq
533 ;
534 ; X32-LABEL: add_nosignbit_ashr:
535 ; X32: # %bb.0:
536 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
537 ; X32-NEXT: movl $2147418112, %eax # imm = 0x7FFF0000
538 ; X32-NEXT: addl {{[0-9]+}}(%esp), %eax
539 ; X32-NEXT: sarl $8, %eax
540 ; X32-NEXT: movl %eax, (%ecx)
541 ; X32-NEXT: retl
542 %t0 = add i32 %x, 2147418112 ; 0x7FFF0000
543 %r = ashr i32 %t0, 8
544 store i32 %r, i32* %dst
545 ret i32 %r
546 }