| blob | aaeb54dd72e759f5b627f7c3babd6c944b332d4b |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512DQ
9 ; AVX1 has support for 256-bit bitwise logic because the FP variants were included.
10 ; If using those ops requires extra insert/extract though, it's probably not worth it.
12 define <8 x i32> @PR32790(<8 x i32> %a, <8 x i32> %b, <8 x i32> %c, <8 x i32> %d) {
13 ; SSE-LABEL: PR32790:
14 ; SSE: # %bb.0:
15 ; SSE-NEXT: paddd %xmm2, %xmm0
16 ; SSE-NEXT: paddd %xmm3, %xmm1
17 ; SSE-NEXT: pand %xmm5, %xmm1
18 ; SSE-NEXT: pand %xmm4, %xmm0
19 ; SSE-NEXT: psubd %xmm6, %xmm0
20 ; SSE-NEXT: psubd %xmm7, %xmm1
21 ; SSE-NEXT: retq
22 ;
23 ; AVX1-LABEL: PR32790:
24 ; AVX1: # %bb.0:
25 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm4
26 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
27 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
28 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
29 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm1
30 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
31 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm1
32 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
33 ; AVX1-NEXT: vpand %xmm2, %xmm4, %xmm1
34 ; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1
35 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
36 ; AVX1-NEXT: retq
37 ;
38 ; AVX2-LABEL: PR32790:
39 ; AVX2: # %bb.0:
40 ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
41 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
42 ; AVX2-NEXT: vpsubd %ymm3, %ymm0, %ymm0
43 ; AVX2-NEXT: retq
44 ;
45 ; AVX512-LABEL: PR32790:
46 ; AVX512: # %bb.0:
47 ; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0
48 ; AVX512-NEXT: vpand %ymm2, %ymm0, %ymm0
49 ; AVX512-NEXT: vpsubd %ymm3, %ymm0, %ymm0
50 ; AVX512-NEXT: retq
51 %add = add <8 x i32> %a, %b
52 %and = and <8 x i32> %add, %c
53 %sub = sub <8 x i32> %and, %d
54 ret <8 x i32> %sub
55 }
57 ; In a more extreme case, even the later AVX targets should avoid extract/insert just
58 ; because 256-bit ops are supported.
60 define <4 x i32> @do_not_use_256bit_op(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) {
61 ; SSE-LABEL: do_not_use_256bit_op:
62 ; SSE: # %bb.0:
63 ; SSE-NEXT: pand %xmm2, %xmm0
64 ; SSE-NEXT: pand %xmm3, %xmm1
65 ; SSE-NEXT: psubd %xmm1, %xmm0
66 ; SSE-NEXT: retq
67 ;
68 ; AVX-LABEL: do_not_use_256bit_op:
69 ; AVX: # %bb.0:
70 ; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0
71 ; AVX-NEXT: vpand %xmm3, %xmm1, %xmm1
72 ; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0
73 ; AVX-NEXT: retq
74 %concat1 = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
75 %concat2 = shufflevector <4 x i32> %c, <4 x i32> %d, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
76 %and = and <8 x i32> %concat1, %concat2
77 %extract1 = shufflevector <8 x i32> %and, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
78 %extract2 = shufflevector <8 x i32> %and, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
79 %sub = sub <4 x i32> %extract1, %extract2
80 ret <4 x i32> %sub
81 }
83 ; When extracting from a vector binop, the source width should be a multiple of the destination width.
84 ; https://bugs.llvm.org/show_bug.cgi?id=39511
86 define <3 x float> @PR39511(<4 x float> %t0, <3 x float>* %b) {
87 ; SSE-LABEL: PR39511:
88 ; SSE: # %bb.0:
89 ; SSE-NEXT: addps {{.*}}(%rip), %xmm0
90 ; SSE-NEXT: retq
91 ;
92 ; AVX-LABEL: PR39511:
93 ; AVX: # %bb.0:
94 ; AVX-NEXT: vaddps {{.*}}(%rip), %xmm0, %xmm0
95 ; AVX-NEXT: retq
96 %add = fadd <4 x float> %t0, <float 1.0, float 2.0, float 3.0, float 4.0>
97 %ext = shufflevector <4 x float> %add, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
98 ret <3 x float> %ext
99 }
101 ; When extracting from a vector binop, we need to be extracting
102 ; by a width of at least 1 of the original vector elements.
103 ; https://bugs.llvm.org/show_bug.cgi?id=39893
105 define <2 x i8> @PR39893(<2 x i32> %x, <8 x i8> %y) {
106 ; SSE-LABEL: PR39893:
107 ; SSE: # %bb.0:
108 ; SSE-NEXT: pxor %xmm2, %xmm2
109 ; SSE-NEXT: psubd %xmm0, %xmm2
110 ; SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7]
111 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm1[2,3]
112 ; SSE-NEXT: movaps %xmm2, %xmm0
113 ; SSE-NEXT: retq
114 ;
115 ; AVX1-LABEL: PR39893:
116 ; AVX1: # %bb.0:
117 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
118 ; AVX1-NEXT: vpsubd %xmm0, %xmm2, %xmm0
119 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2],zero,xmm0[3],zero,xmm0[2],zero,xmm0[3],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero
120 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
121 ; AVX1-NEXT: retq
122 ;
123 ; AVX2-LABEL: PR39893:
124 ; AVX2: # %bb.0:
125 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
126 ; AVX2-NEXT: vpsubd %xmm0, %xmm2, %xmm0
127 ; AVX2-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2],zero,xmm0[3],zero,xmm0[2],zero,xmm0[3],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero
128 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
129 ; AVX2-NEXT: retq
130 ;
131 ; AVX512-LABEL: PR39893:
132 ; AVX512: # %bb.0:
133 ; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2
134 ; AVX512-NEXT: vpsubd %xmm0, %xmm2, %xmm0
135 ; AVX512-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[2],zero,xmm0[3],zero,xmm0[2],zero,xmm0[3],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero
136 ; AVX512-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]
137 ; AVX512-NEXT: retq
138 %sub = sub <2 x i32> <i32 0, i32 undef>, %x
139 %bc = bitcast <2 x i32> %sub to <8 x i8>
140 %shuffle = shufflevector <8 x i8> %y, <8 x i8> %bc, <2 x i32> <i32 10, i32 4>
141 ret <2 x i8> %shuffle
142 }
144 define <2 x i8> @PR39893_2(<2 x float> %x) {
145 ; SSE-LABEL: PR39893_2:
146 ; SSE: # %bb.0:
147 ; SSE-NEXT: xorps %xmm1, %xmm1
148 ; SSE-NEXT: subps %xmm0, %xmm1
149 ; SSE-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3],xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
150 ; SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
151 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,1,3]
152 ; SSE-NEXT: retq
153 ;
154 ; AVX-LABEL: PR39893_2:
155 ; AVX: # %bb.0:
156 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
157 ; AVX-NEXT: vsubps %xmm0, %xmm1, %xmm0
158 ; AVX-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
159 ; AVX-NEXT: retq
160 %fsub = fsub <2 x float> zeroinitializer, %x
161 %bc = bitcast <2 x float> %fsub to <8 x i8>
162 %shuffle = shufflevector <8 x i8> %bc, <8 x i8> undef, <2 x i32> <i32 0, i32 1>
163 ret <2 x i8> %shuffle
164 }
166 define <4 x double> @fmul_v2f64(<2 x double> %x, <2 x double> %y) {
167 ; SSE-LABEL: fmul_v2f64:
168 ; SSE: # %bb.0:
169 ; SSE-NEXT: movapd %xmm1, %xmm2
170 ; SSE-NEXT: unpcklpd {{.*#+}} xmm2 = xmm2[0],xmm0[0]
171 ; SSE-NEXT: unpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
172 ; SSE-NEXT: mulpd %xmm0, %xmm0
173 ; SSE-NEXT: mulpd %xmm2, %xmm2
174 ; SSE-NEXT: addpd %xmm0, %xmm2
175 ; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
176 ; SSE-NEXT: movapd %xmm2, %xmm0
177 ; SSE-NEXT: retq
178 ;
179 ; AVX1-LABEL: fmul_v2f64:
180 ; AVX1: # %bb.0:
181 ; AVX1-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm1[0],xmm0[0]
182 ; AVX1-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
183 ; AVX1-NEXT: vmulpd %xmm0, %xmm0, %xmm0
184 ; AVX1-NEXT: vmulpd %xmm2, %xmm2, %xmm1
185 ; AVX1-NEXT: vaddpd %xmm0, %xmm1, %xmm0
186 ; AVX1-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
187 ; AVX1-NEXT: retq
188 ;
189 ; AVX2-LABEL: fmul_v2f64:
190 ; AVX2: # %bb.0:
191 ; AVX2-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm1[0],xmm0[0]
192 ; AVX2-NEXT: vunpckhpd {{.*#+}} xmm0 = xmm0[1],xmm1[1]
193 ; AVX2-NEXT: vmulpd %xmm0, %xmm0, %xmm0
194 ; AVX2-NEXT: vmulpd %xmm2, %xmm2, %xmm1
195 ; AVX2-NEXT: vaddpd %xmm0, %xmm1, %xmm0
196 ; AVX2-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
197 ; AVX2-NEXT: retq
198 ;
199 ; AVX512-LABEL: fmul_v2f64:
200 ; AVX512: # %bb.0:
201 ; AVX512-NEXT: vunpckhpd {{.*#+}} xmm2 = xmm0[1],xmm1[1]
202 ; AVX512-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm1[0],xmm0[0]
203 ; AVX512-NEXT: vmulpd %xmm0, %xmm0, %xmm0
204 ; AVX512-NEXT: vfmadd231pd {{.*#+}} xmm0 = (xmm2 * xmm2) + xmm0
205 ; AVX512-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
206 ; AVX512-NEXT: retq
207 %s = shufflevector <2 x double> %x, <2 x double> %y, <4 x i32> <i32 2, i32 0, i32 1, i32 3>
208 %bo = fmul fast <4 x double> %s, %s
209 %ext = shufflevector <4 x double> %bo, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
210 %add = fadd fast <4 x double> %bo, %ext
211 %rdx = shufflevector <4 x double> %add, <4 x double> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
212 ret <4 x double> %rdx
213 }