| blob | e4f676cecd6f4312097c1da6bd51f8212a62a691 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512DQ
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
5 ;
6 ; Variable Shifts
7 ;
9 define <8 x i64> @var_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {
10 ; ALL-LABEL: var_shift_v8i64:
11 ; ALL: # %bb.0:
12 ; ALL-NEXT: vpsravq %zmm1, %zmm0, %zmm0
13 ; ALL-NEXT: retq
14 %shift = ashr <8 x i64> %a, %b
15 ret <8 x i64> %shift
16 }
18 define <16 x i32> @var_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {
19 ; ALL-LABEL: var_shift_v16i32:
20 ; ALL: # %bb.0:
21 ; ALL-NEXT: vpsravd %zmm1, %zmm0, %zmm0
22 ; ALL-NEXT: retq
23 %shift = ashr <16 x i32> %a, %b
24 ret <16 x i32> %shift
25 }
27 define <32 x i16> @var_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {
28 ; AVX512DQ-LABEL: var_shift_v32i16:
29 ; AVX512DQ: # %bb.0:
30 ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm2[0],zero,ymm2[1],zero,ymm2[2],zero,ymm2[3],zero,ymm2[4],zero,ymm2[5],zero,ymm2[6],zero,ymm2[7],zero,ymm2[8],zero,ymm2[9],zero,ymm2[10],zero,ymm2[11],zero,ymm2[12],zero,ymm2[13],zero,ymm2[14],zero,ymm2[15],zero
31 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
32 ; AVX512DQ-NEXT: vpsravd %zmm2, %zmm0, %zmm0
33 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0
34 ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero
35 ; AVX512DQ-NEXT: vpmovsxwd %ymm1, %zmm1
36 ; AVX512DQ-NEXT: vpsravd %zmm2, %zmm1, %zmm1
37 ; AVX512DQ-NEXT: vpmovdw %zmm1, %ymm1
38 ; AVX512DQ-NEXT: retq
39 ;
40 ; AVX512BW-LABEL: var_shift_v32i16:
41 ; AVX512BW: # %bb.0:
42 ; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0
43 ; AVX512BW-NEXT: retq
44 %shift = ashr <32 x i16> %a, %b
45 ret <32 x i16> %shift
46 }
48 define <64 x i8> @var_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
49 ; AVX512DQ-LABEL: var_shift_v64i8:
50 ; AVX512DQ: # %bb.0:
51 ; AVX512DQ-NEXT: vpsllw $5, %ymm2, %ymm2
52 ; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15],ymm0[24],ymm2[24],ymm0[25],ymm2[25],ymm0[26],ymm2[26],ymm0[27],ymm2[27],ymm0[28],ymm2[28],ymm0[29],ymm2[29],ymm0[30],ymm2[30],ymm0[31],ymm2[31]
53 ; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm5 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
54 ; AVX512DQ-NEXT: vpsraw $4, %ymm5, %ymm6
55 ; AVX512DQ-NEXT: vpblendvb %ymm4, %ymm6, %ymm5, %ymm5
56 ; AVX512DQ-NEXT: vpsraw $2, %ymm5, %ymm6
57 ; AVX512DQ-NEXT: vpaddw %ymm4, %ymm4, %ymm4
58 ; AVX512DQ-NEXT: vpblendvb %ymm4, %ymm6, %ymm5, %ymm5
59 ; AVX512DQ-NEXT: vpsraw $1, %ymm5, %ymm6
60 ; AVX512DQ-NEXT: vpaddw %ymm4, %ymm4, %ymm4
61 ; AVX512DQ-NEXT: vpblendvb %ymm4, %ymm6, %ymm5, %ymm4
62 ; AVX512DQ-NEXT: vpsrlw $8, %ymm4, %ymm4
63 ; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm2 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[16],ymm2[16],ymm0[17],ymm2[17],ymm0[18],ymm2[18],ymm0[19],ymm2[19],ymm0[20],ymm2[20],ymm0[21],ymm2[21],ymm0[22],ymm2[22],ymm0[23],ymm2[23]
64 ; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
65 ; AVX512DQ-NEXT: vpsraw $4, %ymm0, %ymm5
66 ; AVX512DQ-NEXT: vpblendvb %ymm2, %ymm5, %ymm0, %ymm0
67 ; AVX512DQ-NEXT: vpsraw $2, %ymm0, %ymm5
68 ; AVX512DQ-NEXT: vpaddw %ymm2, %ymm2, %ymm2
69 ; AVX512DQ-NEXT: vpblendvb %ymm2, %ymm5, %ymm0, %ymm0
70 ; AVX512DQ-NEXT: vpsraw $1, %ymm0, %ymm5
71 ; AVX512DQ-NEXT: vpaddw %ymm2, %ymm2, %ymm2
72 ; AVX512DQ-NEXT: vpblendvb %ymm2, %ymm5, %ymm0, %ymm0
73 ; AVX512DQ-NEXT: vpsrlw $8, %ymm0, %ymm0
74 ; AVX512DQ-NEXT: vpackuswb %ymm4, %ymm0, %ymm0
75 ; AVX512DQ-NEXT: vpsllw $5, %ymm3, %ymm2
76 ; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15],ymm0[24],ymm2[24],ymm0[25],ymm2[25],ymm0[26],ymm2[26],ymm0[27],ymm2[27],ymm0[28],ymm2[28],ymm0[29],ymm2[29],ymm0[30],ymm2[30],ymm0[31],ymm2[31]
77 ; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
78 ; AVX512DQ-NEXT: vpsraw $4, %ymm4, %ymm5
79 ; AVX512DQ-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm4
80 ; AVX512DQ-NEXT: vpsraw $2, %ymm4, %ymm5
81 ; AVX512DQ-NEXT: vpaddw %ymm3, %ymm3, %ymm3
82 ; AVX512DQ-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm4
83 ; AVX512DQ-NEXT: vpsraw $1, %ymm4, %ymm5
84 ; AVX512DQ-NEXT: vpaddw %ymm3, %ymm3, %ymm3
85 ; AVX512DQ-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm3
86 ; AVX512DQ-NEXT: vpsrlw $8, %ymm3, %ymm3
87 ; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm2 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[16],ymm2[16],ymm0[17],ymm2[17],ymm0[18],ymm2[18],ymm0[19],ymm2[19],ymm0[20],ymm2[20],ymm0[21],ymm2[21],ymm0[22],ymm2[22],ymm0[23],ymm2[23]
88 ; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
89 ; AVX512DQ-NEXT: vpsraw $4, %ymm1, %ymm4
90 ; AVX512DQ-NEXT: vpblendvb %ymm2, %ymm4, %ymm1, %ymm1
91 ; AVX512DQ-NEXT: vpsraw $2, %ymm1, %ymm4
92 ; AVX512DQ-NEXT: vpaddw %ymm2, %ymm2, %ymm2
93 ; AVX512DQ-NEXT: vpblendvb %ymm2, %ymm4, %ymm1, %ymm1
94 ; AVX512DQ-NEXT: vpsraw $1, %ymm1, %ymm4
95 ; AVX512DQ-NEXT: vpaddw %ymm2, %ymm2, %ymm2
96 ; AVX512DQ-NEXT: vpblendvb %ymm2, %ymm4, %ymm1, %ymm1
97 ; AVX512DQ-NEXT: vpsrlw $8, %ymm1, %ymm1
98 ; AVX512DQ-NEXT: vpackuswb %ymm3, %ymm1, %ymm1
99 ; AVX512DQ-NEXT: retq
100 ;
101 ; AVX512BW-LABEL: var_shift_v64i8:
102 ; AVX512BW: # %bb.0:
103 ; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
104 ; AVX512BW-NEXT: vpsraw $4, %zmm2, %zmm3
105 ; AVX512BW-NEXT: vpsllw $5, %zmm1, %zmm1
106 ; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm4 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
107 ; AVX512BW-NEXT: vpmovb2m %zmm4, %k1
108 ; AVX512BW-NEXT: vmovdqu8 %zmm3, %zmm2 {%k1}
109 ; AVX512BW-NEXT: vpsraw $2, %zmm2, %zmm3
110 ; AVX512BW-NEXT: vpaddw %zmm4, %zmm4, %zmm4
111 ; AVX512BW-NEXT: vpmovb2m %zmm4, %k1
112 ; AVX512BW-NEXT: vmovdqu8 %zmm3, %zmm2 {%k1}
113 ; AVX512BW-NEXT: vpsraw $1, %zmm2, %zmm3
114 ; AVX512BW-NEXT: vpaddw %zmm4, %zmm4, %zmm4
115 ; AVX512BW-NEXT: vpmovb2m %zmm4, %k1
116 ; AVX512BW-NEXT: vmovdqu8 %zmm3, %zmm2 {%k1}
117 ; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2
118 ; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
119 ; AVX512BW-NEXT: vpsraw $4, %zmm0, %zmm3
120 ; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm1 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
121 ; AVX512BW-NEXT: vpmovb2m %zmm1, %k1
122 ; AVX512BW-NEXT: vmovdqu8 %zmm3, %zmm0 {%k1}
123 ; AVX512BW-NEXT: vpsraw $2, %zmm0, %zmm3
124 ; AVX512BW-NEXT: vpaddw %zmm1, %zmm1, %zmm1
125 ; AVX512BW-NEXT: vpmovb2m %zmm1, %k1
126 ; AVX512BW-NEXT: vmovdqu8 %zmm3, %zmm0 {%k1}
127 ; AVX512BW-NEXT: vpsraw $1, %zmm0, %zmm3
128 ; AVX512BW-NEXT: vpaddw %zmm1, %zmm1, %zmm1
129 ; AVX512BW-NEXT: vpmovb2m %zmm1, %k1
130 ; AVX512BW-NEXT: vmovdqu8 %zmm3, %zmm0 {%k1}
131 ; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
132 ; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0
133 ; AVX512BW-NEXT: retq
134 %shift = ashr <64 x i8> %a, %b
135 ret <64 x i8> %shift
136 }
138 ;
139 ; Uniform Variable Shifts
140 ;
142 define <8 x i64> @splatvar_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {
143 ; ALL-LABEL: splatvar_shift_v8i64:
144 ; ALL: # %bb.0:
145 ; ALL-NEXT: vpsraq %xmm1, %zmm0, %zmm0
146 ; ALL-NEXT: retq
147 %splat = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
148 %shift = ashr <8 x i64> %a, %splat
149 ret <8 x i64> %shift
150 }
152 define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {
153 ; ALL-LABEL: splatvar_shift_v16i32:
154 ; ALL: # %bb.0:
155 ; ALL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
156 ; ALL-NEXT: vpsrad %xmm1, %zmm0, %zmm0
157 ; ALL-NEXT: retq
158 %splat = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer
159 %shift = ashr <16 x i32> %a, %splat
160 ret <16 x i32> %shift
161 }
163 define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {
164 ; AVX512DQ-LABEL: splatvar_shift_v32i16:
165 ; AVX512DQ: # %bb.0:
166 ; AVX512DQ-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
167 ; AVX512DQ-NEXT: vpsraw %xmm2, %ymm0, %ymm0
168 ; AVX512DQ-NEXT: vpsraw %xmm2, %ymm1, %ymm1
169 ; AVX512DQ-NEXT: retq
170 ;
171 ; AVX512BW-LABEL: splatvar_shift_v32i16:
172 ; AVX512BW: # %bb.0:
173 ; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
174 ; AVX512BW-NEXT: vpsraw %xmm1, %zmm0, %zmm0
175 ; AVX512BW-NEXT: retq
176 %splat = shufflevector <32 x i16> %b, <32 x i16> undef, <32 x i32> zeroinitializer
177 %shift = ashr <32 x i16> %a, %splat
178 ret <32 x i16> %shift
179 }
181 define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
182 ; AVX512DQ-LABEL: splatvar_shift_v64i8:
183 ; AVX512DQ: # %bb.0:
184 ; AVX512DQ-NEXT: vpmovzxbq {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,zero,zero,zero,zero,xmm2[1],zero,zero,zero,zero,zero,zero,zero
185 ; AVX512DQ-NEXT: vpsrlw %xmm2, %ymm0, %ymm0
186 ; AVX512DQ-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3
187 ; AVX512DQ-NEXT: vpsrlw %xmm2, %xmm3, %xmm3
188 ; AVX512DQ-NEXT: vpsrlw $8, %xmm3, %xmm3
189 ; AVX512DQ-NEXT: vpbroadcastb %xmm3, %ymm3
190 ; AVX512DQ-NEXT: vpand %ymm3, %ymm0, %ymm0
191 ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm4 = [32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896]
192 ; AVX512DQ-NEXT: vpsrlw %xmm2, %ymm4, %ymm4
193 ; AVX512DQ-NEXT: vpxor %ymm4, %ymm0, %ymm0
194 ; AVX512DQ-NEXT: vpsubb %ymm4, %ymm0, %ymm0
195 ; AVX512DQ-NEXT: vpsrlw %xmm2, %ymm1, %ymm1
196 ; AVX512DQ-NEXT: vpand %ymm3, %ymm1, %ymm1
197 ; AVX512DQ-NEXT: vpxor %ymm4, %ymm1, %ymm1
198 ; AVX512DQ-NEXT: vpsubb %ymm4, %ymm1, %ymm1
199 ; AVX512DQ-NEXT: retq
200 ;
201 ; AVX512BW-LABEL: splatvar_shift_v64i8:
202 ; AVX512BW: # %bb.0:
203 ; AVX512BW-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
204 ; AVX512BW-NEXT: vpsrlw %xmm1, %zmm0, %zmm0
205 ; AVX512BW-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
206 ; AVX512BW-NEXT: vpsrlw %xmm1, %xmm2, %xmm2
207 ; AVX512BW-NEXT: vpsrlw $8, %xmm2, %xmm2
208 ; AVX512BW-NEXT: vpbroadcastb %xmm2, %zmm2
209 ; AVX512BW-NEXT: vpandq %zmm2, %zmm0, %zmm0
210 ; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm2 = [32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896,32896]
211 ; AVX512BW-NEXT: vpsrlw %xmm1, %zmm2, %zmm1
212 ; AVX512BW-NEXT: vpxorq %zmm1, %zmm0, %zmm0
213 ; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
214 ; AVX512BW-NEXT: retq
215 %splat = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
216 %shift = ashr <64 x i8> %a, %splat
217 ret <64 x i8> %shift
218 }
220 ;
221 ; Constant Shifts
222 ;
224 define <8 x i64> @constant_shift_v8i64(<8 x i64> %a) nounwind {
225 ; ALL-LABEL: constant_shift_v8i64:
226 ; ALL: # %bb.0:
227 ; ALL-NEXT: vpsravq {{.*}}(%rip), %zmm0, %zmm0
228 ; ALL-NEXT: retq
229 %shift = ashr <8 x i64> %a, <i64 1, i64 7, i64 31, i64 62, i64 1, i64 7, i64 31, i64 62>
230 ret <8 x i64> %shift
231 }
233 define <16 x i32> @constant_shift_v16i32(<16 x i32> %a) nounwind {
234 ; ALL-LABEL: constant_shift_v16i32:
235 ; ALL: # %bb.0:
236 ; ALL-NEXT: vpsravd {{.*}}(%rip), %zmm0, %zmm0
237 ; ALL-NEXT: retq
238 %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7>
239 ret <16 x i32> %shift
240 }
242 define <32 x i16> @constant_shift_v32i16(<32 x i16> %a) nounwind {
243 ; AVX512DQ-LABEL: constant_shift_v32i16:
244 ; AVX512DQ: # %bb.0:
245 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
246 ; AVX512DQ-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
247 ; AVX512DQ-NEXT: vpsravd %zmm2, %zmm0, %zmm0
248 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0
249 ; AVX512DQ-NEXT: vpmovsxwd %ymm1, %zmm1
250 ; AVX512DQ-NEXT: vpsravd %zmm2, %zmm1, %zmm1
251 ; AVX512DQ-NEXT: vpmovdw %zmm1, %ymm1
252 ; AVX512DQ-NEXT: retq
253 ;
254 ; AVX512BW-LABEL: constant_shift_v32i16:
255 ; AVX512BW: # %bb.0:
256 ; AVX512BW-NEXT: vpsravw {{.*}}(%rip), %zmm0, %zmm0
257 ; AVX512BW-NEXT: retq
258 %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
259 ret <32 x i16> %shift
260 }
262 define <64 x i8> @constant_shift_v64i8(<64 x i8> %a) nounwind {
263 ; AVX512DQ-LABEL: constant_shift_v64i8:
264 ; AVX512DQ: # %bb.0:
265 ; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
266 ; AVX512DQ-NEXT: vpsraw $8, %ymm2, %ymm2
267 ; AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [2,4,8,16,32,64,128,256,2,4,8,16,32,64,128,256]
268 ; AVX512DQ-NEXT: # ymm3 = mem[0,1,0,1]
269 ; AVX512DQ-NEXT: vpmullw %ymm3, %ymm2, %ymm2
270 ; AVX512DQ-NEXT: vpsrlw $8, %ymm2, %ymm2
271 ; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
272 ; AVX512DQ-NEXT: vpsraw $8, %ymm0, %ymm0
273 ; AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm4 = [256,128,64,32,16,8,4,2,256,128,64,32,16,8,4,2]
274 ; AVX512DQ-NEXT: # ymm4 = mem[0,1,0,1]
275 ; AVX512DQ-NEXT: vpmullw %ymm4, %ymm0, %ymm0
276 ; AVX512DQ-NEXT: vpsrlw $8, %ymm0, %ymm0
277 ; AVX512DQ-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
278 ; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
279 ; AVX512DQ-NEXT: vpsraw $8, %ymm2, %ymm2
280 ; AVX512DQ-NEXT: vpmullw %ymm3, %ymm2, %ymm2
281 ; AVX512DQ-NEXT: vpsrlw $8, %ymm2, %ymm2
282 ; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
283 ; AVX512DQ-NEXT: vpsraw $8, %ymm1, %ymm1
284 ; AVX512DQ-NEXT: vpmullw %ymm4, %ymm1, %ymm1
285 ; AVX512DQ-NEXT: vpsrlw $8, %ymm1, %ymm1
286 ; AVX512DQ-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
287 ; AVX512DQ-NEXT: retq
288 ;
289 ; AVX512BW-LABEL: constant_shift_v64i8:
290 ; AVX512BW: # %bb.0:
291 ; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm1 = zmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
292 ; AVX512BW-NEXT: vpsraw $8, %zmm1, %zmm1
293 ; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm1, %zmm1
294 ; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
295 ; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
296 ; AVX512BW-NEXT: vpsraw $8, %zmm0, %zmm0
297 ; AVX512BW-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0
298 ; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
299 ; AVX512BW-NEXT: vpackuswb %zmm1, %zmm0, %zmm0
300 ; AVX512BW-NEXT: retq
301 %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
302 ret <64 x i8> %shift
303 }
305 ;
306 ; Uniform Constant Shifts
307 ;
309 define <8 x i64> @splatconstant_shift_v8i64(<8 x i64> %a) nounwind {
310 ; ALL-LABEL: splatconstant_shift_v8i64:
311 ; ALL: # %bb.0:
312 ; ALL-NEXT: vpsraq $7, %zmm0, %zmm0
313 ; ALL-NEXT: retq
314 %shift = ashr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>
315 ret <8 x i64> %shift
316 }
318 define <16 x i32> @splatconstant_shift_v16i32(<16 x i32> %a) nounwind {
319 ; ALL-LABEL: splatconstant_shift_v16i32:
320 ; ALL: # %bb.0:
321 ; ALL-NEXT: vpsrad $5, %zmm0, %zmm0
322 ; ALL-NEXT: retq
323 %shift = ashr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
324 ret <16 x i32> %shift
325 }
327 define <32 x i16> @splatconstant_shift_v32i16(<32 x i16> %a) nounwind {
328 ; AVX512DQ-LABEL: splatconstant_shift_v32i16:
329 ; AVX512DQ: # %bb.0:
330 ; AVX512DQ-NEXT: vpsraw $3, %ymm0, %ymm0
331 ; AVX512DQ-NEXT: vpsraw $3, %ymm1, %ymm1
332 ; AVX512DQ-NEXT: retq
333 ;
334 ; AVX512BW-LABEL: splatconstant_shift_v32i16:
335 ; AVX512BW: # %bb.0:
336 ; AVX512BW-NEXT: vpsraw $3, %zmm0, %zmm0
337 ; AVX512BW-NEXT: retq
338 %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
339 ret <32 x i16> %shift
340 }
342 define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) nounwind {
343 ; AVX512DQ-LABEL: splatconstant_shift_v64i8:
344 ; AVX512DQ: # %bb.0:
345 ; AVX512DQ-NEXT: vpsrlw $3, %ymm0, %ymm0
346 ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31]
347 ; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm0
348 ; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
349 ; AVX512DQ-NEXT: vpxor %ymm3, %ymm0, %ymm0
350 ; AVX512DQ-NEXT: vpsubb %ymm3, %ymm0, %ymm0
351 ; AVX512DQ-NEXT: vpsrlw $3, %ymm1, %ymm1
352 ; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1
353 ; AVX512DQ-NEXT: vpxor %ymm3, %ymm1, %ymm1
354 ; AVX512DQ-NEXT: vpsubb %ymm3, %ymm1, %ymm1
355 ; AVX512DQ-NEXT: retq
356 ;
357 ; AVX512BW-LABEL: splatconstant_shift_v64i8:
358 ; AVX512BW: # %bb.0:
359 ; AVX512BW-NEXT: vpsrlw $3, %zmm0, %zmm0
360 ; AVX512BW-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
361 ; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
362 ; AVX512BW-NEXT: vpxorq %zmm1, %zmm0, %zmm0
363 ; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
364 ; AVX512BW-NEXT: retq
365 %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
366 ret <64 x i8> %shift
367 }
369 define <64 x i8> @ashr_const7_v64i8(<64 x i8> %a) {
370 ; AVX512DQ-LABEL: ashr_const7_v64i8:
371 ; AVX512DQ: # %bb.0:
372 ; AVX512DQ-NEXT: vpxor %xmm2, %xmm2, %xmm2
373 ; AVX512DQ-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0
374 ; AVX512DQ-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm1
375 ; AVX512DQ-NEXT: retq
376 ;
377 ; AVX512BW-LABEL: ashr_const7_v64i8:
378 ; AVX512BW: # %bb.0:
379 ; AVX512BW-NEXT: vpmovb2m %zmm0, %k0
380 ; AVX512BW-NEXT: vpmovm2b %k0, %zmm0
381 ; AVX512BW-NEXT: retq
382 %res = ashr <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
383 ret <64 x i8> %res
384 }