| blob | 1d663839a10efaa7b828d11b6dd83f95e5cd8568 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX1
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX2
8 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512DQ
9 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
10 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL --check-prefix=AVX512DQVL
11 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL --check-prefix=AVX512BWVL
12 ;
13 ; Just one 32-bit run to make sure we do reasonable things for i64 shifts.
14 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=X32-SSE --check-prefix=X32-SSE2
16 ;
17 ; Variable Shifts
18 ;
20 define <2 x i32> @var_shift_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
21 ; SSE2-LABEL: var_shift_v2i32:
22 ; SSE2: # %bb.0:
23 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
24 ; SSE2-NEXT: movdqa %xmm0, %xmm2
25 ; SSE2-NEXT: psllq %xmm1, %xmm2
26 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
27 ; SSE2-NEXT: psllq %xmm1, %xmm0
28 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
29 ; SSE2-NEXT: retq
30 ;
31 ; SSE41-LABEL: var_shift_v2i32:
32 ; SSE41: # %bb.0:
33 ; SSE41-NEXT: pxor %xmm2, %xmm2
34 ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
35 ; SSE41-NEXT: movdqa %xmm0, %xmm1
36 ; SSE41-NEXT: psllq %xmm2, %xmm1
37 ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
38 ; SSE41-NEXT: psllq %xmm2, %xmm0
39 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
40 ; SSE41-NEXT: retq
41 ;
42 ; AVX1-LABEL: var_shift_v2i32:
43 ; AVX1: # %bb.0:
44 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
45 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
46 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm2
47 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
48 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0
49 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
50 ; AVX1-NEXT: retq
51 ;
52 ; AVX2-LABEL: var_shift_v2i32:
53 ; AVX2: # %bb.0:
54 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
55 ; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
56 ; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
57 ; AVX2-NEXT: retq
58 ;
59 ; XOPAVX1-LABEL: var_shift_v2i32:
60 ; XOPAVX1: # %bb.0:
61 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
62 ; XOPAVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
63 ; XOPAVX1-NEXT: vpshlq %xmm1, %xmm0, %xmm0
64 ; XOPAVX1-NEXT: retq
65 ;
66 ; XOPAVX2-LABEL: var_shift_v2i32:
67 ; XOPAVX2: # %bb.0:
68 ; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
69 ; XOPAVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
70 ; XOPAVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
71 ; XOPAVX2-NEXT: retq
72 ;
73 ; AVX512-LABEL: var_shift_v2i32:
74 ; AVX512: # %bb.0:
75 ; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2
76 ; AVX512-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
77 ; AVX512-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
78 ; AVX512-NEXT: retq
79 ;
80 ; AVX512VL-LABEL: var_shift_v2i32:
81 ; AVX512VL: # %bb.0:
82 ; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
83 ; AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
84 ; AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
85 ; AVX512VL-NEXT: retq
86 ;
87 ; X32-SSE-LABEL: var_shift_v2i32:
88 ; X32-SSE: # %bb.0:
89 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
90 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
91 ; X32-SSE-NEXT: psllq %xmm1, %xmm2
92 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
93 ; X32-SSE-NEXT: xorps %xmm3, %xmm3
94 ; X32-SSE-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
95 ; X32-SSE-NEXT: psllq %xmm3, %xmm0
96 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
97 ; X32-SSE-NEXT: retl
98 %shift = shl <2 x i32> %a, %b
99 ret <2 x i32> %shift
100 }
102 define <4 x i16> @var_shift_v4i16(<4 x i16> %a, <4 x i16> %b) nounwind {
103 ; SSE2-LABEL: var_shift_v4i16:
104 ; SSE2: # %bb.0:
105 ; SSE2-NEXT: pslld $23, %xmm1
106 ; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
107 ; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
108 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
109 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
110 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
111 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
112 ; SSE2-NEXT: pmuludq %xmm2, %xmm1
113 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
114 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
115 ; SSE2-NEXT: retq
116 ;
117 ; SSE41-LABEL: var_shift_v4i16:
118 ; SSE41: # %bb.0:
119 ; SSE41-NEXT: pslld $23, %xmm1
120 ; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
121 ; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
122 ; SSE41-NEXT: pmulld %xmm1, %xmm0
123 ; SSE41-NEXT: retq
124 ;
125 ; AVX1-LABEL: var_shift_v4i16:
126 ; AVX1: # %bb.0:
127 ; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
128 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
129 ; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
130 ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0
131 ; AVX1-NEXT: retq
132 ;
133 ; AVX2-LABEL: var_shift_v4i16:
134 ; AVX2: # %bb.0:
135 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
136 ; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
137 ; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
138 ; AVX2-NEXT: retq
139 ;
140 ; XOPAVX1-LABEL: var_shift_v4i16:
141 ; XOPAVX1: # %bb.0:
142 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
143 ; XOPAVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
144 ; XOPAVX1-NEXT: vpshld %xmm1, %xmm0, %xmm0
145 ; XOPAVX1-NEXT: retq
146 ;
147 ; XOPAVX2-LABEL: var_shift_v4i16:
148 ; XOPAVX2: # %bb.0:
149 ; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
150 ; XOPAVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
151 ; XOPAVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
152 ; XOPAVX2-NEXT: retq
153 ;
154 ; AVX512-LABEL: var_shift_v4i16:
155 ; AVX512: # %bb.0:
156 ; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2
157 ; AVX512-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
158 ; AVX512-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
159 ; AVX512-NEXT: retq
160 ;
161 ; AVX512VL-LABEL: var_shift_v4i16:
162 ; AVX512VL: # %bb.0:
163 ; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
164 ; AVX512VL-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
165 ; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
166 ; AVX512VL-NEXT: retq
167 ;
168 ; X32-SSE-LABEL: var_shift_v4i16:
169 ; X32-SSE: # %bb.0:
170 ; X32-SSE-NEXT: pslld $23, %xmm1
171 ; X32-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm1
172 ; X32-SSE-NEXT: cvttps2dq %xmm1, %xmm1
173 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
174 ; X32-SSE-NEXT: pmuludq %xmm1, %xmm0
175 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
176 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
177 ; X32-SSE-NEXT: pmuludq %xmm2, %xmm1
178 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
179 ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
180 ; X32-SSE-NEXT: retl
181 %shift = shl <4 x i16> %a, %b
182 ret <4 x i16> %shift
183 }
185 define <2 x i16> @var_shift_v2i16(<2 x i16> %a, <2 x i16> %b) nounwind {
186 ; SSE2-LABEL: var_shift_v2i16:
187 ; SSE2: # %bb.0:
188 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
189 ; SSE2-NEXT: movdqa %xmm0, %xmm2
190 ; SSE2-NEXT: psllq %xmm1, %xmm2
191 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
192 ; SSE2-NEXT: psllq %xmm1, %xmm0
193 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
194 ; SSE2-NEXT: retq
195 ;
196 ; SSE41-LABEL: var_shift_v2i16:
197 ; SSE41: # %bb.0:
198 ; SSE41-NEXT: pxor %xmm2, %xmm2
199 ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
200 ; SSE41-NEXT: movdqa %xmm0, %xmm1
201 ; SSE41-NEXT: psllq %xmm2, %xmm1
202 ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
203 ; SSE41-NEXT: psllq %xmm2, %xmm0
204 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
205 ; SSE41-NEXT: retq
206 ;
207 ; AVX1-LABEL: var_shift_v2i16:
208 ; AVX1: # %bb.0:
209 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
210 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
211 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm2
212 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
213 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0
214 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
215 ; AVX1-NEXT: retq
216 ;
217 ; AVX2-LABEL: var_shift_v2i16:
218 ; AVX2: # %bb.0:
219 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
220 ; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
221 ; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
222 ; AVX2-NEXT: retq
223 ;
224 ; XOPAVX1-LABEL: var_shift_v2i16:
225 ; XOPAVX1: # %bb.0:
226 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
227 ; XOPAVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
228 ; XOPAVX1-NEXT: vpshlq %xmm1, %xmm0, %xmm0
229 ; XOPAVX1-NEXT: retq
230 ;
231 ; XOPAVX2-LABEL: var_shift_v2i16:
232 ; XOPAVX2: # %bb.0:
233 ; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
234 ; XOPAVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
235 ; XOPAVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
236 ; XOPAVX2-NEXT: retq
237 ;
238 ; AVX512-LABEL: var_shift_v2i16:
239 ; AVX512: # %bb.0:
240 ; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2
241 ; AVX512-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
242 ; AVX512-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
243 ; AVX512-NEXT: retq
244 ;
245 ; AVX512VL-LABEL: var_shift_v2i16:
246 ; AVX512VL: # %bb.0:
247 ; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
248 ; AVX512VL-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
249 ; AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
250 ; AVX512VL-NEXT: retq
251 ;
252 ; X32-SSE-LABEL: var_shift_v2i16:
253 ; X32-SSE: # %bb.0:
254 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
255 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
256 ; X32-SSE-NEXT: psllq %xmm1, %xmm2
257 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
258 ; X32-SSE-NEXT: psllq %xmm1, %xmm0
259 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
260 ; X32-SSE-NEXT: retl
261 %shift = shl <2 x i16> %a, %b
262 ret <2 x i16> %shift
263 }
265 define <8 x i8> @var_shift_v8i8(<8 x i8> %a, <8 x i8> %b) nounwind {
266 ; SSE2-LABEL: var_shift_v8i8:
267 ; SSE2: # %bb.0:
268 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
269 ; SSE2-NEXT: pxor %xmm2, %xmm2
270 ; SSE2-NEXT: movdqa %xmm1, %xmm3
271 ; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
272 ; SSE2-NEXT: pslld $23, %xmm3
273 ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [1065353216,1065353216,1065353216,1065353216]
274 ; SSE2-NEXT: paddd %xmm4, %xmm3
275 ; SSE2-NEXT: cvttps2dq %xmm3, %xmm3
276 ; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7]
277 ; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7]
278 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
279 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
280 ; SSE2-NEXT: pslld $23, %xmm1
281 ; SSE2-NEXT: paddd %xmm4, %xmm1
282 ; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
283 ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
284 ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
285 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
286 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
287 ; SSE2-NEXT: pmullw %xmm1, %xmm0
288 ; SSE2-NEXT: retq
289 ;
290 ; SSE41-LABEL: var_shift_v8i8:
291 ; SSE41: # %bb.0:
292 ; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [255,0,255,0,255,0,255,0,255,0,255,0,255,0,255,0]
293 ; SSE41-NEXT: pand %xmm1, %xmm2
294 ; SSE41-NEXT: pxor %xmm3, %xmm3
295 ; SSE41-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm3[8],xmm1[9],xmm3[9],xmm1[10],xmm3[10],xmm1[11],xmm3[11],xmm1[12],xmm3[12],xmm1[13],xmm3[13],xmm1[14],xmm3[14],xmm1[15],xmm3[15]
296 ; SSE41-NEXT: pslld $23, %xmm1
297 ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
298 ; SSE41-NEXT: paddd %xmm3, %xmm1
299 ; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
300 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero
301 ; SSE41-NEXT: pslld $23, %xmm2
302 ; SSE41-NEXT: paddd %xmm3, %xmm2
303 ; SSE41-NEXT: cvttps2dq %xmm2, %xmm2
304 ; SSE41-NEXT: packusdw %xmm1, %xmm2
305 ; SSE41-NEXT: pmullw %xmm2, %xmm0
306 ; SSE41-NEXT: retq
307 ;
308 ; AVX1-LABEL: var_shift_v8i8:
309 ; AVX1: # %bb.0:
310 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
311 ; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm1[8],xmm2[8],xmm1[9],xmm2[9],xmm1[10],xmm2[10],xmm1[11],xmm2[11],xmm1[12],xmm2[12],xmm1[13],xmm2[13],xmm1[14],xmm2[14],xmm1[15],xmm2[15]
312 ; AVX1-NEXT: vpslld $23, %xmm2, %xmm2
313 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
314 ; AVX1-NEXT: vpaddd %xmm3, %xmm2, %xmm2
315 ; AVX1-NEXT: vcvttps2dq %xmm2, %xmm2
316 ; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
317 ; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
318 ; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1
319 ; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
320 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
321 ; AVX1-NEXT: vpmullw %xmm1, %xmm0, %xmm0
322 ; AVX1-NEXT: retq
323 ;
324 ; AVX2-LABEL: var_shift_v8i8:
325 ; AVX2: # %bb.0:
326 ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
327 ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
328 ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
329 ; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
330 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
331 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
332 ; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
333 ; AVX2-NEXT: vzeroupper
334 ; AVX2-NEXT: retq
335 ;
336 ; XOP-LABEL: var_shift_v8i8:
337 ; XOP: # %bb.0:
338 ; XOP-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
339 ; XOP-NEXT: vpshlw %xmm1, %xmm0, %xmm0
340 ; XOP-NEXT: retq
341 ;
342 ; AVX512DQ-LABEL: var_shift_v8i8:
343 ; AVX512DQ: # %bb.0:
344 ; AVX512DQ-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
345 ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
346 ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
347 ; AVX512DQ-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
348 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0
349 ; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
350 ; AVX512DQ-NEXT: vzeroupper
351 ; AVX512DQ-NEXT: retq
352 ;
353 ; AVX512BW-LABEL: var_shift_v8i8:
354 ; AVX512BW: # %bb.0:
355 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
356 ; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
357 ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
358 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
359 ; AVX512BW-NEXT: vzeroupper
360 ; AVX512BW-NEXT: retq
361 ;
362 ; AVX512DQVL-LABEL: var_shift_v8i8:
363 ; AVX512DQVL: # %bb.0:
364 ; AVX512DQVL-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
365 ; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
366 ; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
367 ; AVX512DQVL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
368 ; AVX512DQVL-NEXT: vpmovdw %ymm0, %xmm0
369 ; AVX512DQVL-NEXT: vzeroupper
370 ; AVX512DQVL-NEXT: retq
371 ;
372 ; AVX512BWVL-LABEL: var_shift_v8i8:
373 ; AVX512BWVL: # %bb.0:
374 ; AVX512BWVL-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
375 ; AVX512BWVL-NEXT: vpsllvw %xmm1, %xmm0, %xmm0
376 ; AVX512BWVL-NEXT: retq
377 ;
378 ; X32-SSE-LABEL: var_shift_v8i8:
379 ; X32-SSE: # %bb.0:
380 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
381 ; X32-SSE-NEXT: pxor %xmm2, %xmm2
382 ; X32-SSE-NEXT: movdqa %xmm1, %xmm3
383 ; X32-SSE-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
384 ; X32-SSE-NEXT: pslld $23, %xmm3
385 ; X32-SSE-NEXT: movdqa {{.*#+}} xmm4 = [1065353216,1065353216,1065353216,1065353216]
386 ; X32-SSE-NEXT: paddd %xmm4, %xmm3
387 ; X32-SSE-NEXT: cvttps2dq %xmm3, %xmm3
388 ; X32-SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7]
389 ; X32-SSE-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7]
390 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
391 ; X32-SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
392 ; X32-SSE-NEXT: pslld $23, %xmm1
393 ; X32-SSE-NEXT: paddd %xmm4, %xmm1
394 ; X32-SSE-NEXT: cvttps2dq %xmm1, %xmm1
395 ; X32-SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
396 ; X32-SSE-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
397 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
398 ; X32-SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
399 ; X32-SSE-NEXT: pmullw %xmm1, %xmm0
400 ; X32-SSE-NEXT: retl
401 %shift = shl <8 x i8> %a, %b
402 ret <8 x i8> %shift
403 }
405 define <4 x i8> @var_shift_v4i8(<4 x i8> %a, <4 x i8> %b) nounwind {
406 ; SSE2-LABEL: var_shift_v4i8:
407 ; SSE2: # %bb.0:
408 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
409 ; SSE2-NEXT: pslld $23, %xmm1
410 ; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
411 ; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
412 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
413 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
414 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
415 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
416 ; SSE2-NEXT: pmuludq %xmm2, %xmm1
417 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
418 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
419 ; SSE2-NEXT: retq
420 ;
421 ; SSE41-LABEL: var_shift_v4i8:
422 ; SSE41: # %bb.0:
423 ; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
424 ; SSE41-NEXT: pslld $23, %xmm1
425 ; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
426 ; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
427 ; SSE41-NEXT: pmulld %xmm1, %xmm0
428 ; SSE41-NEXT: retq
429 ;
430 ; AVX1-LABEL: var_shift_v4i8:
431 ; AVX1: # %bb.0:
432 ; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
433 ; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
434 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
435 ; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
436 ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0
437 ; AVX1-NEXT: retq
438 ;
439 ; AVX2-LABEL: var_shift_v4i8:
440 ; AVX2: # %bb.0:
441 ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
442 ; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
443 ; AVX2-NEXT: retq
444 ;
445 ; XOPAVX1-LABEL: var_shift_v4i8:
446 ; XOPAVX1: # %bb.0:
447 ; XOPAVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
448 ; XOPAVX1-NEXT: vpshld %xmm1, %xmm0, %xmm0
449 ; XOPAVX1-NEXT: retq
450 ;
451 ; XOPAVX2-LABEL: var_shift_v4i8:
452 ; XOPAVX2: # %bb.0:
453 ; XOPAVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
454 ; XOPAVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
455 ; XOPAVX2-NEXT: retq
456 ;
457 ; AVX512-LABEL: var_shift_v4i8:
458 ; AVX512: # %bb.0:
459 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
460 ; AVX512-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
461 ; AVX512-NEXT: retq
462 ;
463 ; AVX512VL-LABEL: var_shift_v4i8:
464 ; AVX512VL: # %bb.0:
465 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
466 ; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
467 ; AVX512VL-NEXT: retq
468 ;
469 ; X32-SSE-LABEL: var_shift_v4i8:
470 ; X32-SSE: # %bb.0:
471 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
472 ; X32-SSE-NEXT: pslld $23, %xmm1
473 ; X32-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm1
474 ; X32-SSE-NEXT: cvttps2dq %xmm1, %xmm1
475 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
476 ; X32-SSE-NEXT: pmuludq %xmm1, %xmm0
477 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
478 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
479 ; X32-SSE-NEXT: pmuludq %xmm2, %xmm1
480 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
481 ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
482 ; X32-SSE-NEXT: retl
483 %shift = shl <4 x i8> %a, %b
484 ret <4 x i8> %shift
485 }
487 define <2 x i8> @var_shift_v2i8(<2 x i8> %a, <2 x i8> %b) nounwind {
488 ; SSE2-LABEL: var_shift_v2i8:
489 ; SSE2: # %bb.0:
490 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
491 ; SSE2-NEXT: movdqa %xmm0, %xmm2
492 ; SSE2-NEXT: psllq %xmm1, %xmm2
493 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
494 ; SSE2-NEXT: psllq %xmm1, %xmm0
495 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
496 ; SSE2-NEXT: retq
497 ;
498 ; SSE41-LABEL: var_shift_v2i8:
499 ; SSE41: # %bb.0:
500 ; SSE41-NEXT: pand {{.*}}(%rip), %xmm1
501 ; SSE41-NEXT: movdqa %xmm0, %xmm2
502 ; SSE41-NEXT: psllq %xmm1, %xmm2
503 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
504 ; SSE41-NEXT: psllq %xmm1, %xmm0
505 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
506 ; SSE41-NEXT: retq
507 ;
508 ; AVX1-LABEL: var_shift_v2i8:
509 ; AVX1: # %bb.0:
510 ; AVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
511 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm2
512 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
513 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0
514 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
515 ; AVX1-NEXT: retq
516 ;
517 ; AVX2-LABEL: var_shift_v2i8:
518 ; AVX2: # %bb.0:
519 ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
520 ; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
521 ; AVX2-NEXT: retq
522 ;
523 ; XOPAVX1-LABEL: var_shift_v2i8:
524 ; XOPAVX1: # %bb.0:
525 ; XOPAVX1-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
526 ; XOPAVX1-NEXT: vpshlq %xmm1, %xmm0, %xmm0
527 ; XOPAVX1-NEXT: retq
528 ;
529 ; XOPAVX2-LABEL: var_shift_v2i8:
530 ; XOPAVX2: # %bb.0:
531 ; XOPAVX2-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
532 ; XOPAVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
533 ; XOPAVX2-NEXT: retq
534 ;
535 ; AVX512-LABEL: var_shift_v2i8:
536 ; AVX512: # %bb.0:
537 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
538 ; AVX512-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
539 ; AVX512-NEXT: retq
540 ;
541 ; AVX512VL-LABEL: var_shift_v2i8:
542 ; AVX512VL: # %bb.0:
543 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
544 ; AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
545 ; AVX512VL-NEXT: retq
546 ;
547 ; X32-SSE-LABEL: var_shift_v2i8:
548 ; X32-SSE: # %bb.0:
549 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
550 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
551 ; X32-SSE-NEXT: psllq %xmm1, %xmm2
552 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
553 ; X32-SSE-NEXT: psllq %xmm1, %xmm0
554 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
555 ; X32-SSE-NEXT: retl
556 %shift = shl <2 x i8> %a, %b
557 ret <2 x i8> %shift
558 }
560 ;
561 ; Uniform Variable Shifts
562 ;
564 define <2 x i32> @splatvar_shift_v2i32(<2 x i32> %a, <2 x i32> %b) nounwind {
565 ; SSE2-LABEL: splatvar_shift_v2i32:
566 ; SSE2: # %bb.0:
567 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
568 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
569 ; SSE2-NEXT: movdqa %xmm0, %xmm2
570 ; SSE2-NEXT: psllq %xmm1, %xmm2
571 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
572 ; SSE2-NEXT: psllq %xmm1, %xmm0
573 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
574 ; SSE2-NEXT: retq
575 ;
576 ; SSE41-LABEL: splatvar_shift_v2i32:
577 ; SSE41: # %bb.0:
578 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
579 ; SSE41-NEXT: pxor %xmm2, %xmm2
580 ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
581 ; SSE41-NEXT: movdqa %xmm0, %xmm1
582 ; SSE41-NEXT: psllq %xmm2, %xmm1
583 ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
584 ; SSE41-NEXT: psllq %xmm2, %xmm0
585 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
586 ; SSE41-NEXT: retq
587 ;
588 ; AVX1-LABEL: splatvar_shift_v2i32:
589 ; AVX1: # %bb.0:
590 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
591 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
592 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
593 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm2
594 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
595 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0
596 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
597 ; AVX1-NEXT: retq
598 ;
599 ; AVX2-LABEL: splatvar_shift_v2i32:
600 ; AVX2: # %bb.0:
601 ; AVX2-NEXT: vpbroadcastq %xmm1, %xmm1
602 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
603 ; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
604 ; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
605 ; AVX2-NEXT: retq
606 ;
607 ; XOPAVX1-LABEL: splatvar_shift_v2i32:
608 ; XOPAVX1: # %bb.0:
609 ; XOPAVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
610 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
611 ; XOPAVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
612 ; XOPAVX1-NEXT: vpshlq %xmm1, %xmm0, %xmm0
613 ; XOPAVX1-NEXT: retq
614 ;
615 ; XOPAVX2-LABEL: splatvar_shift_v2i32:
616 ; XOPAVX2: # %bb.0:
617 ; XOPAVX2-NEXT: vpbroadcastq %xmm1, %xmm1
618 ; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
619 ; XOPAVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
620 ; XOPAVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
621 ; XOPAVX2-NEXT: retq
622 ;
623 ; AVX512-LABEL: splatvar_shift_v2i32:
624 ; AVX512: # %bb.0:
625 ; AVX512-NEXT: vpbroadcastq %xmm1, %xmm1
626 ; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2
627 ; AVX512-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
628 ; AVX512-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
629 ; AVX512-NEXT: retq
630 ;
631 ; AVX512VL-LABEL: splatvar_shift_v2i32:
632 ; AVX512VL: # %bb.0:
633 ; AVX512VL-NEXT: vpbroadcastq %xmm1, %xmm1
634 ; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
635 ; AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
636 ; AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
637 ; AVX512VL-NEXT: retq
638 ;
639 ; X32-SSE-LABEL: splatvar_shift_v2i32:
640 ; X32-SSE: # %bb.0:
641 ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,0,4294967295,0]
642 ; X32-SSE-NEXT: pand %xmm1, %xmm2
643 ; X32-SSE-NEXT: movdqa %xmm0, %xmm3
644 ; X32-SSE-NEXT: psllq %xmm2, %xmm3
645 ; X32-SSE-NEXT: pxor %xmm2, %xmm2
646 ; X32-SSE-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
647 ; X32-SSE-NEXT: psllq %xmm2, %xmm0
648 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm3[0],xmm0[1]
649 ; X32-SSE-NEXT: retl
650 %splat = shufflevector <2 x i32> %b, <2 x i32> undef, <2 x i32> zeroinitializer
651 %shift = shl <2 x i32> %a, %splat
652 ret <2 x i32> %shift
653 }
655 define <4 x i16> @splatvar_shift_v4i16(<4 x i16> %a, <4 x i16> %b) nounwind {
656 ; SSE2-LABEL: splatvar_shift_v4i16:
657 ; SSE2: # %bb.0:
658 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
659 ; SSE2-NEXT: pslld $23, %xmm1
660 ; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
661 ; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
662 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
663 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
664 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
665 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
666 ; SSE2-NEXT: pmuludq %xmm2, %xmm1
667 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
668 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
669 ; SSE2-NEXT: retq
670 ;
671 ; SSE41-LABEL: splatvar_shift_v4i16:
672 ; SSE41: # %bb.0:
673 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
674 ; SSE41-NEXT: pslld $23, %xmm1
675 ; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
676 ; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
677 ; SSE41-NEXT: pmulld %xmm1, %xmm0
678 ; SSE41-NEXT: retq
679 ;
680 ; AVX1-LABEL: splatvar_shift_v4i16:
681 ; AVX1: # %bb.0:
682 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
683 ; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
684 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
685 ; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
686 ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0
687 ; AVX1-NEXT: retq
688 ;
689 ; AVX2-LABEL: splatvar_shift_v4i16:
690 ; AVX2: # %bb.0:
691 ; AVX2-NEXT: vpbroadcastd %xmm1, %xmm1
692 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
693 ; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
694 ; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
695 ; AVX2-NEXT: retq
696 ;
697 ; XOPAVX1-LABEL: splatvar_shift_v4i16:
698 ; XOPAVX1: # %bb.0:
699 ; XOPAVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
700 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
701 ; XOPAVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
702 ; XOPAVX1-NEXT: vpshld %xmm1, %xmm0, %xmm0
703 ; XOPAVX1-NEXT: retq
704 ;
705 ; XOPAVX2-LABEL: splatvar_shift_v4i16:
706 ; XOPAVX2: # %bb.0:
707 ; XOPAVX2-NEXT: vpbroadcastd %xmm1, %xmm1
708 ; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
709 ; XOPAVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
710 ; XOPAVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
711 ; XOPAVX2-NEXT: retq
712 ;
713 ; AVX512-LABEL: splatvar_shift_v4i16:
714 ; AVX512: # %bb.0:
715 ; AVX512-NEXT: vpbroadcastd %xmm1, %xmm1
716 ; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2
717 ; AVX512-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
718 ; AVX512-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
719 ; AVX512-NEXT: retq
720 ;
721 ; AVX512VL-LABEL: splatvar_shift_v4i16:
722 ; AVX512VL: # %bb.0:
723 ; AVX512VL-NEXT: vpbroadcastd %xmm1, %xmm1
724 ; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
725 ; AVX512VL-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3],xmm1[4],xmm2[5],xmm1[6],xmm2[7]
726 ; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
727 ; AVX512VL-NEXT: retq
728 ;
729 ; X32-SSE-LABEL: splatvar_shift_v4i16:
730 ; X32-SSE: # %bb.0:
731 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
732 ; X32-SSE-NEXT: pslld $23, %xmm1
733 ; X32-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm1
734 ; X32-SSE-NEXT: cvttps2dq %xmm1, %xmm1
735 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
736 ; X32-SSE-NEXT: pmuludq %xmm1, %xmm0
737 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
738 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
739 ; X32-SSE-NEXT: pmuludq %xmm2, %xmm1
740 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
741 ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
742 ; X32-SSE-NEXT: retl
743 %splat = shufflevector <4 x i16> %b, <4 x i16> undef, <4 x i32> zeroinitializer
744 %shift = shl <4 x i16> %a, %splat
745 ret <4 x i16> %shift
746 }
748 define <2 x i16> @splatvar_shift_v2i16(<2 x i16> %a, <2 x i16> %b) nounwind {
749 ; SSE2-LABEL: splatvar_shift_v2i16:
750 ; SSE2: # %bb.0:
751 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
752 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
753 ; SSE2-NEXT: movdqa %xmm0, %xmm2
754 ; SSE2-NEXT: psllq %xmm1, %xmm2
755 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
756 ; SSE2-NEXT: psllq %xmm1, %xmm0
757 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
758 ; SSE2-NEXT: retq
759 ;
760 ; SSE41-LABEL: splatvar_shift_v2i16:
761 ; SSE41: # %bb.0:
762 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
763 ; SSE41-NEXT: pxor %xmm2, %xmm2
764 ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
765 ; SSE41-NEXT: movdqa %xmm0, %xmm1
766 ; SSE41-NEXT: psllq %xmm2, %xmm1
767 ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,0,1]
768 ; SSE41-NEXT: psllq %xmm2, %xmm0
769 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
770 ; SSE41-NEXT: retq
771 ;
772 ; AVX1-LABEL: splatvar_shift_v2i16:
773 ; AVX1: # %bb.0:
774 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
775 ; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
776 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
777 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm2
778 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
779 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0
780 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
781 ; AVX1-NEXT: retq
782 ;
783 ; AVX2-LABEL: splatvar_shift_v2i16:
784 ; AVX2: # %bb.0:
785 ; AVX2-NEXT: vpbroadcastq %xmm1, %xmm1
786 ; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
787 ; AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
788 ; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
789 ; AVX2-NEXT: retq
790 ;
791 ; XOPAVX1-LABEL: splatvar_shift_v2i16:
792 ; XOPAVX1: # %bb.0:
793 ; XOPAVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
794 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
795 ; XOPAVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
796 ; XOPAVX1-NEXT: vpshlq %xmm1, %xmm0, %xmm0
797 ; XOPAVX1-NEXT: retq
798 ;
799 ; XOPAVX2-LABEL: splatvar_shift_v2i16:
800 ; XOPAVX2: # %bb.0:
801 ; XOPAVX2-NEXT: vpbroadcastq %xmm1, %xmm1
802 ; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
803 ; XOPAVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
804 ; XOPAVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
805 ; XOPAVX2-NEXT: retq
806 ;
807 ; AVX512-LABEL: splatvar_shift_v2i16:
808 ; AVX512: # %bb.0:
809 ; AVX512-NEXT: vpbroadcastq %xmm1, %xmm1
810 ; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2
811 ; AVX512-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
812 ; AVX512-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
813 ; AVX512-NEXT: retq
814 ;
815 ; AVX512VL-LABEL: splatvar_shift_v2i16:
816 ; AVX512VL: # %bb.0:
817 ; AVX512VL-NEXT: vpbroadcastq %xmm1, %xmm1
818 ; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
819 ; AVX512VL-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3],xmm1[4],xmm2[5,6,7]
820 ; AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
821 ; AVX512VL-NEXT: retq
822 ;
823 ; X32-SSE-LABEL: splatvar_shift_v2i16:
824 ; X32-SSE: # %bb.0:
825 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
826 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
827 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
828 ; X32-SSE-NEXT: psllq %xmm1, %xmm2
829 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
830 ; X32-SSE-NEXT: psllq %xmm1, %xmm0
831 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
832 ; X32-SSE-NEXT: retl
833 %splat = shufflevector <2 x i16> %b, <2 x i16> undef, <2 x i32> zeroinitializer
834 %shift = shl <2 x i16> %a, %splat
835 ret <2 x i16> %shift
836 }
838 define <8 x i8> @splatvar_shift_v8i8(<8 x i8> %a, <8 x i8> %b) nounwind {
839 ; SSE2-LABEL: splatvar_shift_v8i8:
840 ; SSE2: # %bb.0:
841 ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,2,3,4,5,6,7]
842 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
843 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
844 ; SSE2-NEXT: pxor %xmm2, %xmm2
845 ; SSE2-NEXT: movdqa %xmm1, %xmm3
846 ; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
847 ; SSE2-NEXT: pslld $23, %xmm3
848 ; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [1065353216,1065353216,1065353216,1065353216]
849 ; SSE2-NEXT: paddd %xmm4, %xmm3
850 ; SSE2-NEXT: cvttps2dq %xmm3, %xmm3
851 ; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7]
852 ; SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7]
853 ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
854 ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
855 ; SSE2-NEXT: pslld $23, %xmm1
856 ; SSE2-NEXT: paddd %xmm4, %xmm1
857 ; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
858 ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
859 ; SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
860 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
861 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
862 ; SSE2-NEXT: pmullw %xmm1, %xmm0
863 ; SSE2-NEXT: retq
864 ;
865 ; SSE41-LABEL: splatvar_shift_v8i8:
866 ; SSE41: # %bb.0:
867 ; SSE41-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero
868 ; SSE41-NEXT: pmovzxwd {{.*#+}} xmm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
869 ; SSE41-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
870 ; SSE41-NEXT: pslld $23, %xmm1
871 ; SSE41-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
872 ; SSE41-NEXT: paddd %xmm3, %xmm1
873 ; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
874 ; SSE41-NEXT: pslld $23, %xmm2
875 ; SSE41-NEXT: paddd %xmm3, %xmm2
876 ; SSE41-NEXT: cvttps2dq %xmm2, %xmm2
877 ; SSE41-NEXT: packusdw %xmm1, %xmm2
878 ; SSE41-NEXT: pmullw %xmm2, %xmm0
879 ; SSE41-NEXT: retq
880 ;
881 ; AVX1-LABEL: splatvar_shift_v8i8:
882 ; AVX1: # %bb.0:
883 ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero
884 ; AVX1-NEXT: vpunpckhwd {{.*#+}} xmm2 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]
885 ; AVX1-NEXT: vpslld $23, %xmm2, %xmm2
886 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
887 ; AVX1-NEXT: vpaddd %xmm3, %xmm2, %xmm2
888 ; AVX1-NEXT: vcvttps2dq %xmm2, %xmm2
889 ; AVX1-NEXT: vpmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
890 ; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
891 ; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1
892 ; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
893 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
894 ; AVX1-NEXT: vpmullw %xmm1, %xmm0, %xmm0
895 ; AVX1-NEXT: retq
896 ;
897 ; AVX2-LABEL: splatvar_shift_v8i8:
898 ; AVX2: # %bb.0:
899 ; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero
900 ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
901 ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
902 ; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
903 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
904 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
905 ; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
906 ; AVX2-NEXT: vzeroupper
907 ; AVX2-NEXT: retq
908 ;
909 ; XOP-LABEL: splatvar_shift_v8i8:
910 ; XOP: # %bb.0:
911 ; XOP-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero
912 ; XOP-NEXT: vpshlw %xmm1, %xmm0, %xmm0
913 ; XOP-NEXT: retq
914 ;
915 ; AVX512DQ-LABEL: splatvar_shift_v8i8:
916 ; AVX512DQ: # %bb.0:
917 ; AVX512DQ-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero
918 ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
919 ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
920 ; AVX512DQ-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
921 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0
922 ; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
923 ; AVX512DQ-NEXT: vzeroupper
924 ; AVX512DQ-NEXT: retq
925 ;
926 ; AVX512BW-LABEL: splatvar_shift_v8i8:
927 ; AVX512BW: # %bb.0:
928 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
929 ; AVX512BW-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero
930 ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
931 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
932 ; AVX512BW-NEXT: vzeroupper
933 ; AVX512BW-NEXT: retq
934 ;
935 ; AVX512DQVL-LABEL: splatvar_shift_v8i8:
936 ; AVX512DQVL: # %bb.0:
937 ; AVX512DQVL-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero
938 ; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
939 ; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
940 ; AVX512DQVL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
941 ; AVX512DQVL-NEXT: vpmovdw %ymm0, %xmm0
942 ; AVX512DQVL-NEXT: vzeroupper
943 ; AVX512DQVL-NEXT: retq
944 ;
945 ; AVX512BWVL-LABEL: splatvar_shift_v8i8:
946 ; AVX512BWVL: # %bb.0:
947 ; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero,xmm1[0],zero
948 ; AVX512BWVL-NEXT: vpsllvw %xmm1, %xmm0, %xmm0
949 ; AVX512BWVL-NEXT: retq
950 ;
951 ; X32-SSE-LABEL: splatvar_shift_v8i8:
952 ; X32-SSE: # %bb.0:
953 ; X32-SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,2,3,4,5,6,7]
954 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
955 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
956 ; X32-SSE-NEXT: pxor %xmm2, %xmm2
957 ; X32-SSE-NEXT: movdqa %xmm1, %xmm3
958 ; X32-SSE-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
959 ; X32-SSE-NEXT: pslld $23, %xmm3
960 ; X32-SSE-NEXT: movdqa {{.*#+}} xmm4 = [1065353216,1065353216,1065353216,1065353216]
961 ; X32-SSE-NEXT: paddd %xmm4, %xmm3
962 ; X32-SSE-NEXT: cvttps2dq %xmm3, %xmm3
963 ; X32-SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7]
964 ; X32-SSE-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7]
965 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
966 ; X32-SSE-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
967 ; X32-SSE-NEXT: pslld $23, %xmm1
968 ; X32-SSE-NEXT: paddd %xmm4, %xmm1
969 ; X32-SSE-NEXT: cvttps2dq %xmm1, %xmm1
970 ; X32-SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
971 ; X32-SSE-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
972 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
973 ; X32-SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0]
974 ; X32-SSE-NEXT: pmullw %xmm1, %xmm0
975 ; X32-SSE-NEXT: retl
976 %splat = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
977 %shift = shl <8 x i8> %a, %splat
978 ret <8 x i8> %shift
979 }
981 define <4 x i8> @splatvar_shift_v4i8(<4 x i8> %a, <4 x i8> %b) nounwind {
982 ; SSE2-LABEL: splatvar_shift_v4i8:
983 ; SSE2: # %bb.0:
984 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
985 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
986 ; SSE2-NEXT: pslld $23, %xmm1
987 ; SSE2-NEXT: paddd {{.*}}(%rip), %xmm1
988 ; SSE2-NEXT: cvttps2dq %xmm1, %xmm1
989 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
990 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
991 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
992 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
993 ; SSE2-NEXT: pmuludq %xmm2, %xmm1
994 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
995 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
996 ; SSE2-NEXT: retq
997 ;
998 ; SSE41-LABEL: splatvar_shift_v4i8:
999 ; SSE41: # %bb.0:
1000 ; SSE41-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
1001 ; SSE41-NEXT: pslld $23, %xmm1
1002 ; SSE41-NEXT: paddd {{.*}}(%rip), %xmm1
1003 ; SSE41-NEXT: cvttps2dq %xmm1, %xmm1
1004 ; SSE41-NEXT: pmulld %xmm1, %xmm0
1005 ; SSE41-NEXT: retq
1006 ;
1007 ; AVX1-LABEL: splatvar_shift_v4i8:
1008 ; AVX1: # %bb.0:
1009 ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
1010 ; AVX1-NEXT: vpslld $23, %xmm1, %xmm1
1011 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm1, %xmm1
1012 ; AVX1-NEXT: vcvttps2dq %xmm1, %xmm1
1013 ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0
1014 ; AVX1-NEXT: retq
1015 ;
1016 ; AVX2-LABEL: splatvar_shift_v4i8:
1017 ; AVX2: # %bb.0:
1018 ; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
1019 ; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
1020 ; AVX2-NEXT: retq
1021 ;
1022 ; XOPAVX1-LABEL: splatvar_shift_v4i8:
1023 ; XOPAVX1: # %bb.0:
1024 ; XOPAVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
1025 ; XOPAVX1-NEXT: vpshld %xmm1, %xmm0, %xmm0
1026 ; XOPAVX1-NEXT: retq
1027 ;
1028 ; XOPAVX2-LABEL: splatvar_shift_v4i8:
1029 ; XOPAVX2: # %bb.0:
1030 ; XOPAVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
1031 ; XOPAVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
1032 ; XOPAVX2-NEXT: retq
1033 ;
1034 ; AVX512-LABEL: splatvar_shift_v4i8:
1035 ; AVX512: # %bb.0:
1036 ; AVX512-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
1037 ; AVX512-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
1038 ; AVX512-NEXT: retq
1039 ;
1040 ; AVX512VL-LABEL: splatvar_shift_v4i8:
1041 ; AVX512VL: # %bb.0:
1042 ; AVX512VL-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero,xmm1[0],zero,zero,zero
1043 ; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
1044 ; AVX512VL-NEXT: retq
1045 ;
1046 ; X32-SSE-LABEL: splatvar_shift_v4i8:
1047 ; X32-SSE: # %bb.0:
1048 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
1049 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
1050 ; X32-SSE-NEXT: pslld $23, %xmm1
1051 ; X32-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm1
1052 ; X32-SSE-NEXT: cvttps2dq %xmm1, %xmm1
1053 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
1054 ; X32-SSE-NEXT: pmuludq %xmm1, %xmm0
1055 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
1056 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
1057 ; X32-SSE-NEXT: pmuludq %xmm2, %xmm1
1058 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
1059 ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1060 ; X32-SSE-NEXT: retl
1061 %splat = shufflevector <4 x i8> %b, <4 x i8> undef, <4 x i32> zeroinitializer
1062 %shift = shl <4 x i8> %a, %splat
1063 ret <4 x i8> %shift
1064 }
1066 define <2 x i8> @splatvar_shift_v2i8(<2 x i8> %a, <2 x i8> %b) nounwind {
1067 ; SSE2-LABEL: splatvar_shift_v2i8:
1068 ; SSE2: # %bb.0:
1069 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
1070 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm1
1071 ; SSE2-NEXT: movdqa %xmm0, %xmm2
1072 ; SSE2-NEXT: psllq %xmm1, %xmm2
1073 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
1074 ; SSE2-NEXT: psllq %xmm1, %xmm0
1075 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
1076 ; SSE2-NEXT: retq
1077 ;
1078 ; SSE41-LABEL: splatvar_shift_v2i8:
1079 ; SSE41: # %bb.0:
1080 ; SSE41-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[0],zero,zero,zero,zero,zero,zero,zero
1081 ; SSE41-NEXT: movdqa %xmm0, %xmm2
1082 ; SSE41-NEXT: psllq %xmm1, %xmm2
1083 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
1084 ; SSE41-NEXT: psllq %xmm1, %xmm0
1085 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
1086 ; SSE41-NEXT: retq
1087 ;
1088 ; AVX1-LABEL: splatvar_shift_v2i8:
1089 ; AVX1: # %bb.0:
1090 ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[0],zero,zero,zero,zero,zero,zero,zero
1091 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm2
1092 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
1093 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0
1094 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
1095 ; AVX1-NEXT: retq
1096 ;
1097 ; AVX2-LABEL: splatvar_shift_v2i8:
1098 ; AVX2: # %bb.0:
1099 ; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[0],zero,zero,zero,zero,zero,zero,zero
1100 ; AVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
1101 ; AVX2-NEXT: retq
1102 ;
1103 ; XOPAVX1-LABEL: splatvar_shift_v2i8:
1104 ; XOPAVX1: # %bb.0:
1105 ; XOPAVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[0],zero,zero,zero,zero,zero,zero,zero
1106 ; XOPAVX1-NEXT: vpshlq %xmm1, %xmm0, %xmm0
1107 ; XOPAVX1-NEXT: retq
1108 ;
1109 ; XOPAVX2-LABEL: splatvar_shift_v2i8:
1110 ; XOPAVX2: # %bb.0:
1111 ; XOPAVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[0],zero,zero,zero,zero,zero,zero,zero
1112 ; XOPAVX2-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
1113 ; XOPAVX2-NEXT: retq
1114 ;
1115 ; AVX512-LABEL: splatvar_shift_v2i8:
1116 ; AVX512: # %bb.0:
1117 ; AVX512-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[0],zero,zero,zero,zero,zero,zero,zero
1118 ; AVX512-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
1119 ; AVX512-NEXT: retq
1120 ;
1121 ; AVX512VL-LABEL: splatvar_shift_v2i8:
1122 ; AVX512VL: # %bb.0:
1123 ; AVX512VL-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[0],zero,zero,zero,zero,zero,zero,zero
1124 ; AVX512VL-NEXT: vpsllvq %xmm1, %xmm0, %xmm0
1125 ; AVX512VL-NEXT: retq
1126 ;
1127 ; X32-SSE-LABEL: splatvar_shift_v2i8:
1128 ; X32-SSE: # %bb.0:
1129 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
1130 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
1131 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
1132 ; X32-SSE-NEXT: psllq %xmm1, %xmm2
1133 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
1134 ; X32-SSE-NEXT: psllq %xmm1, %xmm0
1135 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
1136 ; X32-SSE-NEXT: retl
1137 %splat = shufflevector <2 x i8> %b, <2 x i8> undef, <2 x i32> zeroinitializer
1138 %shift = shl <2 x i8> %a, %splat
1139 ret <2 x i8> %shift
1140 }
1142 ;
1143 ; Constant Shifts
1144 ;
1146 define <2 x i32> @constant_shift_v2i32(<2 x i32> %a) nounwind {
1147 ; SSE2-LABEL: constant_shift_v2i32:
1148 ; SSE2: # %bb.0:
1149 ; SSE2-NEXT: movdqa %xmm0, %xmm1
1150 ; SSE2-NEXT: psllq $4, %xmm1
1151 ; SSE2-NEXT: psllq $5, %xmm0
1152 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1153 ; SSE2-NEXT: retq
1154 ;
1155 ; SSE41-LABEL: constant_shift_v2i32:
1156 ; SSE41: # %bb.0:
1157 ; SSE41-NEXT: movdqa %xmm0, %xmm1
1158 ; SSE41-NEXT: psllq $5, %xmm1
1159 ; SSE41-NEXT: psllq $4, %xmm0
1160 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
1161 ; SSE41-NEXT: retq
1162 ;
1163 ; AVX1-LABEL: constant_shift_v2i32:
1164 ; AVX1: # %bb.0:
1165 ; AVX1-NEXT: vpsllq $5, %xmm0, %xmm1
1166 ; AVX1-NEXT: vpsllq $4, %xmm0, %xmm0
1167 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
1168 ; AVX1-NEXT: retq
1169 ;
1170 ; AVX2-LABEL: constant_shift_v2i32:
1171 ; AVX2: # %bb.0:
1172 ; AVX2-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1173 ; AVX2-NEXT: retq
1174 ;
1175 ; XOPAVX1-LABEL: constant_shift_v2i32:
1176 ; XOPAVX1: # %bb.0:
1177 ; XOPAVX1-NEXT: vpshlq {{.*}}(%rip), %xmm0, %xmm0
1178 ; XOPAVX1-NEXT: retq
1179 ;
1180 ; XOPAVX2-LABEL: constant_shift_v2i32:
1181 ; XOPAVX2: # %bb.0:
1182 ; XOPAVX2-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1183 ; XOPAVX2-NEXT: retq
1184 ;
1185 ; AVX512-LABEL: constant_shift_v2i32:
1186 ; AVX512: # %bb.0:
1187 ; AVX512-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1188 ; AVX512-NEXT: retq
1189 ;
1190 ; AVX512VL-LABEL: constant_shift_v2i32:
1191 ; AVX512VL: # %bb.0:
1192 ; AVX512VL-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1193 ; AVX512VL-NEXT: retq
1194 ;
1195 ; X32-SSE-LABEL: constant_shift_v2i32:
1196 ; X32-SSE: # %bb.0:
1197 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
1198 ; X32-SSE-NEXT: psllq $4, %xmm1
1199 ; X32-SSE-NEXT: psllq $5, %xmm0
1200 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1201 ; X32-SSE-NEXT: retl
1202 %shift = shl <2 x i32> %a, <i32 4, i32 5>
1203 ret <2 x i32> %shift
1204 }
1206 define <4 x i16> @constant_shift_v4i16(<4 x i16> %a) nounwind {
1207 ; SSE2-LABEL: constant_shift_v4i16:
1208 ; SSE2: # %bb.0:
1209 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,2,4,8]
1210 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
1211 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
1212 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
1213 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
1214 ; SSE2-NEXT: pmuludq %xmm2, %xmm1
1215 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
1216 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1217 ; SSE2-NEXT: retq
1218 ;
1219 ; SSE41-LABEL: constant_shift_v4i16:
1220 ; SSE41: # %bb.0:
1221 ; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
1222 ; SSE41-NEXT: retq
1223 ;
1224 ; AVX1-LABEL: constant_shift_v4i16:
1225 ; AVX1: # %bb.0:
1226 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
1227 ; AVX1-NEXT: retq
1228 ;
1229 ; AVX2-LABEL: constant_shift_v4i16:
1230 ; AVX2: # %bb.0:
1231 ; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
1232 ; AVX2-NEXT: retq
1233 ;
1234 ; XOPAVX1-LABEL: constant_shift_v4i16:
1235 ; XOPAVX1: # %bb.0:
1236 ; XOPAVX1-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm0
1237 ; XOPAVX1-NEXT: retq
1238 ;
1239 ; XOPAVX2-LABEL: constant_shift_v4i16:
1240 ; XOPAVX2: # %bb.0:
1241 ; XOPAVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
1242 ; XOPAVX2-NEXT: retq
1243 ;
1244 ; AVX512-LABEL: constant_shift_v4i16:
1245 ; AVX512: # %bb.0:
1246 ; AVX512-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
1247 ; AVX512-NEXT: retq
1248 ;
1249 ; AVX512VL-LABEL: constant_shift_v4i16:
1250 ; AVX512VL: # %bb.0:
1251 ; AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
1252 ; AVX512VL-NEXT: retq
1253 ;
1254 ; X32-SSE-LABEL: constant_shift_v4i16:
1255 ; X32-SSE: # %bb.0:
1256 ; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,4,8]
1257 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
1258 ; X32-SSE-NEXT: pmuludq %xmm1, %xmm0
1259 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
1260 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
1261 ; X32-SSE-NEXT: pmuludq %xmm2, %xmm1
1262 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
1263 ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1264 ; X32-SSE-NEXT: retl
1265 %shift = shl <4 x i16> %a, <i16 0, i16 1, i16 2, i16 3>
1266 ret <4 x i16> %shift
1267 }
1269 define <2 x i16> @constant_shift_v2i16(<2 x i16> %a) nounwind {
1270 ; SSE2-LABEL: constant_shift_v2i16:
1271 ; SSE2: # %bb.0:
1272 ; SSE2-NEXT: movdqa %xmm0, %xmm1
1273 ; SSE2-NEXT: psllq $2, %xmm1
1274 ; SSE2-NEXT: psllq $3, %xmm0
1275 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1276 ; SSE2-NEXT: retq
1277 ;
1278 ; SSE41-LABEL: constant_shift_v2i16:
1279 ; SSE41: # %bb.0:
1280 ; SSE41-NEXT: movdqa %xmm0, %xmm1
1281 ; SSE41-NEXT: psllq $3, %xmm1
1282 ; SSE41-NEXT: psllq $2, %xmm0
1283 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
1284 ; SSE41-NEXT: retq
1285 ;
1286 ; AVX1-LABEL: constant_shift_v2i16:
1287 ; AVX1: # %bb.0:
1288 ; AVX1-NEXT: vpsllq $3, %xmm0, %xmm1
1289 ; AVX1-NEXT: vpsllq $2, %xmm0, %xmm0
1290 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
1291 ; AVX1-NEXT: retq
1292 ;
1293 ; AVX2-LABEL: constant_shift_v2i16:
1294 ; AVX2: # %bb.0:
1295 ; AVX2-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1296 ; AVX2-NEXT: retq
1297 ;
1298 ; XOPAVX1-LABEL: constant_shift_v2i16:
1299 ; XOPAVX1: # %bb.0:
1300 ; XOPAVX1-NEXT: vpshlq {{.*}}(%rip), %xmm0, %xmm0
1301 ; XOPAVX1-NEXT: retq
1302 ;
1303 ; XOPAVX2-LABEL: constant_shift_v2i16:
1304 ; XOPAVX2: # %bb.0:
1305 ; XOPAVX2-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1306 ; XOPAVX2-NEXT: retq
1307 ;
1308 ; AVX512-LABEL: constant_shift_v2i16:
1309 ; AVX512: # %bb.0:
1310 ; AVX512-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1311 ; AVX512-NEXT: retq
1312 ;
1313 ; AVX512VL-LABEL: constant_shift_v2i16:
1314 ; AVX512VL: # %bb.0:
1315 ; AVX512VL-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1316 ; AVX512VL-NEXT: retq
1317 ;
1318 ; X32-SSE-LABEL: constant_shift_v2i16:
1319 ; X32-SSE: # %bb.0:
1320 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
1321 ; X32-SSE-NEXT: psllq $2, %xmm1
1322 ; X32-SSE-NEXT: psllq $3, %xmm0
1323 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1324 ; X32-SSE-NEXT: retl
1325 %shift = shl <2 x i16> %a, <i16 2, i16 3>
1326 ret <2 x i16> %shift
1327 }
1329 define <8 x i8> @constant_shift_v8i8(<8 x i8> %a) nounwind {
1330 ; SSE-LABEL: constant_shift_v8i8:
1331 ; SSE: # %bb.0:
1332 ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
1333 ; SSE-NEXT: retq
1334 ;
1335 ; AVX-LABEL: constant_shift_v8i8:
1336 ; AVX: # %bb.0:
1337 ; AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
1338 ; AVX-NEXT: retq
1339 ;
1340 ; XOP-LABEL: constant_shift_v8i8:
1341 ; XOP: # %bb.0:
1342 ; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
1343 ; XOP-NEXT: retq
1344 ;
1345 ; AVX512DQ-LABEL: constant_shift_v8i8:
1346 ; AVX512DQ: # %bb.0:
1347 ; AVX512DQ-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
1348 ; AVX512DQ-NEXT: retq
1349 ;
1350 ; AVX512BW-LABEL: constant_shift_v8i8:
1351 ; AVX512BW: # %bb.0:
1352 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
1353 ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7]
1354 ; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
1355 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
1356 ; AVX512BW-NEXT: vzeroupper
1357 ; AVX512BW-NEXT: retq
1358 ;
1359 ; AVX512DQVL-LABEL: constant_shift_v8i8:
1360 ; AVX512DQVL: # %bb.0:
1361 ; AVX512DQVL-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
1362 ; AVX512DQVL-NEXT: retq
1363 ;
1364 ; AVX512BWVL-LABEL: constant_shift_v8i8:
1365 ; AVX512BWVL: # %bb.0:
1366 ; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %xmm0, %xmm0
1367 ; AVX512BWVL-NEXT: retq
1368 ;
1369 ; X32-SSE-LABEL: constant_shift_v8i8:
1370 ; X32-SSE: # %bb.0:
1371 ; X32-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0
1372 ; X32-SSE-NEXT: retl
1373 %shift = shl <8 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>
1374 ret <8 x i8> %shift
1375 }
1377 define <4 x i8> @constant_shift_v4i8(<4 x i8> %a) nounwind {
1378 ; SSE2-LABEL: constant_shift_v4i8:
1379 ; SSE2: # %bb.0:
1380 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [1,2,4,8]
1381 ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
1382 ; SSE2-NEXT: pmuludq %xmm1, %xmm0
1383 ; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
1384 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
1385 ; SSE2-NEXT: pmuludq %xmm2, %xmm1
1386 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
1387 ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1388 ; SSE2-NEXT: retq
1389 ;
1390 ; SSE41-LABEL: constant_shift_v4i8:
1391 ; SSE41: # %bb.0:
1392 ; SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
1393 ; SSE41-NEXT: retq
1394 ;
1395 ; AVX1-LABEL: constant_shift_v4i8:
1396 ; AVX1: # %bb.0:
1397 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
1398 ; AVX1-NEXT: retq
1399 ;
1400 ; AVX2-LABEL: constant_shift_v4i8:
1401 ; AVX2: # %bb.0:
1402 ; AVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
1403 ; AVX2-NEXT: retq
1404 ;
1405 ; XOPAVX1-LABEL: constant_shift_v4i8:
1406 ; XOPAVX1: # %bb.0:
1407 ; XOPAVX1-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm0
1408 ; XOPAVX1-NEXT: retq
1409 ;
1410 ; XOPAVX2-LABEL: constant_shift_v4i8:
1411 ; XOPAVX2: # %bb.0:
1412 ; XOPAVX2-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
1413 ; XOPAVX2-NEXT: retq
1414 ;
1415 ; AVX512-LABEL: constant_shift_v4i8:
1416 ; AVX512: # %bb.0:
1417 ; AVX512-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
1418 ; AVX512-NEXT: retq
1419 ;
1420 ; AVX512VL-LABEL: constant_shift_v4i8:
1421 ; AVX512VL: # %bb.0:
1422 ; AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
1423 ; AVX512VL-NEXT: retq
1424 ;
1425 ; X32-SSE-LABEL: constant_shift_v4i8:
1426 ; X32-SSE: # %bb.0:
1427 ; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [1,2,4,8]
1428 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
1429 ; X32-SSE-NEXT: pmuludq %xmm1, %xmm0
1430 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
1431 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
1432 ; X32-SSE-NEXT: pmuludq %xmm2, %xmm1
1433 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
1434 ; X32-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1435 ; X32-SSE-NEXT: retl
1436 %shift = shl <4 x i8> %a, <i8 0, i8 1, i8 2, i8 3>
1437 ret <4 x i8> %shift
1438 }
1440 define <2 x i8> @constant_shift_v2i8(<2 x i8> %a) nounwind {
1441 ; SSE2-LABEL: constant_shift_v2i8:
1442 ; SSE2: # %bb.0:
1443 ; SSE2-NEXT: movdqa %xmm0, %xmm1
1444 ; SSE2-NEXT: psllq $2, %xmm1
1445 ; SSE2-NEXT: psllq $3, %xmm0
1446 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1447 ; SSE2-NEXT: retq
1448 ;
1449 ; SSE41-LABEL: constant_shift_v2i8:
1450 ; SSE41: # %bb.0:
1451 ; SSE41-NEXT: movdqa %xmm0, %xmm1
1452 ; SSE41-NEXT: psllq $3, %xmm1
1453 ; SSE41-NEXT: psllq $2, %xmm0
1454 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
1455 ; SSE41-NEXT: retq
1456 ;
1457 ; AVX1-LABEL: constant_shift_v2i8:
1458 ; AVX1: # %bb.0:
1459 ; AVX1-NEXT: vpsllq $3, %xmm0, %xmm1
1460 ; AVX1-NEXT: vpsllq $2, %xmm0, %xmm0
1461 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
1462 ; AVX1-NEXT: retq
1463 ;
1464 ; AVX2-LABEL: constant_shift_v2i8:
1465 ; AVX2: # %bb.0:
1466 ; AVX2-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1467 ; AVX2-NEXT: retq
1468 ;
1469 ; XOPAVX1-LABEL: constant_shift_v2i8:
1470 ; XOPAVX1: # %bb.0:
1471 ; XOPAVX1-NEXT: vpshlq {{.*}}(%rip), %xmm0, %xmm0
1472 ; XOPAVX1-NEXT: retq
1473 ;
1474 ; XOPAVX2-LABEL: constant_shift_v2i8:
1475 ; XOPAVX2: # %bb.0:
1476 ; XOPAVX2-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1477 ; XOPAVX2-NEXT: retq
1478 ;
1479 ; AVX512-LABEL: constant_shift_v2i8:
1480 ; AVX512: # %bb.0:
1481 ; AVX512-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1482 ; AVX512-NEXT: retq
1483 ;
1484 ; AVX512VL-LABEL: constant_shift_v2i8:
1485 ; AVX512VL: # %bb.0:
1486 ; AVX512VL-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0
1487 ; AVX512VL-NEXT: retq
1488 ;
1489 ; X32-SSE-LABEL: constant_shift_v2i8:
1490 ; X32-SSE: # %bb.0:
1491 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
1492 ; X32-SSE-NEXT: psllq $2, %xmm1
1493 ; X32-SSE-NEXT: psllq $3, %xmm0
1494 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
1495 ; X32-SSE-NEXT: retl
1496 %shift = shl <2 x i8> %a, <i8 2, i8 3>
1497 ret <2 x i8> %shift
1498 }
1500 ;
1501 ; Uniform Constant Shifts
1502 ;
1504 define <2 x i32> @splatconstant_shift_v2i32(<2 x i32> %a) nounwind {
1505 ; SSE-LABEL: splatconstant_shift_v2i32:
1506 ; SSE: # %bb.0:
1507 ; SSE-NEXT: psllq $5, %xmm0
1508 ; SSE-NEXT: retq
1509 ;
1510 ; AVX-LABEL: splatconstant_shift_v2i32:
1511 ; AVX: # %bb.0:
1512 ; AVX-NEXT: vpsllq $5, %xmm0, %xmm0
1513 ; AVX-NEXT: retq
1514 ;
1515 ; XOP-LABEL: splatconstant_shift_v2i32:
1516 ; XOP: # %bb.0:
1517 ; XOP-NEXT: vpsllq $5, %xmm0, %xmm0
1518 ; XOP-NEXT: retq
1519 ;
1520 ; AVX512-LABEL: splatconstant_shift_v2i32:
1521 ; AVX512: # %bb.0:
1522 ; AVX512-NEXT: vpsllq $5, %xmm0, %xmm0
1523 ; AVX512-NEXT: retq
1524 ;
1525 ; AVX512VL-LABEL: splatconstant_shift_v2i32:
1526 ; AVX512VL: # %bb.0:
1527 ; AVX512VL-NEXT: vpsllq $5, %xmm0, %xmm0
1528 ; AVX512VL-NEXT: retq
1529 ;
1530 ; X32-SSE-LABEL: splatconstant_shift_v2i32:
1531 ; X32-SSE: # %bb.0:
1532 ; X32-SSE-NEXT: psllq $5, %xmm0
1533 ; X32-SSE-NEXT: retl
1534 %shift = shl <2 x i32> %a, <i32 5, i32 5>
1535 ret <2 x i32> %shift
1536 }
1538 define <4 x i16> @splatconstant_shift_v4i16(<4 x i16> %a) nounwind {
1539 ; SSE-LABEL: splatconstant_shift_v4i16:
1540 ; SSE: # %bb.0:
1541 ; SSE-NEXT: pslld $3, %xmm0
1542 ; SSE-NEXT: retq
1543 ;
1544 ; AVX-LABEL: splatconstant_shift_v4i16:
1545 ; AVX: # %bb.0:
1546 ; AVX-NEXT: vpslld $3, %xmm0, %xmm0
1547 ; AVX-NEXT: retq
1548 ;
1549 ; XOP-LABEL: splatconstant_shift_v4i16:
1550 ; XOP: # %bb.0:
1551 ; XOP-NEXT: vpslld $3, %xmm0, %xmm0
1552 ; XOP-NEXT: retq
1553 ;
1554 ; AVX512-LABEL: splatconstant_shift_v4i16:
1555 ; AVX512: # %bb.0:
1556 ; AVX512-NEXT: vpslld $3, %xmm0, %xmm0
1557 ; AVX512-NEXT: retq
1558 ;
1559 ; AVX512VL-LABEL: splatconstant_shift_v4i16:
1560 ; AVX512VL: # %bb.0:
1561 ; AVX512VL-NEXT: vpslld $3, %xmm0, %xmm0
1562 ; AVX512VL-NEXT: retq
1563 ;
1564 ; X32-SSE-LABEL: splatconstant_shift_v4i16:
1565 ; X32-SSE: # %bb.0:
1566 ; X32-SSE-NEXT: pslld $3, %xmm0
1567 ; X32-SSE-NEXT: retl
1568 %shift = shl <4 x i16> %a, <i16 3, i16 3, i16 3, i16 3>
1569 ret <4 x i16> %shift
1570 }
1572 define <2 x i16> @splatconstant_shift_v2i16(<2 x i16> %a) nounwind {
1573 ; SSE-LABEL: splatconstant_shift_v2i16:
1574 ; SSE: # %bb.0:
1575 ; SSE-NEXT: psllq $3, %xmm0
1576 ; SSE-NEXT: retq
1577 ;
1578 ; AVX-LABEL: splatconstant_shift_v2i16:
1579 ; AVX: # %bb.0:
1580 ; AVX-NEXT: vpsllq $3, %xmm0, %xmm0
1581 ; AVX-NEXT: retq
1582 ;
1583 ; XOP-LABEL: splatconstant_shift_v2i16:
1584 ; XOP: # %bb.0:
1585 ; XOP-NEXT: vpsllq $3, %xmm0, %xmm0
1586 ; XOP-NEXT: retq
1587 ;
1588 ; AVX512-LABEL: splatconstant_shift_v2i16:
1589 ; AVX512: # %bb.0:
1590 ; AVX512-NEXT: vpsllq $3, %xmm0, %xmm0
1591 ; AVX512-NEXT: retq
1592 ;
1593 ; AVX512VL-LABEL: splatconstant_shift_v2i16:
1594 ; AVX512VL: # %bb.0:
1595 ; AVX512VL-NEXT: vpsllq $3, %xmm0, %xmm0
1596 ; AVX512VL-NEXT: retq
1597 ;
1598 ; X32-SSE-LABEL: splatconstant_shift_v2i16:
1599 ; X32-SSE: # %bb.0:
1600 ; X32-SSE-NEXT: psllq $3, %xmm0
1601 ; X32-SSE-NEXT: retl
1602 %shift = shl <2 x i16> %a, <i16 3, i16 3>
1603 ret <2 x i16> %shift
1604 }
1606 define <8 x i8> @splatconstant_shift_v8i8(<8 x i8> %a) nounwind {
1607 ; SSE-LABEL: splatconstant_shift_v8i8:
1608 ; SSE: # %bb.0:
1609 ; SSE-NEXT: psllw $3, %xmm0
1610 ; SSE-NEXT: retq
1611 ;
1612 ; AVX-LABEL: splatconstant_shift_v8i8:
1613 ; AVX: # %bb.0:
1614 ; AVX-NEXT: vpsllw $3, %xmm0, %xmm0
1615 ; AVX-NEXT: retq
1616 ;
1617 ; XOP-LABEL: splatconstant_shift_v8i8:
1618 ; XOP: # %bb.0:
1619 ; XOP-NEXT: vpsllw $3, %xmm0, %xmm0
1620 ; XOP-NEXT: retq
1621 ;
1622 ; AVX512-LABEL: splatconstant_shift_v8i8:
1623 ; AVX512: # %bb.0:
1624 ; AVX512-NEXT: vpsllw $3, %xmm0, %xmm0
1625 ; AVX512-NEXT: retq
1626 ;
1627 ; AVX512VL-LABEL: splatconstant_shift_v8i8:
1628 ; AVX512VL: # %bb.0:
1629 ; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0
1630 ; AVX512VL-NEXT: retq
1631 ;
1632 ; X32-SSE-LABEL: splatconstant_shift_v8i8:
1633 ; X32-SSE: # %bb.0:
1634 ; X32-SSE-NEXT: psllw $3, %xmm0
1635 ; X32-SSE-NEXT: retl
1636 %shift = shl <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
1637 ret <8 x i8> %shift
1638 }
1640 define <4 x i8> @splatconstant_shift_v4i8(<4 x i8> %a) nounwind {
1641 ; SSE-LABEL: splatconstant_shift_v4i8:
1642 ; SSE: # %bb.0:
1643 ; SSE-NEXT: pslld $3, %xmm0
1644 ; SSE-NEXT: retq
1645 ;
1646 ; AVX-LABEL: splatconstant_shift_v4i8:
1647 ; AVX: # %bb.0:
1648 ; AVX-NEXT: vpslld $3, %xmm0, %xmm0
1649 ; AVX-NEXT: retq
1650 ;
1651 ; XOP-LABEL: splatconstant_shift_v4i8:
1652 ; XOP: # %bb.0:
1653 ; XOP-NEXT: vpslld $3, %xmm0, %xmm0
1654 ; XOP-NEXT: retq
1655 ;
1656 ; AVX512-LABEL: splatconstant_shift_v4i8:
1657 ; AVX512: # %bb.0:
1658 ; AVX512-NEXT: vpslld $3, %xmm0, %xmm0
1659 ; AVX512-NEXT: retq
1660 ;
1661 ; AVX512VL-LABEL: splatconstant_shift_v4i8:
1662 ; AVX512VL: # %bb.0:
1663 ; AVX512VL-NEXT: vpslld $3, %xmm0, %xmm0
1664 ; AVX512VL-NEXT: retq
1665 ;
1666 ; X32-SSE-LABEL: splatconstant_shift_v4i8:
1667 ; X32-SSE: # %bb.0:
1668 ; X32-SSE-NEXT: pslld $3, %xmm0
1669 ; X32-SSE-NEXT: retl
1670 %shift = shl <4 x i8> %a, <i8 3, i8 3, i8 3, i8 3>
1671 ret <4 x i8> %shift
1672 }
1674 define <2 x i8> @splatconstant_shift_v2i8(<2 x i8> %a) nounwind {
1675 ; SSE-LABEL: splatconstant_shift_v2i8:
1676 ; SSE: # %bb.0:
1677 ; SSE-NEXT: psllq $3, %xmm0
1678 ; SSE-NEXT: retq
1679 ;
1680 ; AVX-LABEL: splatconstant_shift_v2i8:
1681 ; AVX: # %bb.0:
1682 ; AVX-NEXT: vpsllq $3, %xmm0, %xmm0
1683 ; AVX-NEXT: retq
1684 ;
1685 ; XOP-LABEL: splatconstant_shift_v2i8:
1686 ; XOP: # %bb.0:
1687 ; XOP-NEXT: vpsllq $3, %xmm0, %xmm0
1688 ; XOP-NEXT: retq
1689 ;
1690 ; AVX512-LABEL: splatconstant_shift_v2i8:
1691 ; AVX512: # %bb.0:
1692 ; AVX512-NEXT: vpsllq $3, %xmm0, %xmm0
1693 ; AVX512-NEXT: retq
1694 ;
1695 ; AVX512VL-LABEL: splatconstant_shift_v2i8:
1696 ; AVX512VL: # %bb.0:
1697 ; AVX512VL-NEXT: vpsllq $3, %xmm0, %xmm0
1698 ; AVX512VL-NEXT: retq
1699 ;
1700 ; X32-SSE-LABEL: splatconstant_shift_v2i8:
1701 ; X32-SSE: # %bb.0:
1702 ; X32-SSE-NEXT: psllq $3, %xmm0
1703 ; X32-SSE-NEXT: retl
1704 %shift = shl <2 x i8> %a, <i8 3, i8 3>
1705 ret <2 x i8> %shift
1706 }