1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X32
3 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=X64
5 ; test vector shifts converted to proper SSE2 vector shifts when the shift
6 ; amounts are the same.
8 define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
10 ; X32: # %bb.0: # %entry
11 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
12 ; X32-NEXT: psrlq $32, %xmm0
13 ; X32-NEXT: movdqa %xmm0, (%eax)
17 ; X64: # %bb.0: # %entry
18 ; X64-NEXT: psrlq $32, %xmm0
19 ; X64-NEXT: movdqa %xmm0, (%rdi)
22 %lshr = lshr <2 x i64> %val, < i64 32, i64 32 >
23 store <2 x i64> %lshr, <2 x i64>* %dst
27 define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
29 ; X32: # %bb.0: # %entry
30 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
31 ; X32-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
32 ; X32-NEXT: psrlq %xmm1, %xmm0
33 ; X32-NEXT: movdqa %xmm0, (%eax)
37 ; X64: # %bb.0: # %entry
38 ; X64-NEXT: movq %rsi, %xmm1
39 ; X64-NEXT: psrlq %xmm1, %xmm0
40 ; X64-NEXT: movdqa %xmm0, (%rdi)
43 %0 = insertelement <2 x i64> undef, i64 %amt, i32 0
44 %1 = insertelement <2 x i64> %0, i64 %amt, i32 1
45 %lshr = lshr <2 x i64> %val, %1
46 store <2 x i64> %lshr, <2 x i64>* %dst
50 define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
52 ; X32: # %bb.0: # %entry
53 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
54 ; X32-NEXT: psrld $17, %xmm0
55 ; X32-NEXT: movdqa %xmm0, (%eax)
59 ; X64: # %bb.0: # %entry
60 ; X64-NEXT: psrld $17, %xmm0
61 ; X64-NEXT: movdqa %xmm0, (%rdi)
64 %lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 >
65 store <4 x i32> %lshr, <4 x i32>* %dst
69 define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
71 ; X32: # %bb.0: # %entry
72 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
73 ; X32-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
74 ; X32-NEXT: psrld %xmm1, %xmm0
75 ; X32-NEXT: movdqa %xmm0, (%eax)
79 ; X64: # %bb.0: # %entry
80 ; X64-NEXT: movd %esi, %xmm1
81 ; X64-NEXT: psrld %xmm1, %xmm0
82 ; X64-NEXT: movdqa %xmm0, (%rdi)
85 %0 = insertelement <4 x i32> undef, i32 %amt, i32 0
86 %1 = insertelement <4 x i32> %0, i32 %amt, i32 1
87 %2 = insertelement <4 x i32> %1, i32 %amt, i32 2
88 %3 = insertelement <4 x i32> %2, i32 %amt, i32 3
89 %lshr = lshr <4 x i32> %val, %3
90 store <4 x i32> %lshr, <4 x i32>* %dst
95 define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
97 ; X32: # %bb.0: # %entry
98 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
99 ; X32-NEXT: psrlw $5, %xmm0
100 ; X32-NEXT: movdqa %xmm0, (%eax)
103 ; X64-LABEL: shift3a:
104 ; X64: # %bb.0: # %entry
105 ; X64-NEXT: psrlw $5, %xmm0
106 ; X64-NEXT: movdqa %xmm0, (%rdi)
109 %lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
110 store <8 x i16> %lshr, <8 x i16>* %dst
114 ; properly zero extend the shift amount
115 define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
116 ; X32-LABEL: shift3b:
117 ; X32: # %bb.0: # %entry
118 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
119 ; X32-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
120 ; X32-NEXT: movd %ecx, %xmm1
121 ; X32-NEXT: psrlw %xmm1, %xmm0
122 ; X32-NEXT: movdqa %xmm0, (%eax)
125 ; X64-LABEL: shift3b:
126 ; X64: # %bb.0: # %entry
127 ; X64-NEXT: movzwl %si, %eax
128 ; X64-NEXT: movd %eax, %xmm1
129 ; X64-NEXT: psrlw %xmm1, %xmm0
130 ; X64-NEXT: movdqa %xmm0, (%rdi)
133 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0
134 %1 = insertelement <8 x i16> %0, i16 %amt, i32 1
135 %2 = insertelement <8 x i16> %1, i16 %amt, i32 2
136 %3 = insertelement <8 x i16> %2, i16 %amt, i32 3
137 %4 = insertelement <8 x i16> %3, i16 %amt, i32 4
138 %5 = insertelement <8 x i16> %4, i16 %amt, i32 5
139 %6 = insertelement <8 x i16> %5, i16 %amt, i32 6
140 %7 = insertelement <8 x i16> %6, i16 %amt, i32 7
141 %lshr = lshr <8 x i16> %val, %7
142 store <8 x i16> %lshr, <8 x i16>* %dst