1 ; RUN: opt < %s -loop-reduce -S | FileCheck %s
3 target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4 target triple = "thumbv6m-arm-none-eabi"
6 ; These are regression tests for
7 ; https://bugs.llvm.org/show_bug.cgi?id=34106
8 ; "ARMTargetLowering::isLegalAddressingMode can accept incorrect
9 ; addressing modes for Thumb1 target"
10 ; https://reviews.llvm.org/D34583
11 ; "[LSR] Narrow search space by filtering non-optimal formulae with the
12 ; same ScaledReg and Scale."
14 ; Due to a bug in ARMTargetLowering::isLegalAddressingMode LSR got
15 ; 4*reg({0,+,-1}) and -4*reg({0,+,-1}) had the same cost for the Thumb1 target.
16 ; Another issue was that LSR got that -1*reg was free for the Thumb1 target.
18 ; Test case 01: -1*reg is not free for the Thumb1 target.
20 ; CHECK-LABEL: @negativeOneCase
23 define i8* @negativeOneCase(i8* returned %a, i8* nocapture readonly %b, i32 %n) nounwind {
25 %add.ptr = getelementptr inbounds i8, i8* %a, i32 -1
28 while.cond: ; preds = %while.cond, %entry
29 %p.0 = phi i8* [ %add.ptr, %entry ], [ %incdec.ptr, %while.cond ]
30 %incdec.ptr = getelementptr inbounds i8, i8* %p.0, i32 1
31 %0 = load i8, i8* %incdec.ptr, align 1
32 %cmp = icmp eq i8 %0, 0
33 br i1 %cmp, label %while.cond2.preheader, label %while.cond
35 while.cond2.preheader: ; preds = %while.cond
38 while.cond2: ; preds = %while.cond2.preheader, %while.body5
39 %b.addr.0 = phi i8* [ %incdec.ptr6, %while.body5 ], [ %b, %while.cond2.preheader ]
40 %n.addr.0 = phi i32 [ %dec, %while.body5 ], [ %n, %while.cond2.preheader ]
41 %p.1 = phi i8* [ %incdec.ptr7, %while.body5 ], [ %incdec.ptr, %while.cond2.preheader ]
42 %cmp3 = icmp eq i32 %n.addr.0, 0
43 br i1 %cmp3, label %while.end8, label %while.body5
45 while.body5: ; preds = %while.cond2
46 %dec = add i32 %n.addr.0, -1
47 %incdec.ptr6 = getelementptr inbounds i8, i8* %b.addr.0, i32 1
48 %1 = load i8, i8* %b.addr.0, align 1
49 %incdec.ptr7 = getelementptr inbounds i8, i8* %p.1, i32 1
50 store i8 %1, i8* %p.1, align 1
53 while.end8: ; preds = %while.cond2
54 %scevgep = getelementptr i8, i8* %incdec.ptr, i32 %n
55 store i8 0, i8* %scevgep, align 1
59 ; Test case 02: 4*reg({0,+,-1}) and -4*reg({0,+,-1}) are not supported for
62 ; CHECK-LABEL: @negativeFourCase
65 define void @negativeFourCase(i8* %ptr1, i32* %ptr2) nounwind {
67 br label %for.cond6.preheader.us.i.i
69 for.cond6.preheader.us.i.i: ; preds = %if.end48.us.i.i, %entry
70 %addr.0108.us.i.i = phi i8* [ %scevgep.i.i, %if.end48.us.i.i ], [ %ptr1, %entry ]
71 %inc49.us.i.i = phi i32 [ %inc50.us.i.i, %if.end48.us.i.i ], [ 0, %entry ]
72 %c1.0104.us.i.i = phi i32* [ %c0.0103.us.i.i, %if.end48.us.i.i ], [ %ptr2, %entry ]
73 %c0.0103.us.i.i = phi i32* [ %c1.0104.us.i.i, %if.end48.us.i.i ], [ %ptr2, %entry ]
74 br label %for.body8.us.i.i
76 if.end48.us.i.i: ; preds = %for.inc.us.i.i
77 %scevgep.i.i = getelementptr i8, i8* %addr.0108.us.i.i, i32 256
78 %inc50.us.i.i = add nuw nsw i32 %inc49.us.i.i, 1
79 %exitcond110.i.i = icmp eq i32 %inc50.us.i.i, 256
80 br i1 %exitcond110.i.i, label %exit.i, label %for.cond6.preheader.us.i.i
82 for.body8.us.i.i: ; preds = %for.inc.us.i.i, %for.cond6.preheader.us.i.i
83 %addr.198.us.i.i = phi i8* [ %addr.0108.us.i.i, %for.cond6.preheader.us.i.i ], [ %incdec.ptr.us.i.i, %for.inc.us.i.i ]
84 %inc.196.us.i.i = phi i32 [ 0, %for.cond6.preheader.us.i.i ], [ %inc.2.us.i.i, %for.inc.us.i.i ]
85 %c.093.us.i.i = phi i32 [ 0, %for.cond6.preheader.us.i.i ], [ %inc43.us.i.i, %for.inc.us.i.i ]
86 %incdec.ptr.us.i.i = getelementptr inbounds i8, i8* %addr.198.us.i.i, i32 1
87 %0 = load i8, i8* %addr.198.us.i.i, align 1
88 %cmp9.us.i.i = icmp eq i8 %0, -1
89 br i1 %cmp9.us.i.i, label %if.end37.us.i.i, label %if.else.us.i.i
91 if.else.us.i.i: ; preds = %for.body8.us.i.i
92 %add12.us.i.i = add nuw nsw i32 %c.093.us.i.i, 1
93 %arrayidx13.us.i.i = getelementptr inbounds i32, i32* %c1.0104.us.i.i, i32 %add12.us.i.i
94 %1 = load i32, i32* %arrayidx13.us.i.i, align 4
95 %arrayidx16.us.i.i = getelementptr inbounds i32, i32* %c1.0104.us.i.i, i32 %c.093.us.i.i
96 %2 = load i32, i32* %arrayidx16.us.i.i, align 4
97 %sub19.us.i.i = add nsw i32 %c.093.us.i.i, -1
98 %arrayidx20.us.i.i = getelementptr inbounds i32, i32* %c1.0104.us.i.i, i32 %sub19.us.i.i
99 %3 = load i32, i32* %arrayidx20.us.i.i, align 4
100 br label %if.end37.us.i.i
102 if.end37.us.i.i: ; preds = %if.else.us.i.i, %for.body8.us.i.i
103 %4 = phi i32 [ %3, %if.else.us.i.i ], [ 0, %for.body8.us.i.i ]
104 %arrayidx36.us.i.i = getelementptr inbounds i32, i32* %c0.0103.us.i.i, i32 %c.093.us.i.i
105 store i32 %4, i32* %arrayidx36.us.i.i, align 4
106 %inc.us.i.i = add nsw i32 %inc.196.us.i.i, 1
107 %cmp38.us.i.i = icmp sgt i32 %inc.196.us.i.i, 6
108 br i1 %cmp38.us.i.i, label %if.then40.us.i.i, label %for.inc.us.i.i
110 if.then40.us.i.i: ; preds = %if.end37.us.i.i
111 br label %for.inc.us.i.i
113 for.inc.us.i.i: ; preds = %if.then40.us.i.i, %if.end37.us.i.i
114 %inc.2.us.i.i = phi i32 [ 0, %if.then40.us.i.i ], [ %inc.us.i.i, %if.end37.us.i.i ]
115 %inc43.us.i.i = add nuw nsw i32 %c.093.us.i.i, 1
116 %exitcond.i.i = icmp eq i32 %inc43.us.i.i, 256
117 br i1 %exitcond.i.i, label %if.end48.us.i.i, label %for.body8.us.i.i
119 exit.i: ; preds = %if.end48.us.i.i