test/tools/llvm-mca/X86/BdVer2/clear-super-register-1.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=100 -resource-pressure=false -timeline -timeline-max-iterations=2 < %s | FileCheck %s
   3
   4 ## Sets register RAX.
   5 imulq $5, %rcx, %rax
   6
   7 ## Kills the previous definition of RAX.
   8 ## The upper portion of RAX is cleared.
   9 lzcnt %ecx, %eax
  10
  11 ## The AND can start immediately after the LZCNT.
  12 ## It doesn't need to wait for the IMUL.
  13 and   %rcx, %rax
  14 bsf   %rax, %rcx
  15
  16 # CHECK:      Iterations:        100
  17 # CHECK-NEXT: Instructions:      400
  18 # CHECK-NEXT: Total Cycles:      900
  19 # CHECK-NEXT: Total uOps:        1000
  20
  21 # CHECK:      Dispatch Width:    4
  22 # CHECK-NEXT: uOps Per Cycle:    1.11
  23 # CHECK-NEXT: IPC:               0.44
  24 # CHECK-NEXT: Block RThroughput: 4.0
  25
  26 # CHECK:      Instruction Info:
  27 # CHECK-NEXT: [1]: #uOps
  28 # CHECK-NEXT: [2]: Latency
  29 # CHECK-NEXT: [3]: RThroughput
  30 # CHECK-NEXT: [4]: MayLoad
  31 # CHECK-NEXT: [5]: MayStore
  32 # CHECK-NEXT: [6]: HasSideEffects (U)
  33
  34 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  35 # CHECK-NEXT:  1      6     4.00                        imulq   $5, %rcx, %rax
  36 # CHECK-NEXT:  2      2     2.00                        lzcntl  %ecx, %eax
  37 # CHECK-NEXT:  1      1     1.00                        andq    %rcx, %rax
  38 # CHECK-NEXT:  6      3     3.00                        bsfq    %rax, %rcx
  39
  40 # CHECK:      Timeline view:
  41 # CHECK-NEXT:                     01234567
  42 # CHECK-NEXT: Index     0123456789
  43
  44 # CHECK:      [0,0]     DeeeeeeER .    . .   imulq      $5, %rcx, %rax
  45 # CHECK-NEXT: [0,1]     DeeE----R .    . .   lzcntl     %ecx, %eax
  46 # CHECK-NEXT: [0,2]     D==eE---R .    . .   andq       %rcx, %rax
  47 # CHECK-NEXT: [0,3]     .D==eeeER .    . .   bsfq       %rax, %rcx
  48 # CHECK-NEXT: [1,0]     . D====eeeeeeER. .   imulq      $5, %rcx, %rax
  49 # CHECK-NEXT: [1,1]     .  D======eeE-R. .   lzcntl     %ecx, %eax
  50 # CHECK-NEXT: [1,2]     .  D========eER. .   andq       %rcx, %rax
  51 # CHECK-NEXT: [1,3]     .   D========eeeER   bsfq       %rax, %rcx
  52
  53 # CHECK:      Average Wait times (based on the timeline view):
  54 # CHECK-NEXT: [0]: Executions
  55 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  56 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  57 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
  58
  59 # CHECK:            [0]    [1]    [2]    [3]
  60 # CHECK-NEXT: 0.     2     3.0    0.5    0.0       imulq        $5, %rcx, %rax
  61 # CHECK-NEXT: 1.     2     4.0    2.0    2.5       lzcntl       %ecx, %eax
  62 # CHECK-NEXT: 2.     2     6.0    0.0    1.5       andq %rcx, %rax
  63 # CHECK-NEXT: 3.     2     6.0    0.0    0.0       bsfq %rax, %rcx