[ARM] Adjust how NEON shifts are lowered
[llvm-core.git] / test / tools / llvm-mca / X86 / BdVer2 / partial-reg-update-2.s
blobfe8b159edcca7e749e0ac31bceb237f725bc5f44
1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=bdver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
4 imul %rax, %rbx
5 lzcnt %ax, %bx
6 add %ecx, %ebx
8 # CHECK: Iterations: 1
9 # CHECK-NEXT: Instructions: 3
10 # CHECK-NEXT: Total Cycles: 11
11 # CHECK-NEXT: Total uOps: 4
13 # CHECK: Dispatch Width: 4
14 # CHECK-NEXT: uOps Per Cycle: 0.36
15 # CHECK-NEXT: IPC: 0.27
16 # CHECK-NEXT: Block RThroughput: 4.0
18 # CHECK: Instruction Info:
19 # CHECK-NEXT: [1]: #uOps
20 # CHECK-NEXT: [2]: Latency
21 # CHECK-NEXT: [3]: RThroughput
22 # CHECK-NEXT: [4]: MayLoad
23 # CHECK-NEXT: [5]: MayStore
24 # CHECK-NEXT: [6]: HasSideEffects (U)
26 # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
27 # CHECK-NEXT: 1 6 4.00 imulq %rax, %rbx
28 # CHECK-NEXT: 2 2 2.00 lzcntw %ax, %bx
29 # CHECK-NEXT: 1 1 1.00 addl %ecx, %ebx
31 # CHECK: Timeline view:
32 # CHECK-NEXT: 0
33 # CHECK-NEXT: Index 0123456789
35 # CHECK: [0,0] DeeeeeeER . imulq %rax, %rbx
36 # CHECK-NEXT: [0,1] D=====eeER. lzcntw %ax, %bx
37 # CHECK-NEXT: [0,2] D=======eER addl %ecx, %ebx
39 # CHECK: Average Wait times (based on the timeline view):
40 # CHECK-NEXT: [0]: Executions
41 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
42 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
43 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
45 # CHECK: [0] [1] [2] [3]
46 # CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rbx
47 # CHECK-NEXT: 1. 1 6.0 0.0 0.0 lzcntw %ax, %bx
48 # CHECK-NEXT: 2. 1 8.0 0.0 0.0 addl %ecx, %ebx